From: hadaq <hadaq>
Date: Fri, 10 Aug 2012 09:28:24 +0000 (+0000)
Subject: bug fix - cu
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=458af4bf13c8c67d08ea436796d0f55343ccf7e7;p=trb3.git

bug fix - cu
---

diff --git a/tdc_releases/tdc_v0.4/TDC.vhd b/tdc_releases/tdc_v0.4/TDC.vhd
index 067d601..2d87aa8 100644
--- a/tdc_releases/tdc_v0.4/TDC.vhd
+++ b/tdc_releases/tdc_v0.4/TDC.vhd
@@ -146,10 +146,10 @@ architecture TDC of TDC is
 -- Slow Control Signals
   signal ch_en_i                  : std_logic_vector(63 downto 0);
   signal trigger_win_en           : std_logic;
-  signal readout_trigger_mode     : std_logic := '1';  -- readout trigger
-                                                       -- 1: with trigger
-                                                       -- 0: triggerless
-  signal readout_trigger_mode_200 : std_logic := '1';  -- trigger mode signal synchronised to the coarse counter clk
+  signal readout_trigger_mode     : std_logic;  -- readout trigger
+                                                -- 1: with trigger
+                                                -- 0: triggerless
+  signal readout_trigger_mode_200 : std_logic;  -- trigger mode signal synchronised to the coarse counter clk
   signal logic_anal_control       : std_logic_vector(3 downto 0);
   signal debug_mode_en_i          : std_logic;
 
@@ -552,7 +552,7 @@ begin
           data_wr_reg   <= '1';
           stop_status_i <= '0';
         else
---          data_out_reg <= (others => '1');
+          data_out_reg <= (others => '1');
           data_wr_reg   <= '0';
           stop_status_i <= '0';
         end if;