From: Michael Traxler <M.Traxler@gsi.de>
Date: Sun, 12 Sep 2021 10:35:54 +0000 (+0200)
Subject: added new boards to HW_INFO_BASE and so on, mt
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=45f84fd884b1f3866bc6031f7904708e3a74e182;p=daqdocu.git

added new boards to HW_INFO_BASE and so on, mt
---

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index 8ff5320..607cca2 100644
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -112,6 +112,10 @@ have to contain one of the following values. The last digit should be used to de
  \item[9600] design for DiRich
  \item[9700] design for DiRich Combiner module
  \item[9900] design for Munich Skyroc boards
+ \item[9A00] design for DiRICH5s
+ \item[9B00] design for FaRICH1
+ \item[9C00] design for DiRICH1
+
  \item[A500] design for TRB5sc
  \item[A600] design for MDC central
  \item[A700] design for MDC TDC
@@ -197,8 +201,13 @@ All boards of a given type are accessible by a broadcast address at the same tim
  \item 0x4e peripheral FPGA for Hades Start detector
  \item 0x4f peripheral FPGA for Panda Straw Tube
  \item 0x50 CBM-Rich
- \item 0x51 DiRich Frontend
- \item 0x52 DiRich Combiner
+ \item 0x51 DiRICH Frontend
+ \item 0x52 DiRICH Combiner
+ \item 0x53 DiRICH4 TDCv4
+ \item 0x54 DiRICH5s TDCv4
+ \item 0x55 FaRICH1 TDCv4
+ \item 0x56 DiRICH1 TDCv4
+ \item 0x57 DiRICH5s TDCv2
  \item 0x60 Trb3sc
  \item 0x61 Trb3sc Backplane Maser w/ GbE
  \item 0x62 Trb3sc CTS w/ SFP
@@ -228,8 +237,9 @@ The initial address set with \signal{Regio\_Init\_Address} can be chosen from th
  \item 0xF3CC slave TRB3sc
  \item 0xF3CD TRB3sc with hub AddOn
  \item 0xF3CE crate master TRB3sc
- \item 0xF3D1 Dirch
- \item 0xF3DC Dirich combiner
+ \item 0xF3D1 DiRICH
+ \item 0xF3D5 DiRICH5s
+ \item 0xF3DC DiRICH combiner
  \item 0xF355 Trb5sc
 \end{itemize*}