From: Cahit Date: Thu, 28 Jan 2016 14:22:35 +0000 (+0100) Subject: brought 32PinAddon project up-to-date with last TDC version X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=461b83a1fab24a466a8d309dd15eccd6c44d6fb5;p=trb3.git brought 32PinAddon project up-to-date with last TDC version --- diff --git a/32PinAddOn/config.vhd b/32PinAddOn/config.vhd index 356cde7..891d3fe 100644 --- a/32PinAddOn/config.vhd +++ b/32PinAddOn/config.vhd @@ -11,34 +11,34 @@ package config is --TDC settings constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 3; -- number of tdc channels per module - constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 65; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 2; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, -- 2: alternating channels, -- 3: same channel with stretcher - constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file + constant RING_BUFFER_SIZE : integer range 0 to 7 := 1; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file --ring buffer size: 32,64,96,128,dyn - constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N - constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 - + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 11; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 1024; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 + constant INCLUDE_UART : integer := c_NO; constant INCLUDE_SPI : integer := c_YES; constant INCLUDE_LCD : integer := c_NO; - constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; - + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + --input monitor and trigger generation logic constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; constant INCLUDE_STATISTICS : integer := c_YES; constant TRIG_GEN_INPUT_NUM : integer := 16; constant TRIG_GEN_OUTPUT_NUM : integer := 4; - constant MONITOR_INPUT_NUM : integer := 24; + constant MONITOR_INPUT_NUM : integer := 24; constant USE_SINGLE_FIFO : integer := c_YES; -- single fifo for statistics --Run wih 125 MHz instead of 100 MHz, use received clock from serdes or external clock input - constant USE_125_MHZ : integer := c_NO; --not implemented yet! + constant USE_125_MHZ : integer := c_NO; --not implemented yet! constant USE_RXCLOCK : integer := c_NO; --not implemented yet! constant USE_EXTERNALCLOCK : integer := c_NO; --not implemented yet! diff --git a/32PinAddOn/trb3_periph_32PinAddOn.vhd b/32PinAddOn/trb3_periph_32PinAddOn.vhd index e4edf0b..1fab6e1 100644 --- a/32PinAddOn/trb3_periph_32PinAddOn.vhd +++ b/32PinAddOn/trb3_periph_32PinAddOn.vhd @@ -420,11 +420,12 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record -- Trigger signals from handler BUSRDO_RX => readout_rx, BUSRDO_TX => readout_tx(0), - -- - INFO_IN => timer, - LOGIC_ANALYSER_OUT => TEST_LINE, + -- Slow control bus BUS_RX => bustdc_rx, - BUS_TX => bustdc_tx + BUS_TX => bustdc_tx, + -- Dubug signals + INFO_IN => timer, + LOGIC_ANALYSER_OUT => TEST_LINE ); -- For single edge measurements