From: hadeshyp <hadeshyp>
Date: Fri, 5 Jun 2009 08:02:22 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~440
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=4685c20e39cfbe82c9582db4ef18ac7abdc5739a;p=trbnet.git

*** empty log message ***
---

diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd
index 451534e..bb1a1a3 100644
--- a/trb_net16_hub_base.vhd
+++ b/trb_net16_hub_base.vhd
@@ -4,6 +4,7 @@ USE IEEE.numeric_std.ALL;
 USE IEEE.std_logic_UNSIGNED.ALL;
 library work;
 use work.trb_net_std.all;
+use work.trb_net_components.all;
 use work.trb_net16_hub_func.all;
 
 entity trb_net16_hub_base is
@@ -393,6 +394,7 @@ MED_DATA_OUT       <= buf_MED_DATA_OUT;
         INT_SLAVE_DATA_IN         => hub_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
         INT_SLAVE_PACKET_NUM_IN   => hub_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
         INT_SLAVE_READ_OUT        => hub_to_buf_INIT_READ(i),
+        CTRL_SEQNR_RESET          => HC_COMMON_CTRL_REGS(10),
         -- Status and control port
         STAT_FIFO_TO_INT          => open,
         STAT_FIFO_TO_APL          => open
diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd
index 8fb5bdd..7c7c009 100644
--- a/trb_net16_hub_ipu_logic.vhd
+++ b/trb_net16_hub_ipu_logic.vhd
@@ -763,11 +763,6 @@ reply_compare_finished <= reply_compare_start;
             next_state <= WAIT_FOR_HDR_DATA;
           end if;
 
-        when WAIT_FOR_REPLY =>
-          if got_all_reply_starts = '1' then
-            next_state <= WAIT_FOR_HDR_DATA;
-          end if;
-
         when WAIT_FOR_HDR_DATA =>  --start writing HDR when first reply is received, stop waiting for length
           last_dhdr_addr <= "010";
           case packet_counter is
diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index 8d9e4c0..ff1f776 100644
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -107,6 +107,7 @@ package trb_net_components is
       INT_SLAVE_PACKET_NUM_IN   : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
       INT_SLAVE_READ_OUT        : out std_logic;
       -- Status and control port
+      CTRL_SEQNR_RESET          : in  std_logic;
       STAT_FIFO_TO_INT          : out std_logic_vector(31 downto 0);
       STAT_FIFO_TO_APL          : out std_logic_vector(31 downto 0)
       );
@@ -327,7 +328,7 @@ package trb_net_components is
   component trb_net16_hub_logic is
     generic (
     --media interfaces
-      POINT_NUMBER        : integer range 2 to c_MAX_POINTS_PER_HUB := 2
+      POINT_NUMBER        : integer range 2 to 32 := 2
       );
     port (
       CLK    : in std_logic;
@@ -549,7 +550,7 @@ package trb_net_components is
 
   component trb_net_priority_arbiter is
     generic (
-      WIDTH : integer := POINT_NUMBER
+      WIDTH : integer := 1
       );
     port(
       --  Misc