From: Tobias Weber Date: Wed, 4 Jul 2018 13:41:09 +0000 (+0200) Subject: working version of the SODA test module. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=46d0c2f2503e05d703a1c689de1f649c11c81a58;p=trb3.git working version of the SODA test module. --- diff --git a/mupix/MupixSoda/sources/LinearFeedbackShiftRegister.vhd b/mupix/MupixSoda/sources/LinearFeedbackShiftRegister.vhd index 1c01590..ac1a4e7 100644 --- a/mupix/MupixSoda/sources/LinearFeedbackShiftRegister.vhd +++ b/mupix/MupixSoda/sources/LinearFeedbackShiftRegister.vhd @@ -19,7 +19,7 @@ end LinearFeedbackShiftRegister; architecture Behavioral of LinearFeedbackShiftRegister is - signal lfsr_speicher : std_logic_vector(3 downto 0); + signal lfsr_speicher : std_logic_vector(3 downto 0) := "1111"; signal enable : std_logic := '0'; begin diff --git a/mupix/MupixSoda/sources/SodaBoard.vhd b/mupix/MupixSoda/sources/SodaBoard.vhd index 0d38f26..53c6b62 100644 --- a/mupix/MupixSoda/sources/SodaBoard.vhd +++ b/mupix/MupixSoda/sources/SodaBoard.vhd @@ -165,7 +165,7 @@ begin slv_ack_out <= '0'; slv_no_more_data_out <= '0'; slv_unknown_addr_out <= '0'; - reset_trigger_state_i <= '1'; + reset_trigger_state_i <= '0'; if (slv_write_in = '1') then case slv_addr_in is diff --git a/mupix/MupixSoda/sources/TriggerHandler.vhd b/mupix/MupixSoda/sources/TriggerHandler.vhd index 6b3d0c3..baf559a 100644 --- a/mupix/MupixSoda/sources/TriggerHandler.vhd +++ b/mupix/MupixSoda/sources/TriggerHandler.vhd @@ -117,6 +117,7 @@ begin timing_trigger_edge <= (others => '0'); reset_trigger_state_edge <= (others => '0'); else + buffer_readout_end_int <= buffer_readout_end_int(0) & FEE_DATA_FINISHED_IN; timing_trigger_edge <= timing_trigger_edge(0) & TIMING_TRIGGER_IN; reset_trigger_state_edge <= reset_trigger_state_edge(1) & reset_trigger_state; end if; @@ -171,6 +172,8 @@ begin else trigger_handler_fsm <= check_trigger_type; end if; + else + trigger_handler_fsm <= idle; end if; when check_trigger_type => diff --git a/mupix/MupixSoda/tb/SodaBoardTest.vhd b/mupix/MupixSoda/tb/SodaBoardTest.vhd new file mode 100644 index 0000000..a791a23 --- /dev/null +++ b/mupix/MupixSoda/tb/SodaBoardTest.vhd @@ -0,0 +1,149 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.TRBSimulationPkg.all; + +entity SodaBoardSimulation is +end entity SodaBoardSimulation; + +architecture sim of SodaBoardSimulation is + + component sodaBoard is + port ( + clk_in : in std_logic; + reset_in : in std_logic; + TIMING_TRG_IN : in std_logic; + LVL1_TRG_DATA_VALID_IN : in std_logic; + LVL1_VALID_TIMING_TRG_IN : in std_logic; + LVL1_VALID_NOTIMING_TRG_IN : in std_logic; + LVL1_INVALID_TRG_IN : in std_logic; + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + FEE_TRG_RELEASE_OUT : out std_logic; + FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_WRITE_OUT : out std_logic; + FEE_DATA_FINISHED_OUT : out std_logic; + FEE_DATA_ALMOST_FULL_IN : in std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic); + end component sodaBoard; + + constant clk_period : time := 10 ns; + signal clk_in : std_logic; + signal reset_in : std_logic := '0'; + signal TIMING_TRG_IN : std_logic := '0'; + signal LVL1_TRG_DATA_VALID_IN : std_logic := '0'; + signal LVL1_VALID_TIMING_TRG_IN : std_logic := '0'; + signal LVL1_VALID_NOTIMING_TRG_IN : std_logic := '0'; + signal LVL1_INVALID_TRG_IN : std_logic := '0'; + signal LVL1_TRG_TYPE_IN : std_logic_vector(3 downto 0) := (others => '0'); + signal LVL1_TRG_NUMBER_IN : std_logic_vector(15 downto 0) := (others => '0'); + signal LVL1_TRG_CODE_IN : std_logic_vector(7 downto 0) := (others => '0'); + signal LVL1_TRG_INFORMATION_IN : std_logic_vector(23 downto 0) := (others => '0'); + signal LVL1_INT_TRG_NUMBER_IN : std_logic_vector(15 downto 0) := (others => '0'); + signal FEE_TRG_RELEASE_OUT : std_logic; + signal FEE_TRG_STATUSBITS_OUT : std_logic_vector(31 downto 0) := (others => '0'); + signal FEE_DATA_OUT : std_logic_vector(31 downto 0) := (others => '0'); + signal FEE_DATA_WRITE_OUT : std_logic; + signal FEE_DATA_FINISHED_OUT : std_logic; + signal FEE_DATA_ALMOST_FULL_IN : std_logic := '0'; + signal SLV_READ_IN : std_logic := '0'; + signal SLV_WRITE_IN : std_logic := '0'; + signal SLV_DATA_OUT : std_logic_vector(31 downto 0); + signal SLV_DATA_IN : std_logic_vector(31 downto 0) := (others => '0'); + signal SLV_ADDR_IN : std_logic_vector(15 downto 0) := (others => '0'); + signal SLV_ACK_OUT : std_logic; + signal SLV_NO_MORE_DATA_OUT : std_logic; + signal SLV_UNKNOWN_ADDR_OUT : std_logic; + +begin -- architecture sim + + sodaBoard_1 : entity work.sodaBoard + port map ( + clk_in => clk_in, + reset_in => reset_in, + TIMING_TRG_IN => TIMING_TRG_IN, + LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN, + LVL1_VALID_TIMING_TRG_IN => LVL1_VALID_TIMING_TRG_IN, + LVL1_VALID_NOTIMING_TRG_IN => LVL1_VALID_NOTIMING_TRG_IN, + LVL1_INVALID_TRG_IN => LVL1_INVALID_TRG_IN, + LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN, + LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN, + LVL1_TRG_CODE_IN => LVL1_TRG_CODE_IN, + LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_IN, + LVL1_INT_TRG_NUMBER_IN => LVL1_INT_TRG_NUMBER_IN, + FEE_TRG_RELEASE_OUT => FEE_TRG_RELEASE_OUT, + FEE_TRG_STATUSBITS_OUT => FEE_TRG_STATUSBITS_OUT, + FEE_DATA_OUT => FEE_DATA_OUT, + FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT, + FEE_DATA_FINISHED_OUT => FEE_DATA_FINISHED_OUT, + FEE_DATA_ALMOST_FULL_IN => FEE_DATA_ALMOST_FULL_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_NO_MORE_DATA_OUT => SLV_NO_MORE_DATA_OUT, + SLV_UNKNOWN_ADDR_OUT => SLV_UNKNOWN_ADDR_OUT); + + clock_gen : process is + begin -- process clock_gen + clk_in <= '0'; + wait for clk_period/2; + clk_in <= '1'; + wait for clk_period/2; + end process clock_gen; + + stimul : process is + begin -- process stimul + wait for 100 ns; + -- simulate a trigger while bypass is on + LVL1_TRG_DATA_VALID_IN <= '1'; + LVL1_TRG_TYPE_IN <= x"1"; + LVL1_INT_TRG_NUMBER_IN <= (others => '0'); + LVL1_VALID_NOTIMING_TRG_IN <= '1'; + wait for 10*clk_period; + LVL1_TRG_DATA_VALID_IN <= '0'; + LVL1_TRG_TYPE_IN <= x"0"; + LVL1_VALID_NOTIMING_TRG_IN <= '0'; + wait for 10*clk_period; + -- test status trigger + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0004"); + LVL1_TRG_DATA_VALID_IN <= '1'; + LVL1_TRG_TYPE_IN <= x"e"; + LVL1_INT_TRG_NUMBER_IN <= (others => '0'); + LVL1_INT_TRG_NUMBER_IN(0) <= '1'; + LVL1_VALID_NOTIMING_TRG_IN <= '1'; + wait for 10*clk_period; + LVL1_TRG_DATA_VALID_IN <= '0'; + LVL1_TRG_TYPE_IN <= x"0"; + LVL1_VALID_NOTIMING_TRG_IN <= '0'; + LVL1_INT_TRG_NUMBER_IN(0) <= '0'; + wait for 100 ns; + -- test physics trigger and data generation + LVL1_TRG_DATA_VALID_IN <= '1'; + LVL1_TRG_TYPE_IN <= x"1"; + LVL1_INT_TRG_NUMBER_IN <= (others => '0'); + LVL1_INT_TRG_NUMBER_IN(1) <= '1'; + LVL1_VALID_NOTIMING_TRG_IN <= '1'; + wait for 30*clk_period; + LVL1_TRG_DATA_VALID_IN <= '0'; + LVL1_TRG_TYPE_IN <= x"0"; + LVL1_VALID_NOTIMING_TRG_IN <= '0'; + LVL1_INT_TRG_NUMBER_IN(0) <= '0'; + wait; + end process stimul; + +end architecture sim; diff --git a/mupix/MupixSoda/trb3_periph.prj b/mupix/MupixSoda/trb3_periph.prj index baaaafc..7d4a244 100644 --- a/mupix/MupixSoda/trb3_periph.prj +++ b/mupix/MupixSoda/trb3_periph.prj @@ -149,3 +149,4 @@ add_file -vhdl -lib "work" "trb3_periph.vhd" add_file -vhdl -lib "work" "sources/FrameGenerator.vhd" add_file -vhdl -lib "work" "sources/LinearFeedbackShiftRegister.vhd" add_file -vhdl -lib "work" "sources/SodaBoard.vhd" +add_file -vhdl -lib "work" "sources/TriggerHandler.vhd" diff --git a/mupix/MupixSoda/trb3_periph.vhd b/mupix/MupixSoda/trb3_periph.vhd index cfe6447..cba4910 100644 --- a/mupix/MupixSoda/trb3_periph.vhd +++ b/mupix/MupixSoda/trb3_periph.vhd @@ -172,6 +172,7 @@ architecture trb3_periph_arch of trb3_periph is signal trg_spike_detected_i : std_logic; --Data channel + constant NumberFEECards : integer := 1; signal fee_trg_release_i : std_logic_vector(NumberFEECards-1 downto 0); signal fee_trg_statusbits_i : std_logic_vector(NumberFEECards*32-1 downto 0); signal fee_data_i : std_logic_vector(NumberFEECards*32-1 downto 0);