From: Florian Marx Date: Mon, 4 Jun 2018 13:24:20 +0000 (+0200) Subject: starting to work on delay and stretch X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=46e8e378209af214f53d219304b0528cf50e1241;p=triggerlogic.git starting to work on delay and stretch --- diff --git a/cores/delay_shift_reg.vhd b/cores/delay_shift_reg.vhd new file mode 100644 index 0000000..c303544 --- /dev/null +++ b/cores/delay_shift_reg.vhd @@ -0,0 +1,696 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.1.112 +-- Module Version: 5.2 +--/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n delay_shift_reg -lang vhdl -synth synplify -bb -arch ep5c00 -type shiftreg -width 1 -depth 256 -mode 2 -pipe_final_output + +-- Fri Jun 1 14:33:29 2018 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity delay_shift_reg is + port ( + Din: in std_logic_vector(0 downto 0); -- eingang vn einem signal also muss 32 mal initialisiert werden + Addr: in std_logic_vector(7 downto 0); -- tiefe aus dem register + Clock: in std_logic; + ClockEn: in std_logic; -- dauerhaft auf 1 + Reset: in std_logic; -- dauerhaft 0 + Q: out std_logic_vector(0 downto 0)); +end delay_shift_reg; + +architecture Structure of delay_shift_reg is + + -- internal signal declarations + signal func_and_inet: std_logic; + signal func_and_inet_1: std_logic; + signal func_and_inet_2: std_logic; + signal func_and_inet_3: std_logic; + signal func_and_inet_4: std_logic; + signal func_and_inet_5: std_logic; + signal func_and_inet_6: std_logic; + signal shreg_addr_w7_inv: std_logic; + signal func_and_inet_7: std_logic; + signal func_and_inet_8: std_logic; + signal func_and_inet_9: std_logic; + signal func_and_inet_10: std_logic; + signal shreg_addr_w6_inv: std_logic; + signal func_and_inet_11: std_logic; + signal func_and_inet_12: std_logic; + signal shreg_addr_w5_inv: std_logic; + signal func_and_inet_13: std_logic; + signal shreg_addr_w4_inv: std_logic; + signal func_and_inet_14: std_logic; + signal Reset_inv: std_logic; + signal func_and_inet_15: std_logic; + signal scuba_vhi: std_logic; + signal ishreg_addr_w0: std_logic; + signal ishreg_addr_w1: std_logic; + signal sreg_0_ctr_1_ci: std_logic; + signal ishreg_addr_w2: std_logic; + signal ishreg_addr_w3: std_logic; + signal co0: std_logic; + signal ishreg_addr_w4: std_logic; + signal ishreg_addr_w5: std_logic; + signal co1: std_logic; + signal ishreg_addr_w6: std_logic; + signal ishreg_addr_w7: std_logic; + signal co3: std_logic; + signal co2: std_logic; + signal precin: std_logic; + signal low_inv: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal shreg_addr_w4: std_logic; + signal co2_1: std_logic; + signal shreg_addr_w5: std_logic; + signal shreg_addr_w6: std_logic; + signal co3_1: std_logic; + signal shreg_addr_w7: std_logic; + signal Q0_ffin: std_logic; + signal shreg_addr_r7: std_logic; + signal shreg_addr_r6: std_logic; + signal shreg_addr_r5: std_logic; + signal shreg_addr_r4: std_logic; + signal mdL0_0_0: std_logic; + signal dec0_wre3: std_logic; + signal mdL0_1_0: std_logic; + signal dec1_wre7: std_logic; + signal mdL0_2_0: std_logic; + signal dec2_wre11: std_logic; + signal mdL0_3_0: std_logic; + signal dec3_wre15: std_logic; + signal mdL0_4_0: std_logic; + signal dec4_wre19: std_logic; + signal mdL0_5_0: std_logic; + signal dec5_wre23: std_logic; + signal mdL0_6_0: std_logic; + signal dec6_wre27: std_logic; + signal mdL0_7_0: std_logic; + signal dec7_wre31: std_logic; + signal mdL0_8_0: std_logic; + signal dec8_wre35: std_logic; + signal mdL0_9_0: std_logic; + signal dec9_wre39: std_logic; + signal mdL0_10_0: std_logic; + signal dec10_wre43: std_logic; + signal mdL0_11_0: std_logic; + signal dec11_wre47: std_logic; + signal mdL0_12_0: std_logic; + signal dec12_wre51: std_logic; + signal mdL0_13_0: std_logic; + signal dec13_wre55: std_logic; + signal mdL0_14_0: std_logic; + signal dec14_wre59: std_logic; + signal mdL0_15_0: std_logic; + signal shreg_addr_r3: std_logic; + signal shreg_addr_r2: std_logic; + signal shreg_addr_r1: std_logic; + signal shreg_addr_r0: std_logic; + signal dec15_wre63: std_logic; + signal shreg_addr_w3: std_logic; + signal shreg_addr_w2: std_logic; + signal shreg_addr_w1: std_logic; + signal shreg_addr_w0: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX161 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; D4: in std_logic; D5: in std_logic; + D6: in std_logic; D7: in std_logic; D8: in std_logic; + D9: in std_logic; D10: in std_logic; D11: in std_logic; + D12: in std_logic; D13: in std_logic; D14: in std_logic; + D15: in std_logic; SD1: in std_logic; SD2: in std_logic; + SD3: in std_logic; SD4: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4C + generic (INITVAL : in String); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute GSR : string; + attribute MEM_INIT_FILE : string; + attribute MEM_LPC_FILE : string; + attribute COMP : string; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute MEM_INIT_FILE of sram_1_0_0 : label is "(0-15)(0-0)"; + attribute MEM_LPC_FILE of sram_1_0_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_0_0 : label is "sram_1_0_0"; + attribute MEM_INIT_FILE of sram_1_1_0 : label is "(16-31)(0-0)"; + attribute MEM_LPC_FILE of sram_1_1_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_1_0 : label is "sram_1_1_0"; + attribute MEM_INIT_FILE of sram_1_2_0 : label is "(32-47)(0-0)"; + attribute MEM_LPC_FILE of sram_1_2_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_2_0 : label is "sram_1_2_0"; + attribute MEM_INIT_FILE of sram_1_3_0 : label is "(48-63)(0-0)"; + attribute MEM_LPC_FILE of sram_1_3_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_3_0 : label is "sram_1_3_0"; + attribute MEM_INIT_FILE of sram_1_4_0 : label is "(64-79)(0-0)"; + attribute MEM_LPC_FILE of sram_1_4_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_4_0 : label is "sram_1_4_0"; + attribute MEM_INIT_FILE of sram_1_5_0 : label is "(80-95)(0-0)"; + attribute MEM_LPC_FILE of sram_1_5_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_5_0 : label is "sram_1_5_0"; + attribute MEM_INIT_FILE of sram_1_6_0 : label is "(96-111)(0-0)"; + attribute MEM_LPC_FILE of sram_1_6_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_6_0 : label is "sram_1_6_0"; + attribute MEM_INIT_FILE of sram_1_7_0 : label is "(112-127)(0-0)"; + attribute MEM_LPC_FILE of sram_1_7_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_7_0 : label is "sram_1_7_0"; + attribute MEM_INIT_FILE of sram_1_8_0 : label is "(128-143)(0-0)"; + attribute MEM_LPC_FILE of sram_1_8_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_8_0 : label is "sram_1_8_0"; + attribute MEM_INIT_FILE of sram_1_9_0 : label is "(144-159)(0-0)"; + attribute MEM_LPC_FILE of sram_1_9_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_9_0 : label is "sram_1_9_0"; + attribute MEM_INIT_FILE of sram_1_10_0 : label is "(160-175)(0-0)"; + attribute MEM_LPC_FILE of sram_1_10_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_10_0 : label is "sram_1_10_0"; + attribute MEM_INIT_FILE of sram_1_11_0 : label is "(176-191)(0-0)"; + attribute MEM_LPC_FILE of sram_1_11_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_11_0 : label is "sram_1_11_0"; + attribute MEM_INIT_FILE of sram_1_12_0 : label is "(192-207)(0-0)"; + attribute MEM_LPC_FILE of sram_1_12_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_12_0 : label is "sram_1_12_0"; + attribute MEM_INIT_FILE of sram_1_13_0 : label is "(208-223)(0-0)"; + attribute MEM_LPC_FILE of sram_1_13_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_13_0 : label is "sram_1_13_0"; + attribute MEM_INIT_FILE of sram_1_14_0 : label is "(224-239)(0-0)"; + attribute MEM_LPC_FILE of sram_1_14_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_14_0 : label is "sram_1_14_0"; + attribute MEM_INIT_FILE of sram_1_15_0 : label is "(240-255)(0-0)"; + attribute MEM_LPC_FILE of sram_1_15_0 : label is "delay_shift_reg.lpc"; + attribute COMP of sram_1_15_0 : label is "sram_1_15_0"; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + INV_5: INV + port map (A=>Reset, Z=>Reset_inv); + + INV_4: INV + port map (A=>scuba_vlo, Z=>low_inv); + + INV_3: INV + port map (A=>shreg_addr_w4, Z=>shreg_addr_w4_inv); + + INV_2: INV + port map (A=>shreg_addr_w5, Z=>shreg_addr_w5_inv); + + INV_1: INV + port map (A=>shreg_addr_w6, Z=>shreg_addr_w6_inv); + + INV_0: INV + port map (A=>shreg_addr_w7, Z=>shreg_addr_w7_inv); + + LUT4_31: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet); + + LUT4_30: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec0_wre3); + + LUT4_29: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet_1); + + LUT4_28: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_1, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec1_wre7); + + LUT4_27: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5, DO0=>func_and_inet_2); + + LUT4_26: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_2, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec2_wre11); + + LUT4_25: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5, DO0=>func_and_inet_3); + + LUT4_24: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_3, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec3_wre15); + + LUT4_23: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet_4); + + LUT4_22: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_4, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec4_wre19); + + LUT4_21: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet_5); + + LUT4_20: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_5, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec5_wre23); + + LUT4_19: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5, DO0=>func_and_inet_6); + + LUT4_18: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_6, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec6_wre27); + + LUT4_17: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5, DO0=>func_and_inet_7); + + LUT4_16: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_7, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7_inv, AD0=>scuba_vhi, DO0=>dec7_wre31); + + LUT4_15: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet_8); + + LUT4_14: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_8, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec8_wre35); + + LUT4_13: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet_9); + + LUT4_12: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_9, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec9_wre39); + + LUT4_11: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5, DO0=>func_and_inet_10); + + LUT4_10: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_10, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec10_wre43); + + LUT4_9: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5, DO0=>func_and_inet_11); + + LUT4_8: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_11, AD2=>shreg_addr_w6_inv, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec11_wre47); + + LUT4_7: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet_12); + + LUT4_6: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_12, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec12_wre51); + + LUT4_5: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5_inv, DO0=>func_and_inet_13); + + LUT4_4: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_13, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec13_wre55); + + LUT4_3: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5, DO0=>func_and_inet_14); + + LUT4_2: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_14, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec14_wre59); + + LUT4_1: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5, DO0=>func_and_inet_15); + + LUT4_0: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_15, AD2=>shreg_addr_w6, + AD1=>shreg_addr_w7, AD0=>scuba_vhi, DO0=>dec15_wre63); + + FF_8: FD1P3DX + port map (D=>ishreg_addr_w0, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w0); + + FF_7: FD1P3DX + port map (D=>ishreg_addr_w1, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w1); + + FF_6: FD1P3DX + port map (D=>ishreg_addr_w2, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w2); + + FF_5: FD1P3DX + port map (D=>ishreg_addr_w3, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w3); + + FF_4: FD1P3DX + port map (D=>ishreg_addr_w4, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w4); + + FF_3: FD1P3DX + port map (D=>ishreg_addr_w5, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w5); + + FF_2: FD1P3DX + port map (D=>ishreg_addr_w6, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w6); + + FF_1: FD1P3DX + port map (D=>ishreg_addr_w7, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w7); + + FF_0: FD1P3DX + port map (D=>Q0_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(0)); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + sreg_0_ctr_1_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>sreg_0_ctr_1_ci, + S0=>open, S1=>open); + + sreg_0_ctr_1_0: CU2 + port map (CI=>sreg_0_ctr_1_ci, PC0=>shreg_addr_w0, + PC1=>shreg_addr_w1, CO=>co0, NC0=>ishreg_addr_w0, + NC1=>ishreg_addr_w1); + + sreg_0_ctr_1_1: CU2 + port map (CI=>co0, PC0=>shreg_addr_w2, PC1=>shreg_addr_w3, + CO=>co1, NC0=>ishreg_addr_w2, NC1=>ishreg_addr_w3); + + sreg_0_ctr_1_2: CU2 + port map (CI=>co1, PC0=>shreg_addr_w4, PC1=>shreg_addr_w5, + CO=>co2, NC0=>ishreg_addr_w4, NC1=>ishreg_addr_w5); + + sreg_0_ctr_1_3: CU2 + port map (CI=>co2, PC0=>shreg_addr_w6, PC1=>shreg_addr_w7, + CO=>co3, NC0=>ishreg_addr_w6, NC1=>ishreg_addr_w7); + + precin_inst46: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, + S1=>open); + + raddr_sub_1_0: FSUB2B + port map (A0=>scuba_vlo, A1=>shreg_addr_w0, B0=>low_inv, + B1=>Addr(0), BI=>precin, BOUT=>co0_1, S0=>open, + S1=>shreg_addr_r0); + + raddr_sub_1_1: FSUB2B + port map (A0=>shreg_addr_w1, A1=>shreg_addr_w2, B0=>Addr(1), + B1=>Addr(2), BI=>co0_1, BOUT=>co1_1, S0=>shreg_addr_r1, + S1=>shreg_addr_r2); + + raddr_sub_1_2: FSUB2B + port map (A0=>shreg_addr_w3, A1=>shreg_addr_w4, B0=>Addr(3), + B1=>Addr(4), BI=>co1_1, BOUT=>co2_1, S0=>shreg_addr_r3, + S1=>shreg_addr_r4); + + raddr_sub_1_3: FSUB2B + port map (A0=>shreg_addr_w5, A1=>shreg_addr_w6, B0=>Addr(5), + B1=>Addr(6), BI=>co2_1, BOUT=>co3_1, S0=>shreg_addr_r5, + S1=>shreg_addr_r6); + + raddr_sub_1_4: FSUB2B + port map (A0=>shreg_addr_w7, A1=>scuba_vlo, B0=>Addr(7), + B1=>scuba_vlo, BI=>co3_1, BOUT=>open, S0=>shreg_addr_r7, + S1=>open); + + mux_0: MUX161 + port map (D0=>mdL0_0_0, D1=>mdL0_1_0, D2=>mdL0_2_0, D3=>mdL0_3_0, + D4=>mdL0_4_0, D5=>mdL0_5_0, D6=>mdL0_6_0, D7=>mdL0_7_0, + D8=>mdL0_8_0, D9=>mdL0_9_0, D10=>mdL0_10_0, D11=>mdL0_11_0, + D12=>mdL0_12_0, D13=>mdL0_13_0, D14=>mdL0_14_0, + D15=>mdL0_15_0, SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, + SD3=>shreg_addr_r6, SD4=>shreg_addr_r7, Z=>Q0_ffin); + + sram_1_0_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec0_wre3, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_0_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_1_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec1_wre7, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_1_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_2_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec2_wre11, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_2_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_3_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec3_wre15, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_3_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_4_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec4_wre19, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_4_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_5_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec5_wre23, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_5_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_6_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec6_wre27, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_6_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_7_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec7_wre31, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_7_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_8_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec8_wre35, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_8_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_9_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec9_wre39, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_9_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_10_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec10_wre43, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_10_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_11_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec11_wre47, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_11_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_12_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec12_wre51, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_12_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_13_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec13_wre55, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_13_0, + DO1=>open, DO2=>open, DO3=>open); + + sram_1_14_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec14_wre59, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_14_0, + DO1=>open, DO2=>open, DO3=>open); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + sram_1_15_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec15_wre63, + RAD0=>shreg_addr_r0, RAD1=>shreg_addr_r1, + RAD2=>shreg_addr_r2, RAD3=>shreg_addr_r3, + WAD0=>shreg_addr_w0, WAD1=>shreg_addr_w1, + WAD2=>shreg_addr_w2, WAD3=>shreg_addr_w3, DO0=>mdL0_15_0, + DO1=>open, DO2=>open, DO3=>open); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of delay_shift_reg is + for Structure + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX161 use entity ecp3.MUX161(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:DPR16X4C use entity ecp3.DPR16X4C(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/testbench/tb.vhd b/testbench/tb.vhd index 1624c85..9e2c749 100644 --- a/testbench/tb.vhd +++ b/testbench/tb.vhd @@ -21,8 +21,8 @@ component trigger_logic RESET : in std_logic; --Slowcontrol - BUS_RX : in CTRLBUS_RX; - BUS_TX : out CTRLBUS_TX; + BUS_RX : in CTRLBUS_RX; -- communication in + BUS_TX : out CTRLBUS_TX; -- communication out --Inputs and Outputs INPUT : in std_logic_vector(INPUTS-1 downto 0); @@ -45,24 +45,34 @@ begin CLK <= not CLK after 5 ns; -PROC_INIT_REGISTERS : process begin +PROC_INIT_REGISTERS : process begin -- Define the Values for the Registers here BUS_RX.write <= '0'; BUS_RX.read <= '0'; wait for 100 ns; wait until rising_edge(CLK); wait for 1 ns; - BUS_RX.write <= '1'; BUS_RX.addr <= x"0000"; BUS_RX.data <= x"0000FFFF"; + BUS_RX.write <= '1'; BUS_RX.addr <= x"0000"; BUS_RX.data <= x"0000FFFF"; -- Bsp adress + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"0001"; BUS_RX.data <= x"FFFFFFFF"; -- Adress for Enable rn: all open + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"0002"; BUS_RX.data <= x"00000000"; -- Adress for Invert rn: none inverted wait until rising_edge(CLK); wait for 1 ns; BUS_RX.write <= '0'; wait; end process; -PROC_INPUTS : process begin +PROC_INPUTS : process begin -- Simulates the Inputs by the detector inputs <= (others => '0'); wait for 500 ns; wait for 24 ns; inputs <= x"00000001"; wait for 27 ns; + inputs <= x"008AB400"; + wait for 33 ns; + inputs <= x"0000F44F"; + wait for 14 ns; + inputs <= x"0000C4CF"; + wait for 6 ns; inputs <= x"00000000"; end process; diff --git a/trigger_coin.vhd b/trigger_coin.vhd new file mode 100644 index 0000000..ee2de11 --- /dev/null +++ b/trigger_coin.vhd @@ -0,0 +1,33 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_std.all; + + +entity trg_coin is + port( + + + ) +end trg_coin; + + + + + + + + + + +architecture behave of trg_coin is + + SIGNAL ......:std_logic... + + + +begin + +end behave; diff --git a/trigger_delay.vhd b/trigger_delay.vhd new file mode 100644 index 0000000..b571b0e --- /dev/null +++ b/trigger_delay.vhd @@ -0,0 +1,33 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_std.all; + + +entity trg_delay is + port( + clk_in : in std_logic; + signals : in std_logic_vector(31 downto 0); + reg_inhalt1 : in std_logic_vector(31 downto 0); + reg_inhalt2 : in std_logic_vector(31 downto 0); + reg_inhalt3 : in std_logic_vector(31 downto 0); + processed_signals : out std_logic_vector(31 downto 0) + ) +end trg_delay; + +architecture behave of trg_delay is + + signal + + + +begin + + + + + + +end behave; diff --git a/trigger_edgedetect.vhd b/trigger_edgedetect.vhd index 4bc28c6..2806524 100644 --- a/trigger_edgedetect.vhd +++ b/trigger_edgedetect.vhd @@ -36,10 +36,10 @@ end process; detect_step2: process is begin - wait until falling_edge(clk_in); + wait until rising_edge(clk_in); for i in 0 to 31 loop - if signals(i)='1' and temp_save(i)='0' then - processed_signals(i)<='1'; + if signals(i)='1' and temp_save(i)='0' then -- results in processed signal being transmitted fro 0.5 clk to 1.5 clk + processed_signals(i)<='1'; -- maybe synchronize it better ??? else processed_signals(i)<='0'; end if; diff --git a/trigger_enable.vhd b/trigger_enable.vhd index f64603f..8310faa 100644 --- a/trigger_enable.vhd +++ b/trigger_enable.vhd @@ -25,7 +25,7 @@ begin enable: process is begin - wait until rising_edge(clk_in); +-- wait until rising_edge(clk_in); for i in 0 to 31 loop if reg_inhalt(i) = '0' then processed_signals(i) <= '0'; diff --git a/trigger_inverter.vhd b/trigger_inverter.vhd index 74eabcb..5f8c96a 100644 --- a/trigger_inverter.vhd +++ b/trigger_inverter.vhd @@ -24,7 +24,7 @@ begin invert: process is begin - wait until rising_edge(clk_in); +-- wait until rising_edge(clk_in); for i in 0 to 31 loop if reg_inhalt(i) = '1' then processed_signals(i) <= not signals(i); diff --git a/trigger_logic.vhd b/trigger_logic.vhd index 5ae4259..193edba 100644 --- a/trigger_logic.vhd +++ b/trigger_logic.vhd @@ -7,7 +7,7 @@ library work; entity trigger_logic is generic( - INPUTS : integer := 32; + INPUTS : integer := 32; -- Doppel definiert ( auch in tb ??) OUTPUTS : integer := 32 ); port( @@ -28,17 +28,44 @@ end entity; architecture arch of trigger_logic is +constant CHANNELS : integer := 32; + --Registers -signal REG_ENABLE : std_logic_vector(31 downto 0); +signal reg_bsp : std_logic_vector(31 downto 0); +signal reg_enable : std_logic_vector(31 downto 0); +signal reg_invert : std_logic_vector(31 downto 0); +signal reg_delay : std_logic_vector(31 downto 0); -begin + +-- Registers with values +type Array10bit is array(31 downto 0) of std_logic_vector (9 downto 0); --stretch +type Array7bit is array(31 downto 0) of std_logic_vector (6 downto 0); -- delay +signal stretch_time : Array10bit; +signal delay_time : Array7bit; + + +-- hand over the signals +signal enb_2_inv : std_logic_vector(31 downto 0); +signal inv_2_det : std_logic_vector(31 downto 0); +signal det_2_delay: std_logic_vector(31 downto 0); +signal delay_2_str: std_logic_vector(31 downto 0); +signal str_2_cion : std_logic_vector(31 downto 0); +signal coin_2_out : std_logic_vector(31 downto 0); + +signal address_i : integer range 0 to 255; +-- +begin + --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- + +address_i <= to_integer(unsigned(BUS_RX.addr(7 downto 0))); + THE_REGS : process begin wait until rising_edge(CLK); BUS_TX.ack <= '0'; @@ -47,22 +74,84 @@ THE_REGS : process begin if BUS_RX.read = '1' then BUS_TX.ack <= '1'; - case BUS_RX.addr(7 downto 0) is - when x"00" => BUS_TX.data <= REG_ENABLE; - when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; - end case; - + if BUS_RX.addr(12 downto 8) = x"0" then + case BUS_RX.addr(7 downto 0) is + when x"00" => BUS_TX.data <= reg_bsp; + when x"01" => BUS_TX.data <= reg_enable; + when x"02" => BUS_TX.data <= reg_invert; + when x"03" => BUS_TX.data <= reg_delay1; + when x"04" => BUS_TX.data <= reg_delay2; + when x"05" => BUS_TX.data <= reg_delay3; + when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; + end case; + elsif BUS_RX.addr(12 downto 8) = x"1" then + if address_i < CHANNELS then + BUS_TX.data <= x"00000" & "00000" & delay_time(address_i); + else + BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; + end if; + elsif BUS_RX.addr(12 downto 8) = x"2" then + if address_i < CHANNELS then + BUS_TX.data <= x"000" & "00" & stretch_type(address_i) & "000000" & stretch_time(address_i); + else + BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; + end if; + end if; elsif BUS_RX.write = '1' then BUS_TX.ack <= '1'; case BUS_RX.addr(7 downto 0) is - when x"00" => REG_ENABLE <= BUS_RX.data; + when x"00" => reg_bsp <= BUS_RX.data; + when x"01" => reg_enable <= BUS_RX.data; + when x"02" => reg_invert <= BUS_RX.data; + when x"03" => reg_delay1 <= BUS_RX.data; + when x"04" => reg_delay2 <= BUS_RX.data; + when x"05" => reg_delay3 <= BUS_RX.data; when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end case; end if; end process; +ENABLE : entity work.trg_enable + + port map( + clk_in => CLK, + signals => INPUT, + reg_inhalt => reg_enable, + processed_signals=> enb_2_inv + ); + + +INVERTER : entity work.trg_inverter + + port map( + clk_in => CLK, + signals => enb_2_inv, + reg_inhalt => reg_invert, + processed_signals=> inv_2_det + ); + + +DETECT: entity work.trg_edgedetect + port map( + clk_in => CLK, + signals => inv_2_det, + processed_signals=> det_2_delay + ); + +GEN_DELAYS : for i in 0 to CHANNELS - 1 generate +THE_DELAY: entity work.trg_delay + port map( + clk_in => CLK, + signals => det_2_delay, + reg_inhalt => reg_delay, + + processed_signals=> delay_2_str + ); +end generate; + + end architecture; diff --git a/trigger_strech.vhd b/trigger_strech.vhd new file mode 100644 index 0000000..68ebcaf --- /dev/null +++ b/trigger_strech.vhd @@ -0,0 +1,33 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_std.all; + + +entity trg_stretch is + port( + + + ) +end trg_stretch; + + + + + + + + + + +architecture behave of trg_stretch is + + SIGNAL ......:std_logic...; + + + +begin + +end behave;