From: Tobias Weber <webert@hawaii.edu>
Date: Thu, 3 Aug 2017 13:09:34 +0000 (+0200)
Subject: Add missing signal delay component.
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=4712d2e5681531020267c463f045565519cf52be;p=trb3.git

Add missing signal delay component.
---

diff --git a/mupix/sources/SignalDelay.vhd b/mupix/sources/SignalDelay.vhd
new file mode 100644
index 0000000..808b003
--- /dev/null
+++ b/mupix/sources/SignalDelay.vhd
@@ -0,0 +1,44 @@
+------------------------------------------------------------
+--Delay Signal for  number of clock cycles given by delay_in
+--T. Weber
+------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.numeric_std.all;
+
+entity SignalDelay is
+  generic(
+    Width : integer := 1;
+    Delay : integer := 4  -- 2**Delay-1
+    );
+  port(
+    clk_in   : in  std_logic;
+    write_en_in : in  std_logic;
+    delay_in : in  std_logic_vector(Delay - 1 downto 0);
+    sig_in   : in  std_logic_vector(Width - 1 downto 0);
+    sig_out  : out std_logic_vector(Width - 1 downto 0));
+end entity;
+
+architecture arch of SignalDelay is
+
+  signal writecounter : unsigned(Delay - 1 downto 0) := (others => '0');
+  signal readcounter  : unsigned(Delay - 1 downto 0) := (others => '0');
+  
+  type memory_t is array((2**Delay) - 1 downto 0) of std_logic_vector(Width - 1 downto 0);
+  signal memory       : memory_t;
+  
+begin
+
+  DelayProc : process(clk_in)
+  begin
+    if rising_edge(clk_in) then
+      if write_en_in = '1' then
+       memory(to_integer(writecounter)) <= sig_in; 
+       writecounter                     <= writecounter + 1;
+       readcounter                      <= writecounter - unsigned(delay_in) + 2;
+      end if;
+      sig_out                           <= memory(to_integer(readcounter));
+    end if;
+  end process DelayProc;
+
+end architecture;