From: Jan Michel <j.michel@gsi.de>
Date: Thu, 9 Nov 2017 14:00:27 +0000 (+0100)
Subject: Add new option for TRB3sc onboard 200 MHz oscillator. New mandatory config setting:
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=47abc2f1c60938fdbbd11b2d79fe16dcb7e00558;p=trb3sc.git

Add new option for TRB3sc onboard 200 MHz oscillator. New mandatory config setting:
USE_200MHZOSCILLATOR
---

diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd
index 798ab76..8068456 100644
--- a/code/clock_reset_handler.vhd
+++ b/code/clock_reset_handler.vhd
@@ -58,6 +58,9 @@ attribute syn_preserve of clear_n_i : signal is true;
 
 begin
 
+assert not (USE_RXCLOCK = c_YES and USE_200MHZOSCILLATOR = c_YES)     report "RX Clock and 200 MHz oscillator not implemented" severity error;
+assert not (USE_120_MHZ = c_YES and USE_200MHZOSCILLATOR = c_YES)     report "120 MHz with 200 MHz oscillator not implemented" severity error;
+
 SYS_CLK_OUT  <= clk_selected_half;
 FULL_CLK_OUT <= clk_selected_full;
 REF_CLK_OUT  <= clk_selected_ref;
@@ -108,15 +111,27 @@ gen_norecov_clock : if USE_RXCLOCK = c_NO generate
   -- Make internal clock 200 MHz if required
   ---------------------------------------------------------------------------
   gen_200 : if USE_120_MHZ = c_NO generate
-    THE_INT_PLL : entity work.pll_in240_out200
-      port map(
-        CLK    => INT_CLK_IN,
-        CLKOP  => open,         --200
-        CLKOS  => clk_int_full, --same as OP, but for DCS
-        CLKOK  => clk_int_half, --100
-        LOCK   => pll_int_lock
-        );
-
+    gen_osc240 : if USE_200MHZOSCILLATOR = c_NO generate
+      THE_INT_PLL : entity work.pll_in240_out200
+        port map(
+          CLK    => INT_CLK_IN,
+          CLKOP  => open,         --200
+          CLKOS  => clk_int_full, --same as OP, but for DCS
+          CLKOK  => clk_int_half, --100
+          LOCK   => pll_int_lock
+          );
+    end generate;      
+    gen_osc200 : if USE_200MHZOSCILLATOR = c_YES generate
+      THE_INT_PLL : entity work.pll_in200_out200
+        port map(
+          CLK    => INT_CLK_IN,
+          CLKOP  => open,         --200
+          CLKOS  => clk_int_full, --same as OP, but for DCS
+          CLKOK  => clk_int_half, --100
+          LOCK   => pll_int_lock
+          );
+    end generate;
+    
     gen_ext_pll : if USE_EXTERNAL_CLOCK = c_YES generate        
       THE_EXT_PLL : entity work.pll_in200_out100
         port map(
diff --git a/cts/config.vhd b/cts/config.vhd
index f97c9a7..1a8b29b 100644
--- a/cts/config.vhd
+++ b/cts/config.vhd
@@ -18,6 +18,7 @@ package config is
 
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
+    constant USE_200MHZOSCILLATOR   : integer := c_NO;
     constant USE_EXTERNAL_CLOCK     : integer := c_YES; --'no' not implemented.
     constant CLOCK_FAST_SELECT      : integer := c_YES; --fast clock select (135us) or slow (280ms)?
     
@@ -42,9 +43,9 @@ package config is
     constant MONITOR_INPUT_NUM      : integer  := 32;    
 
     
-   constant INCLUDE_TDC : integer range c_NO to c_YES := c_NO;
-   constant TDC_CHANNEL_NUMBER : integer := 5;
-   constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 0;  --double edge type:  0, 1, 2,  3
+   constant INCLUDE_TDC : integer range c_NO to c_YES := c_YES;
+   constant TDC_CHANNEL_NUMBER : integer := 9;
+   constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 3;  --double edge type:  0, 1, 2,  3
    -- 0: single edge only,
    -- 1: same channel,
    -- 2: alternating channels,
@@ -193,6 +194,7 @@ function generateIncludedFeatures return std_logic_vector is
     t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
     t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
     t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+    t(55 downto 55) := std_logic_vector(to_unsigned(USE_200MHZOSCILLATOR,1));
     return t;
   end function;  
 
diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index 46b5888..54955e5 100644
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -724,6 +724,7 @@ end generate;
   cts_addon_triggers_in(17 downto 2) <= INP(79 downto 64);
   buscts_tx.nack <= '0';
   buscts_tx.ack  <= '0';
+
 ---------------------------------------------------------------------------
 -- TDC
 ---------------------------------------------------------------------------