From: Jan Michel Date: Thu, 24 Jul 2014 16:00:51 +0000 (+0200) Subject: some additional registers for ADC control X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=4809adb2087d2b83276b8768769d76fdecfcba16;p=trb3.git some additional registers for ADC control --- diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd index 696a98c..e9cd47f 100644 --- a/ADC/trb3_periph_adc.vhd +++ b/ADC/trb3_periph_adc.vhd @@ -212,6 +212,7 @@ architecture trb3_periph_adc_arch of trb3_periph_adc is signal adc_data : std_logic_vector(479 downto 0); signal adc_fco : std_logic_vector(119 downto 0); signal adc_data_valid : std_logic_vector(11 downto 0); + signal adc_ctrl : std_logic_vector(31 downto 0); signal busadc_rx : CTRLBUS_RX; signal busadc_tx : CTRLBUS_TX; @@ -468,6 +469,7 @@ THE_ADC_DATA_BUFFER : entity work.adc_data_buffer ADC_FCO_IN => adc_fco, ADC_DATA_VALID => adc_data_valid, ADC_STATUS_IN => debug_adc, + ADC_CONTROL_OUT => adc_ctrl, ADC_RESET_OUT => adc_restart_i, @@ -619,16 +621,16 @@ THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload FPGA_SDI(0) <= spi_SDO when spi_CS(2 downto 0) /= b"111" else '0'; spi_SDI <= FPGA_SDO(0) when spi_CS(2 downto 0) /= b"111" else '0'; - SPI_ADC_SCK <= spi_SCK when spi_CS(3) = '0' else '0'; - SPI_ADC_SDIO <= spi_SDO when spi_CS(3) = '0' else '0'; + SPI_ADC_SCK <= spi_SCK when spi_CS(3) = '0' else adc_ctrl(4); + SPI_ADC_SDIO <= spi_SDO when spi_CS(3) = '0' else adc_ctrl(5); + FPGA_SCK(1) <= '0' when spi_CS(3) = '0' else adc_ctrl(6); --CSB LMK_CLK <= spi_SCK when spi_CS(5 downto 4) /= b"11" else '1' ; LMK_DATA <= spi_SDO when spi_CS(5 downto 4) /= b"11" else '0' ; LMK_LE_1 <= spi_CS(4); -- active low LMK_LE_2 <= spi_CS(5); -- active low - POWER_ENABLE <= '1'; - + POWER_ENABLE <= adc_ctrl(0); --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- diff --git a/base/code/adc_data_buffer.vhd b/base/code/adc_data_buffer.vhd index 04c91c5..1afacb4 100644 --- a/base/code/adc_data_buffer.vhd +++ b/base/code/adc_data_buffer.vhd @@ -19,7 +19,7 @@ entity adc_data_buffer is ADC_FCO_IN : in std_logic_vector(DEVICES*RESOLUTION-1 downto 0); ADC_DATA_VALID : in std_logic_vector(DEVICES-1 downto 0); ADC_STATUS_IN : in std_logic_vector(31 downto 0); - + ADC_CONTROL_OUT: out std_logic_vector(31 downto 0); ADC_RESET_OUT : out std_logic; BUS_RX : in CTRLBUS_RX; @@ -75,6 +75,8 @@ end generate; fifo_wait_1 <= fifo_wait_0 when rising_edge(CLK); fifo_wait_2 <= fifo_wait_1 when rising_edge(CLK); +ADC_CONTROL_OUT <= ctrl_reg; + PROC_BUS : process begin wait until rising_edge(CLK); @@ -84,6 +86,7 @@ PROC_BUS : process begin ADC_RESET_OUT <= '0'; fifo_read <= fifo_full; fifo_wait_0 <= '0'; + fifo_reset <= '0'; if BUS_RX.read = '1' then if BUS_RX.addr(7 downto 0) = x"80" then @@ -111,6 +114,7 @@ PROC_BUS : process begin elsif BUS_RX.addr(7 downto 0) = x"81" then ADC_RESET_OUT <= BUS_RX.data(0); fifo_stop <= BUS_RX.data(1); + fifo_reset <= BUS_RX.data(2); BUS_TX.ack <= '1'; else BUS_TX.unknown <= '1'; diff --git a/base/trb3_periph_adc.lpf b/base/trb3_periph_adc.lpf index dc11dd1..5c6a0b7 100644 --- a/base/trb3_periph_adc.lpf +++ b/base/trb3_periph_adc.lpf @@ -196,7 +196,7 @@ LOCATE COMP "FPGA_SDI_1" SITE "G1"; LOCATE COMP "FPGA_SDO_0" SITE "T25"; LOCATE COMP "FPGA_SDO_1" SITE "T24"; DEFINE PORT GROUP "FPGA_group" "FPGA_*" ; -IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP; #################################################################