From: hadeshyp Date: Wed, 24 Jun 2009 15:24:03 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~425 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=481c92fc78adfc2994f75ebe8e7242f01ad13e75;p=trbnet.git *** empty log message *** --- diff --git a/lattice/ecp2m/pll_in25_out100.vhd b/lattice/ecp2m/pll_in25_out100.vhd index a5da686..f63b0db 100644 --- a/lattice/ecp2m/pll_in25_out100.vhd +++ b/lattice/ecp2m/pll_in25_out100.vhd @@ -67,20 +67,20 @@ architecture Structure of pll_in25_out100 is attribute PLLCAP of PLLDInst_0 : label is "DISABLED"; attribute PLLTYPE of PLLDInst_0 : label is "GPLL"; attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED"; - attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "60.000000"; + attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "50.000000"; attribute CLKOK_DIV of PLLDInst_0 : label is "2"; attribute CLKOS_BYPASS of PLLDInst_0 : label is "DISABLED"; - attribute FREQUENCY_PIN_CLKOP of PLLDInst_0 : label is "120.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLDInst_0 : label is "100.000000"; attribute CLKOP_BYPASS of PLLDInst_0 : label is "DISABLED"; attribute PHASE_CNTL of PLLDInst_0 : label is "STATIC"; attribute FDEL of PLLDInst_0 : label is "0"; attribute DUTY of PLLDInst_0 : label is "8"; attribute PHASEADJ of PLLDInst_0 : label is "0.0"; - attribute FREQUENCY_PIN_CLKI of PLLDInst_0 : label is "30"; + attribute FREQUENCY_PIN_CLKI of PLLDInst_0 : label is "25"; attribute CLKOP_DIV of PLLDInst_0 : label is "8"; attribute CLKFB_DIV of PLLDInst_0 : label is "4"; attribute CLKI_DIV of PLLDInst_0 : label is "1"; - attribute FIN of PLLDInst_0 : label is "30"; + attribute FIN of PLLDInst_0 : label is "25"; attribute syn_keep : boolean; attribute syn_noprune : boolean; attribute syn_noprune of Structure : architecture is true; diff --git a/media_interfaces/trb_net16_lsm_sfp.vhd b/media_interfaces/trb_net16_lsm_sfp.vhd index 0460625..141a96c 100644 --- a/media_interfaces/trb_net16_lsm_sfp.vhd +++ b/media_interfaces/trb_net16_lsm_sfp.vhd @@ -341,7 +341,7 @@ begin end if; when others => NEXT_STATE <= QRST; end case; - if ( (sfp_missing_in = '1') or (sfp_los_in = '1')) and CURRENT_STATE /= QRST then + if ( (sfp_missing_in = '1') or (sfp_los_in = '1') or RESET = '1') and CURRENT_STATE /= QRST then NEXT_STATE <= SLEEP; -- wait for SFP present signal next_ce_tctr <= '1'; next_rst_tctr <= '1'; diff --git a/media_interfaces/trb_net16_med_ecp_sfp_4.vhd b/media_interfaces/trb_net16_med_ecp_sfp_4.vhd index 353bca6..2a68529 100644 --- a/media_interfaces/trb_net16_med_ecp_sfp_4.vhd +++ b/media_interfaces/trb_net16_med_ecp_sfp_4.vhd @@ -270,7 +270,7 @@ component serdes_sfp_full_quad is signal refck2core : std_logic; signal clock : std_logic; - + signal reset_i : std_logic_vector(3 downto 0); --serdes connections signal tx_data : std_logic_vector(4*16-1 downto 0); signal tx_k : std_logic_vector(7 downto 0); @@ -328,7 +328,7 @@ component serdes_sfp_full_quad is -- status inputs from SFP signal sfp_prsnt_n : std_logic_vector(3 downto 0); -- synchronized input signals signal sfp_los : std_logic_vector(3 downto 0); -- synchronized input signals - + signal pwr_up : std_logic_vector(3 downto 0); signal led_counter : std_logic_vector(16 downto 0); signal rx_led, tx_led : std_logic_vector(3 downto 0); @@ -337,6 +337,15 @@ component serdes_sfp_full_quad is begin +-------------------------------------------------------------------------- +-- Internal Lane Resets +-------------------------------------------------------------------------- + + gen_reset_i : for i in 0 to 3 generate + reset_i(i) <= RESET or CTRL_OP(i*16+14); + pwr_up(i) <= not CTRL_OP(i*16+14); + end generate; + -------------------------------------------------------------------------- -- Main control state machine, startup control for SFP @@ -352,7 +361,7 @@ begin WIDTH => 2 ) port map( - RESET => RESET, + RESET => reset_i(i), D_IN(0) => SD_PRSNT_N_IN(i), D_IN(1) => SD_LOS_IN(i), CLK0 => SYSCLK, @@ -368,7 +377,7 @@ begin WIDTH => 2 ) port map( - RESET => RESET, + RESET => reset_i(i), D_IN => comb_rx_k(i*2+1 downto i*2), CLK0 => ff_rxhalfclk(i), CLK1 => SYSCLK, @@ -381,7 +390,7 @@ begin WIDTH => 2 ) port map( - RESET => RESET, + RESET => reset_i(i), D_IN => tx_k(i*2+1 downto i*2), CLK0 => ff_txhalfclk, CLK1 => SYSCLK, @@ -396,7 +405,7 @@ begin WIDTH => 16 ) port map( - RESET => reset, + RESET => reset_i(i), D_IN => comb_rx_data(i*16+15 downto i*16), CLK0 => ff_rxhalfclk(i), CLK1 => ff_rxhalfclk(i), @@ -409,7 +418,7 @@ begin WIDTH => 2 ) port map( - RESET => reset, + RESET => reset_i(i), D_IN => comb_rx_k(i*2+1 downto i*2), CLK0 => ff_rxhalfclk(i), CLK1 => ff_rxhalfclk(i), @@ -422,7 +431,7 @@ begin WIDTH => 2 ) port map( - RESET => RESET, + RESET => reset_i(i), D_IN(0) => rx_allow(i), D_IN(1) => tx_allow(i), CLK0 => sysclk, @@ -437,7 +446,7 @@ begin WIDTH => 1 ) port map( - RESET => RESET, + RESET => reset_i(i), D_IN(0) => rx_allow(i), CLK0 => ff_rxhalfclk(i), CLK1 => ff_rxhalfclk(i), @@ -450,7 +459,7 @@ begin WIDTH => 1 ) port map( - RESET => RESET, + RESET => reset_i(i), D_IN(0) => tx_allow(i), CLK0 => ff_txhalfclk, CLK1 => ff_txhalfclk, @@ -464,7 +473,7 @@ begin THE_SFP_LSM: trb_net16_lsm_sfp port map( SYSCLK => SYSCLK, - RESET => reset, + RESET => reset_i(i), CLEAR => clear, SFP_MISSING_IN => sfp_prsnt_n(i), SFP_LOS_IN => sfp_los(i), @@ -522,8 +531,8 @@ begin ffc_rrst_ch0 => '0', ffc_lane_tx_rst_ch0 => lane_rst(0), --lane_rst(0), ffc_lane_rx_rst_ch0 => lane_rst(0), - ffc_txpwdnb_ch0 => '1', - ffc_rxpwdnb_ch0 => '1', + ffc_txpwdnb_ch0 => pwr_up(0), + ffc_rxpwdnb_ch0 => pwr_up(0), ffs_rlos_lo_ch0 => link_error(0)(2), ffs_ls_sync_status_ch0 => link_ok(0), ffs_cc_underrun_ch0 => link_error(0)(3), @@ -553,8 +562,8 @@ begin ffc_rrst_ch1 => '0', ffc_lane_tx_rst_ch1 => lane_rst(1), --lane_rst(1), ffc_lane_rx_rst_ch1 => lane_rst(1), - ffc_txpwdnb_ch1 => '1', - ffc_rxpwdnb_ch1 => '1', + ffc_txpwdnb_ch1 => pwr_up(1), + ffc_rxpwdnb_ch1 => pwr_up(1), ffs_rlos_lo_ch1 => link_error(1)(2), ffs_ls_sync_status_ch1 => link_ok(1), ffs_cc_underrun_ch1 => link_error(1)(3), @@ -584,8 +593,8 @@ begin ffc_rrst_ch2 => '0', ffc_lane_tx_rst_ch2 => lane_rst(2), --lane_rst(2), ffc_lane_rx_rst_ch2 => lane_rst(2), - ffc_txpwdnb_ch2 => '1', - ffc_rxpwdnb_ch2 => '1', + ffc_txpwdnb_ch2 => pwr_up(2), + ffc_rxpwdnb_ch2 => pwr_up(2), ffs_rlos_lo_ch2 => link_error(2)(2), ffs_ls_sync_status_ch2 => link_ok(2), ffs_cc_underrun_ch2 => link_error(2)(3), @@ -615,8 +624,8 @@ begin ffc_rrst_ch3 => '0', ffc_lane_tx_rst_ch3 => lane_rst(3), --lane_rst(3), ffc_lane_rx_rst_ch3 => lane_rst(3), - ffc_txpwdnb_ch3 => '1', - ffc_rxpwdnb_ch3 => '1', + ffc_txpwdnb_ch3 => pwr_up(3), + ffc_rxpwdnb_ch3 => pwr_up(3), ffs_rlos_lo_ch3 => link_error(3)(2), ffs_ls_sync_status_ch3 => link_ok(3), ffs_cc_underrun_ch3 => link_error(3)(3), @@ -660,8 +669,8 @@ begin ffc_rrst_ch0 => '0', ffc_lane_tx_rst_ch0 => lane_rst(3), --lane_rst(0), ffc_lane_rx_rst_ch0 => lane_rst(3), - ffc_txpwdnb_ch0 => '1', - ffc_rxpwdnb_ch0 => '1', + ffc_txpwdnb_ch0 => pwr_up(3), + ffc_rxpwdnb_ch0 => pwr_up(3), ffs_rlos_lo_ch0 => link_error(3)(2), ffs_ls_sync_status_ch0 => link_ok(3), ffs_cc_underrun_ch0 => link_error(3)(3), @@ -691,8 +700,8 @@ begin ffc_rrst_ch1 => '0', ffc_lane_tx_rst_ch1 => lane_rst(2), --lane_rst(1), ffc_lane_rx_rst_ch1 => lane_rst(2), - ffc_txpwdnb_ch1 => '1', - ffc_rxpwdnb_ch1 => '1', + ffc_txpwdnb_ch1 => pwr_up(2), + ffc_rxpwdnb_ch1 => pwr_up(2), ffs_rlos_lo_ch1 => link_error(2)(2), ffs_ls_sync_status_ch1 => link_ok(2), ffs_cc_underrun_ch1 => link_error(2)(3), @@ -722,8 +731,8 @@ begin ffc_rrst_ch2 => '0', ffc_lane_tx_rst_ch2 => lane_rst(1), --lane_rst(2), ffc_lane_rx_rst_ch2 => lane_rst(1), - ffc_txpwdnb_ch2 => '1', - ffc_rxpwdnb_ch2 => '1', + ffc_txpwdnb_ch2 => pwr_up(1), + ffc_rxpwdnb_ch2 => pwr_up(1), ffs_rlos_lo_ch2 => link_error(1)(2), ffs_ls_sync_status_ch2 => link_ok(1), ffs_cc_underrun_ch2 => link_error(1)(3), @@ -753,8 +762,8 @@ begin ffc_rrst_ch3 => '0', ffc_lane_tx_rst_ch3 => lane_rst(0), --lane_rst(3), ffc_lane_rx_rst_ch3 => lane_rst(0), - ffc_txpwdnb_ch3 => '1', - ffc_rxpwdnb_ch3 => '1', + ffc_txpwdnb_ch3 => pwr_up(0), + ffc_rxpwdnb_ch3 => pwr_up(0), ffs_rlos_lo_ch3 => link_error(0)(2), ffs_ls_sync_status_ch3 => link_ok(0), ffs_cc_underrun_ch3 => link_error(0)(3), @@ -793,7 +802,7 @@ begin empty_out => fifo_rx_empty(i) ); - fifo_rx_reset(i) <= RESET or not rx_allow_q(i); + fifo_rx_reset(i) <= reset_i(i) or not rx_allow_q(i); fifo_rx_rd_en(i) <= '1'; -- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path @@ -822,7 +831,7 @@ begin THE_SYNC_PROC: process( SYSCLK ) begin if( rising_edge(SYSCLK) ) then - if RESET = '1' then + if reset_i(i) = '1' then med_dataready_out(i) <= '0'; else med_dataready_out(i) <= buf_med_dataready_out(i); @@ -838,7 +847,7 @@ begin begin if( rising_edge(SYSCLK) ) then last_fifo_rx_empty(i) <= fifo_rx_empty(i); - if RESET = '1' or rx_allow_q(i) = '0' then + if reset_i(i) = '1' or rx_allow_q(i) = '0' then rx_counter(i*3+2 downto i*3) <= c_H0; else if( buf_med_dataready_out(i) = '1' ) then @@ -870,7 +879,7 @@ begin empty_out => fifo_tx_empty(i) ); - fifo_tx_reset(i) <= reset or not tx_allow_q(i); + fifo_tx_reset(i) <= reset_i(i) or not tx_allow_q(i); fifo_tx_din(i*18+17 downto i*18) <= med_packet_num_in(i*3+2) & med_packet_num_in(i*3+0)& med_data_in(i*16+15 downto i*16); fifo_tx_wr_en(i) <= med_dataready_in(i) and tx_allow(i); fifo_tx_rd_en(i) <= tx_allow_qtx(i); diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 2c28a86..521144e 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -141,7 +141,6 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal HUB_STAT_ERRORBITS : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0); signal buf_HUB_STAT_CHANNEL : std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0); signal buf_STAT_POINTS_locked : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0); - signal buf_HUB_STAT_GEN : std_logic_vector (31 downto 0); signal buf_STAT_DEBUG : std_logic_vector (31 downto 0); signal buf_CTRL_DEBUG : std_logic_vector (31 downto 0); signal buf_MED_DATAREADY_OUT : std_logic_vector (MII_NUMBER-1 downto 0); @@ -171,9 +170,8 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal HUB_MED_CONNECTED : std_logic_vector (31 downto 0); signal HUB_CTRL_final_activepoints : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0); - signal HUB_CTRL_CHANNEL : std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0); signal HUB_CTRL_activepoints : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0); - signal HUB_CTRL_GEN : std_logic_vector (31 downto 0); + signal HUB_CTRL_media_interfaces_off: std_logic_vector (31 downto 0); signal HUB_ADDRESS : std_logic_vector (15 downto 0); signal HUBLOGIC_IPU_STAT_DEBUG : std_logic_vector (31 downto 0); @@ -202,7 +200,10 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is begin - SYNC_RESET : process(CLK) +--------------------------------------------------------------------- +--Generate various reset signals +--------------------------------------------------------------------- + proc_SYNC_RESET : process(CLK) begin if rising_edge(CLK) then reset_i <= RESET; @@ -222,12 +223,16 @@ begin --generate media resync gen_resync : for i in 0 to MII_NUMBER-1 generate resync(i) <= MED_STAT_OP(i*16+15); + MED_CTRL_OP(13+i*16 downto i*16) <= (others => '0'); + MED_CTRL_OP(14+i*16) <= HUB_CTRL_media_interfaces_off(i); MED_CTRL_OP(15+i*16) <= combined_resync; end generate; combined_resync <= or_all(resync); ---generate multiplexers +--------------------------------------------------------------------- +--Multiplexer +--------------------------------------------------------------------- gen_muxes: for i in 0 to MII_NUMBER-1 generate constant t : integer := 0; begin @@ -260,7 +265,11 @@ begin MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT; MED_DATA_OUT <= buf_MED_DATA_OUT; ---generate IOBufs for MII + + +--------------------------------------------------------------------- +--IOBufs +--------------------------------------------------------------------- gen_bufs : for j in 0 to MII_NUMBER-1 generate gen_iobufs: for k in 0 to 2**(c_MUX_WIDTH-1)-1 generate constant i : integer := j*2**(c_MUX_WIDTH-1)+k; @@ -324,7 +333,6 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; STAT_INIT_OBUF_DEBUG => IOBUF_STAT_INIT_OBUF_DEBUG((i+1)*32-1 downto i*32), STAT_REPLY_OBUF_DEBUG => IOBUF_STAT_REPLY_OBUF_DEBUG((i+1)*32-1 downto i*32) ); - end generate; gen_trmbuf: if HUB_USED_CHANNELS(k) = 0 generate IOBUF : trb_net16_term_buf @@ -352,7 +360,9 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; end generate; - +--------------------------------------------------------------------- +--API for control interface +--------------------------------------------------------------------- gen_ctrl_api : if 1 = 1 generate --just a dummy now constant i : integer := 2**(c_MUX_WIDTH-1)*MII_NUMBER; begin @@ -411,6 +421,10 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; STAT_FIFO_TO_APL => open ); end generate; + +--------------------------------------------------------------------- +--Connection for additional internal interfaces +--------------------------------------------------------------------- gen_int : if INT_NUMBER /= 0 generate gen_int1 : for i in 0 to INT_NUMBER-1 generate constant j : integer := i + 2**(c_MUX_WIDTH-1)*MII_NUMBER+1; @@ -444,7 +458,9 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; INT_REPLY_READ_OUT(INT_NUMBER) <= '0'; ---rearrange vectors for hub logic +--------------------------------------------------------------------- +--Connections between IOBuf and Hublogic +--------------------------------------------------------------------- gen_rearrange : for CHANNEL in 0 to 2**(c_MUX_WIDTH-1)-1 generate constant int_num : integer := calc_special_number(CHANNEL, INT_NUMBER, INT_CHANNELS); constant first_point_num : integer := calc_first_point_number(MII_NUMBER, CHANNEL, HUB_CTRL_CHANNELNUM, INT_NUMBER, INT_CHANNELS); @@ -577,22 +593,11 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; end generate; end generate; - gen_MED_CON : for i in 0 to MII_NUMBER-1 generate - process(m_ERROR_IN) - begin - if m_ERROR_IN((i+1)*3-1 downto i*3) /= ERROR_OK then - HUB_MED_CONNECTED(i) <= '0'; - else - HUB_MED_CONNECTED(i) <= '1'; - end if; - end process; - end generate; - - -HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); ---generate hub logic +--------------------------------------------------------------------- +--Hub Logic +--------------------------------------------------------------------- gen_hub_logic: for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate constant point_num : integer := calc_point_number (MII_NUMBER, i, HUB_CTRL_CHANNELNUM, INT_NUMBER, INT_CHANNELS); constant first_point_num : integer := calc_first_point_number(MII_NUMBER, i, HUB_CTRL_CHANNELNUM, INT_NUMBER, INT_CHANNELS); @@ -629,7 +634,6 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); STAT => buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16), STAT_POINTS_locked => buf_STAT_POINTS_locked((i+1)*32-1 downto i*32), STAT_ERRORBITS => open, --HUB_STAT_ERRORBITS(i+1)*32-1 downto i*32), - CTRL => HUB_CTRL_CHANNEL((i+1)*16-1 downto i*16), CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32) ); end generate; @@ -663,7 +667,6 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); STAT_DEBUG => HUBLOGIC_IPU_STAT_DEBUG(31 downto 0), STAT_POINTS_locked => buf_STAT_POINTS_locked((i+1)*32-1 downto i*32), STAT_ERRORBITS => open, --HUB_STAT_ERRORBITS(i+1)*32-1 downto i*32), - CTRL => HUB_CTRL_CHANNEL((i+1)*16-1 downto i*16), CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32) ); buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16) <= (others => '0'); @@ -671,13 +674,17 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); end generate; end generate; + +--------------------------------------------------------------------- +--Control RegIO +--------------------------------------------------------------------- hub_control : trb_net16_regIO generic map( NUM_STAT_REGS => 3, NUM_CTRL_REGS => 3, INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" & x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF", - USED_CTRL_REGS => "01111111", + USED_CTRL_REGS => "00011111", USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" & x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF", USE_DAT_PORT => c_NO, @@ -737,7 +744,9 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); DAT_WRITE_ACK_IN => '0' ); - +--------------------------------------------------------------------- +--1-wire interface +--------------------------------------------------------------------- gen_1wire : if USE_ONEWIRE = c_YES generate onewire_interface : trb_net_onewire generic map( @@ -758,6 +767,7 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); STAT => open ); end generate; + gen_1wire_monitor : if USE_ONEWIRE = c_MONITOR generate onewire_interface : trb_net_onewire_listener port map( @@ -777,64 +787,68 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); +--------------------------------------------------------------------- +--Status of media interfaces +--------------------------------------------------------------------- + gen_MED_CON : for i in 0 to MII_NUMBER-1 generate + process(CLK) + begin + if rising_edge(CLK) then + if m_ERROR_IN((i+1)*3-1 downto i*3) /= ERROR_OK then + HUB_MED_CONNECTED(i) <= '0'; + else + HUB_MED_CONNECTED(i) <= '1'; + end if; + end if; + end process; + end generate; - --debug Status and Control ports - buf_STAT_DEBUG(15 downto 0) <= HUBLOGIC_IPU_STAT_DEBUG(15 downto 0); --- buf_STAT_DEBUG(2 downto 0) <= buf_MED_PACKET_NUM_OUT(2 downto 0); --- buf_STAT_DEBUG(3) <= buf_MED_DATAREADY_OUT(0); --- buf_STAT_DEBUG(7 downto 4) <= buf_MED_DATA_OUT(3 downto 0); --- buf_STAT_DEBUG(10 downto 8) <= MED_PACKET_NUM_IN(5 downto 3); --- buf_STAT_DEBUG(11) <= MED_DATAREADY_IN(1); --- buf_STAT_DEBUG(12) <= m_DATAREADY_OUT(0); --- buf_STAT_DEBUG(15 downto 13) <= m_PACKET_NUM_OUT(2 downto 0); - --- buf_STAT_DEBUG(17 downto 16) <= hub_to_buf_INIT_DATAREADY(1 downto 0); --- buf_STAT_DEBUG(20 downto 18) <= hub_to_buf_INIT_PACKET_NUM(2 downto 0); - buf_STAT_DEBUG(18 downto 16) <= IOBUF_IBUF_BUFFER(20+32*6 downto 18+32*6); - buf_STAT_DEBUG(21 downto 19) <= IOBUF_IBUF_BUFFER(20+32*7 downto 18+32*7); - buf_STAT_DEBUG(25 downto 22) <= buf_to_hub_REPLY_DATA(6*c_DATA_WIDTH+3 downto 6*c_DATA_WIDTH); - buf_STAT_DEBUG(26) <= buf_to_hub_REPLY_DATAREADY(6); - buf_STAT_DEBUG(30 downto 27) <= buf_to_hub_REPLY_DATA(7*c_DATA_WIDTH+3 downto 7*c_DATA_WIDTH); - buf_STAT_DEBUG(31) <= buf_to_hub_REPLY_DATAREADY(7); - --- STAT_DEBUG(0) <= comb_dataready; --- STAT_DEBUG(3 downto 1) <= transfer_counter; --- STAT_DEBUG(4) <= MED_DATAREADY_OUT; --- STAT_DEBUG(7 downto 5) <= MED_PACKET_NUM_OUT; --- STAT_DEBUG(8) <= sbuf_free; --- STAT_DEBUG(9) <= comb_next_read; - --- buf_STAT_DEBUG(31 downto 20) <= TEMP_OUT; - --- buf_STAT_DEBUG(3) <= MED_DATAREADY_IN(0); - +HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); - buf_HUB_STAT_GEN <= (others => '0'); +--------------------------------------------------------------------- +--Status and Control Registers +--------------------------------------------------------------------- - --Registers for RegIO +--Usual common stat reg, trigger counters are not in use here HC_COMMON_STAT_REGS(19 downto 0) <= (others => '0'); HC_COMMON_STAT_REGS(31 downto 20) <= TEMP_OUT; HC_COMMON_STAT_REGS(63 downto 32) <= (others => '0'); +--Status Registers HC_STAT_REGS(2**(c_MUX_WIDTH-1)*32-1 downto 0) <= buf_STAT_POINTS_locked; - HC_STAT_REGS(5*32-1 downto 4*32) <= buf_HUB_STAT_GEN; + HC_STAT_REGS(5*32-1 downto 4*32) <= HUB_MED_CONNECTED; HC_STAT_REGS(8*32-1 downto 5*32) <= (others => '0'); --unused regs - HUB_CTRL_activepoints <= HC_CTRL_REGS(2**(c_MUX_WIDTH-1)*32-1 downto 0); - HUB_CTRL_GEN <= HC_CTRL_REGS(159 downto 128); - HUB_CTRL_CHANNEL <= HC_CTRL_REGS(160+2**(c_MUX_WIDTH-1)*16-1 downto 160); +--Control Registers + HUB_CTRL_activepoints <= HC_CTRL_REGS(2**2*32-1 downto 0); + HUB_CTRL_media_interfaces_off <= HC_CTRL_REGS(2**2*32+31 downto 2**2*32); + + +--------------------------------------------------------------------- +--Debugging Signals +--------------------------------------------------------------------- + + --debug Status and Control ports + buf_STAT_DEBUG(15 downto 0) <= HUBLOGIC_IPU_STAT_DEBUG(15 downto 0); + buf_STAT_DEBUG(18 downto 16) <= IOBUF_IBUF_BUFFER(20+32*6 downto 18+32*6); + buf_STAT_DEBUG(21 downto 19) <= IOBUF_IBUF_BUFFER(20+32*7 downto 18+32*7); + buf_STAT_DEBUG(25 downto 22) <= buf_to_hub_REPLY_DATA(6*c_DATA_WIDTH+3 downto 6*c_DATA_WIDTH); + buf_STAT_DEBUG(26) <= buf_to_hub_REPLY_DATAREADY(6); + buf_STAT_DEBUG(30 downto 27) <= buf_to_hub_REPLY_DATA(7*c_DATA_WIDTH+3 downto 7*c_DATA_WIDTH); + buf_STAT_DEBUG(31) <= buf_to_hub_REPLY_DATAREADY(7); + IOBUF_CTRL_GEN <= (others => '0'); --map regio registers to stat & ctrl outputs STAT_COMMON_STAT_REGS <= HC_COMMON_STAT_REGS; STAT_COMMON_CTRL_REGS <= HC_COMMON_CTRL_REGS; STAT_REGS <= HC_STAT_REGS; STAT_CTRL_REGS <= HC_CTRL_REGS; - HUB_STAT_GEN <= buf_HUB_STAT_GEN; HUB_STAT_CHANNEL <= buf_HUB_STAT_CHANNEL; STAT_DEBUG <= buf_STAT_DEBUG; + HUB_STAT_GEN <= (others => '0'); end architecture; diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index 9711d97..6000fba 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -194,7 +194,6 @@ package trb_net16_hub_func is STAT_DEBUG : out std_logic_vector (31 downto 0); STAT_POINTS_locked : out std_logic_vector (31 downto 0); STAT_ERRORBITS : out std_logic_vector (31 downto 0); - CTRL : in std_logic_vector (15 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1') ); end component; @@ -230,7 +229,6 @@ package trb_net16_hub_func is STAT : out std_logic_vector (15 downto 0); STAT_POINTS_locked : out std_logic_vector (31 downto 0); STAT_ERRORBITS : out std_logic_vector (31 downto 0); - CTRL : in std_logic_vector (15 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0) ); end component; diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd index 84f1ba9..ee8b2d5 100644 --- a/trb_net16_hub_ipu_logic.vhd +++ b/trb_net16_hub_ipu_logic.vhd @@ -43,7 +43,6 @@ entity trb_net16_hub_ipu_logic is STAT_DEBUG : out std_logic_vector (31 downto 0); STAT_POINTS_locked : out std_logic_vector (31 downto 0); STAT_ERRORBITS : out std_logic_vector (31 downto 0); - CTRL : in std_logic_vector (15 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1') ); end entity; @@ -671,7 +670,7 @@ begin begin if rising_edge(CLK) then if RESET = '1' or reply_data_counter_reset = '1' then - reply_data_counter <= (others => '1'); + reply_data_counter <= (others => '0'); elsif last_comb_REPLY_POOL_DATAREADY = '1' and (packet_counter = c_F1 or packet_counter = c_F3) then reply_data_counter <= reply_data_counter + 1; end if; @@ -906,6 +905,7 @@ reply_compare_finished <= reply_compare_start; start_read_padding <= reply_arbiter_result; elsif or_all(current_reply_reading_TRM and reply_arbiter_result) = '1' then -- elsif or_all(reply_arbiter_result and REPLY_DATAREADY_IN)='1' then + reply_data_counter_reset <= '1'; reply_arbiter_CLK_EN <= '1'; end if; diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index a98d58b..17c0da5 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -39,7 +39,6 @@ entity trb_net16_hub_logic is STAT : out std_logic_vector (15 downto 0); STAT_POINTS_locked : out std_logic_vector (31 downto 0); STAT_ERRORBITS : out std_logic_vector (31 downto 0); - CTRL : in std_logic_vector (15 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1') ); end entity; diff --git a/trb_net16_regio_bus_handler.vhd b/trb_net16_regio_bus_handler.vhd index 6632538..65d2f71 100644 --- a/trb_net16_regio_bus_handler.vhd +++ b/trb_net16_regio_bus_handler.vhd @@ -9,7 +9,7 @@ use work.trb_net_components.all; entity trb_net16_regio_bus_handler is generic( - PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 2; + PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 3; PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0')); PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0) ); @@ -27,11 +27,11 @@ entity trb_net16_regio_bus_handler is DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request - BUS_ADDR_OUT : out std_logic_vector(15 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); + BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0); + BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0); BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_TIMEOUT_OUT : out std_logic; + BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); BUS_DATA_IN : in std_logic_vector(32*PORT_NUMBER-1 downto 0); BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); @@ -47,19 +47,19 @@ end entity; architecture regio_bus_handler_arch of trb_net16_regio_bus_handler is - signal port_select : std_logic_vector(PORT_NUMBER-1 downto 0); - signal next_port_select : std_logic_vector(PORT_NUMBER-1 downto 0); signal port_select_int : integer range 0 to c_BUS_HANDLER_MAX_PORTS; signal next_port_select_int : integer range 0 to c_BUS_HANDLER_MAX_PORTS; - signal buf_DAT_DATA_OUT : std_logic_vector(31 downto 0); - signal buf_DAT_DATAREADY_OUT : std_logic; - signal buf_DAT_WRITE_ACK_OUT : std_logic; - signal buf_DAT_NO_MORE_DATA_OUT : std_logic; - signal buf_BUS_READ_OUT : std_logic_vector(PORT_NUMBER-1 downto 0); signal buf_BUS_WRITE_OUT : std_logic_vector(PORT_NUMBER-1 downto 0); + signal buf_BUS_DATA_OUT : std_logic_vector(31 downto 0); + signal buf_BUS_ADDR_OUT : std_logic_vector(15 downto 0); + signal buf_BUS_DATA_IN : std_logic_vector(32*PORT_NUMBER+31 downto 0); + signal buf_BUS_DATAREADY_IN : std_logic_vector(PORT_NUMBER downto 0); + signal buf_BUS_WRITE_ACK_IN : std_logic_vector(PORT_NUMBER downto 0); + signal buf_BUS_NO_MORE_DATA_IN : std_logic_vector(PORT_NUMBER downto 0); + signal buf_BUS_UNKNOWN_ADDR_IN : std_logic_vector(PORT_NUMBER downto 0); begin @@ -71,11 +71,8 @@ begin begin gen_port_select : for i in 0 to PORT_NUMBER-1 loop next_port_select_int <= PORT_NUMBER; - if DAT_ADDR_IN(15 downto PORT_ADDR_MASK(i)) = PORT_ADDRESSES(15 downto PORT_ADDR_MASK(i)) then - next_port_select(i) <= '1'; + if DAT_ADDR_IN(15 downto PORT_ADDR_MASK(i)) = PORT_ADDRESSES(i)(15 downto PORT_ADDR_MASK(i)) then next_port_select_int <= i; - else - next_port_select(i) <= '0'; end if; end loop; end process; @@ -84,10 +81,8 @@ begin begin if rising_edge(CLK) then if RESET = '1' then - port_select <= (others => '0'); port_select_int <= 0; - else - port_select <= next_port_select; + elsif DAT_WRITE_ENABLE_IN = '1' or DAT_READ_ENABLE_IN = '1' then port_select_int <= next_port_select_int; end if; end if; @@ -107,6 +102,8 @@ begin else buf_BUS_READ_OUT <= (others => '0'); buf_BUS_WRITE_OUT <= (others => '0'); + buf_BUS_DATA_OUT <= DAT_DATA_IN; + buf_BUS_ADDR_OUT <= DAT_ADDR_IN; if DAT_READ_ENABLE_IN = '1' then buf_BUS_READ_OUT(next_port_select_int) <= '1'; end if; @@ -117,14 +114,49 @@ begin end if; end process; +--------------------------------------------------------------------- +--Map Data Outputs +--------------------------------------------------------------------- + + BUS_READ_ENABLE_OUT <= buf_BUS_READ_OUT; + BUS_WRITE_ENABLE_OUT<= buf_BUS_WRITE_OUT; + gen_bus_outputs : for i in 0 to PORT_NUMBER-1 generate + BUS_DATA_OUT(i*32+31 downto i*32) <= buf_BUS_DATA_OUT; + BUS_ADDR_OUT(i*16+15 downto i*16) <= buf_BUS_ADDR_OUT; + BUS_TIMEOUT_OUT(i) <= DAT_TIMEOUT_IN; + end generate; +--------------------------------------------------------------------- +--Pack Data Inputs and Dummy Input +--------------------------------------------------------------------- + + buf_BUS_DATA_IN(PORT_NUMBER*32-1 downto 0) <= BUS_DATA_IN; + buf_BUS_DATAREADY_IN(PORT_NUMBER-1 downto 0) <= BUS_DATAREADY_IN; + buf_BUS_WRITE_ACK_IN(PORT_NUMBER-1 downto 0) <= BUS_WRITE_ACK_IN; + buf_BUS_NO_MORE_DATA_IN(PORT_NUMBER-1 downto 0) <= BUS_NO_MORE_DATA_IN; + buf_BUS_UNKNOWN_ADDR_IN(PORT_NUMBER-1 downto 0) <= BUS_UNKNOWN_ADDR_IN; + buf_BUS_DATA_IN(PORT_NUMBER*32+31 downto PORT_NUMBER*32) <= (others => '0'); + buf_BUS_DATAREADY_IN(PORT_NUMBER) <= '0'; + buf_BUS_WRITE_ACK_IN(PORT_NUMBER) <= '0'; + buf_BUS_NO_MORE_DATA_IN(PORT_NUMBER) <= '0'; + buf_BUS_UNKNOWN_ADDR_IN(PORT_NUMBER) <= '1'; + --------------------------------------------------------------------- --Multiplex Data Output --------------------------------------------------------------------- + DAT_DATA_OUT <= buf_BUS_DATA_IN(port_select_int*32+31 downto port_select_int*32); + DAT_DATAREADY_OUT <= buf_BUS_DATAREADY_IN(port_select_int); + DAT_WRITE_ACK_OUT <= buf_BUS_WRITE_ACK_IN(port_select_int); + DAT_NO_MORE_DATA_OUT <= buf_BUS_NO_MORE_DATA_IN(port_select_int); + DAT_UNKNOWN_ADDR_OUT <= buf_BUS_UNKNOWN_ADDR_IN(port_select_int); +--------------------------------------------------------------------- +--Debugging +--------------------------------------------------------------------- + STAT_DEBUG <= (others => '0'); end architecture; \ No newline at end of file diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 1704e99..62eecc4 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -1074,6 +1074,47 @@ package trb_net_components is + component trb_net16_regio_bus_handler is + generic( + PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 3; + PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0')); + PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0) + ); + port( + CLK : in std_logic; + RESET : in std_logic; + DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus + DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint + DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint + DAT_READ_ENABLE_IN : in std_logic; -- read pulse + DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse + DAT_TIMEOUT_IN : in std_logic; -- access timed out + DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested + DAT_WRITE_ACK_OUT : out std_logic; -- data accepted + DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now + DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request + + BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0); + BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0); + BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); + + BUS_DATA_IN : in std_logic_vector(32*PORT_NUMBER-1 downto 0); + BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); + + STAT_DEBUG : out std_logic_vector(31 downto 0) + ); + end component; + + + + + + component trb_net16_sbuf is generic ( VERSION : integer := 0