From: Jan Michel <j.michel@gsi.de>
Date: Fri, 2 Feb 2018 10:56:58 +0000 (+0100)
Subject: Update project files with changed files
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=48a5111615b9c3269ffe98c54146a1dec0267907;p=trb3sc.git

Update project files with changed files
---

diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj
index 320b823..0938f50 100644
--- a/cts/trb3sc_cts.prj
+++ b/cts/trb3sc_cts.prj
@@ -272,8 +272,8 @@ add_file -vhdl -lib work "../../trb3sc/tdc_release/bit_sync.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/BusHandler_record.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel_200.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel.vhd"
-# add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd"
-add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd"
+# add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/fallingEdgeDetect.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/hit_mux.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/LogicAnalyser.vhd"
diff --git a/pinout/basic_constraints.lpf b/pinout/basic_constraints.lpf
index 6b11454..e2fa188 100644
--- a/pinout/basic_constraints.lpf
+++ b/pinout/basic_constraints.lpf
@@ -9,9 +9,9 @@ BLOCK RD_DURING_WR_PATHS ;
 
 SYSCONFIG MCCLK_FREQ = 20;
 
-FREQUENCY PORT CLK_CORE_PCLK         240 MHz;
-FREQUENCY PORT CLK_CORE_PLL_LEFT     240 MHz;
-FREQUENCY PORT CLK_CORE_PLL_RIGHT    240 MHz;
+FREQUENCY PORT CLK_CORE_PCLK         200 MHz;
+FREQUENCY PORT CLK_CORE_PLL_LEFT     200 MHz;
+FREQUENCY PORT CLK_CORE_PLL_RIGHT    200 MHz;
 
 FREQUENCY PORT CLK_SUPPL_PCLK         125 MHz;
 FREQUENCY PORT CLK_SUPPL_PLL_LEFT     125 MHz;
@@ -47,7 +47,7 @@ FREQUENCY NET "THE_MEDIA_INT*/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps
 # LOCATE UGROUP "THE_TOOLS/THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
 # LOCATE UGROUP "THE_TOOLS/THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
 
-#main serdes is PCSB for stand-along or PCSA for crate operation
+#main serdes is PCSB for stand-alone or PCSA for crate operation
 LOCATE COMP          "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSA" ;
 LOCATE COMP          "THE_MEDIA_INTERFACE/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB" ;
 #REGION               "MEDIA_UPLINK" "R96C107D" 19 24;
diff --git a/scripts/nodes_frankfurt_adcaddon.txt b/scripts/nodes_frankfurt_adcaddon.txt
new file mode 100644
index 0000000..ad3ae2a
--- /dev/null
+++ b/scripts/nodes_frankfurt_adcaddon.txt
@@ -0,0 +1,13 @@
+// nodes file for parallel place&route
+
+[jspc29]
+SYSTEM = linux
+CORENUM = 3
+ENV = /d/jspc29/lattice/36_settings.sh
+WORKDIR = /d/jspc22/trb/git/trb3sc/adcaddon/workdir
+
+[jspc57]
+SYSTEM = linux
+CORENUM = 7
+ENV = /d/jspc29/lattice/36_settings.sh
+WORKDIR = /d/jspc22/trb/git/trb3sc/adcaddon/workdir
diff --git a/tdctemplate/config_compile_frankfurt.pl b/tdctemplate/config_compile_frankfurt.pl
index 611f005..c391ae6 100644
--- a/tdctemplate/config_compile_frankfurt.pl
+++ b/tdctemplate/config_compile_frankfurt.pl
@@ -4,7 +4,6 @@ lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
 lattice_path                 => '/d/jspc29/lattice/diamond/3.10_x64',
 synplify_path                => '/d/jspc29/lattice/synplify/N-2017.09-1/',
 nodelist_file                => 'nodes_frankfurt.txt',
-# synplify_command             => "ssh -p 52238 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/tdctemplate/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/L-2016.09-1/bin/synplify_premier_dp -batch ../trb3sc_tdctemplate.prj\" #",
 #Include only necessary lpf files
 #pinout_file                  => 'trb3sc_32pin', #name of pin-out file, if not equal TOPNAME
 pinout_file                  => 'trb3sc_padiwa', #name of pin-out file, if not equal TOPNAME
diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj
index 60ff437..57026ea 100644
--- a/tdctemplate/trb3sc_tdctemplate.prj
+++ b/tdctemplate/trb3sc_tdctemplate.prj
@@ -190,8 +190,8 @@ add_file -vhdl -lib work "../../trb3sc/tdc_release/bit_sync.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/BusHandler_record.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel_200.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel.vhd"
-# add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd"
-add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd"
+#add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/fallingEdgeDetect.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/hit_mux.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/LogicAnalyser.vhd"
diff --git a/template/trb3sc_basic.prj b/template/trb3sc_basic.prj
index 4d7d00e..dfa653d 100644
--- a/template/trb3sc_basic.prj
+++ b/template/trb3sc_basic.prj
@@ -65,7 +65,7 @@ add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd"
 #Basic Infrastructure
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
-add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200_200oscillator.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd"
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
 add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"