From: Adrian Weber Date: Mon, 1 Feb 2021 15:04:51 +0000 (+0100) Subject: include original register 0x006 information to calibration entity X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=48b7e6096ddefaf1fc45f8f2e94801d31ee554a7;p=dirich.git include original register 0x006 information to calibration entity --- diff --git a/combiner_cts/code_EBR/Calibration.vhd b/combiner_cts/code_EBR/Calibration.vhd index 5870c2f..93fcb5d 100644 --- a/combiner_cts/code_EBR/Calibration.vhd +++ b/combiner_cts/code_EBR/Calibration.vhd @@ -268,9 +268,7 @@ begin BUS_TX.data( 9 downto 0) <= Bus_min; when x"5" => BUS_TX.data(31 downto 10) <= (others => '0'); BUS_TX.data( 9 downto 0) <= Bus_max; - when x"6" => BUS_TX.data(31 downto 16) <= (others => '0'); - BUS_TX.data(15 downto 0) <= MY_ADDRESS_IN; - --BUS_TX.data <= std_logic_vector(docal_debug_in); + when x"6" => BUS_TX.data <= std_logic_vector(docal_debug_in); when x"7" => BUS_TX.data <= std_logic_vector(docal_debug_out); when x"8" => BUS_TX.data(11 downto 8) <= FPGA_Lim; BUS_TX.data(7) <= '0';