From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Thu, 28 May 2015 11:41:59 +0000 (+0200)
Subject: Add dqsinput_4x5 file to project
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=498acaca9056c095e2f40d9174aab09247b58663;p=trb3.git

Add dqsinput_4x5 file to project
---

diff --git a/ADC/trb3_periph_adc.prj b/ADC/trb3_periph_adc.prj
index b90c68d..ae59479 100644
--- a/ADC/trb3_periph_adc.prj
+++ b/ADC/trb3_periph_adc.prj
@@ -151,6 +151,7 @@ add_file -vhdl -lib "work" "../base/cores/pll_adc10bit_64.vhd"
 add_file -vhdl -lib "work" "../base/cores/pll_adc10bit_80.vhd"
 add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd"
 add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd"
+add_file -vhdl -lib "work" "../base/cores/dqsinput_4x5.vhd"
 add_file -vhdl -lib "work" "sim/dqsinput_dummy.vhd"
 add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200_50.vhd"
 add_file -vhdl -lib "work" "../base/code/sedcheck.vhd"
@@ -207,4 +208,4 @@ if {$INCLUDE_TDC == 1} {
    add_file -vhdl -lib "work" "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd"
    add_file -vhdl -lib "work" "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd"
    add_file -vhdl -lib "work" "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
-}
\ No newline at end of file
+}