From: hadeshyp Date: Fri, 20 Apr 2012 17:48:28 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~88 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=4a66f79aa9c1c13dc01417a2d7fed445704fba35;p=trbnet.git *** empty log message *** --- diff --git a/lattice/ecp2m/lattice_ecp2m_fifo.vhd b/lattice/ecp2m/lattice_ecp2m_fifo.vhd index e14c049..b7ddf46 100644 --- a/lattice/ecp2m/lattice_ecp2m_fifo.vhd +++ b/lattice/ecp2m/lattice_ecp2m_fifo.vhd @@ -7,6 +7,21 @@ use work.trb_net_std.all; package lattice_ecp2m_fifo is + +component fifo_19x16 is + port ( + Data: in std_logic_vector(18 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(18 downto 0); + WCNT: out std_logic_vector(4 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end component; + component fifo_var_oreg is generic( FIFO_WIDTH : integer range 1 to 64 := 36; diff --git a/media_interfaces/trb_net16_lsm_sfp.vhd b/media_interfaces/trb_net16_lsm_sfp.vhd index 5b20cc6..7969d52 100644 --- a/media_interfaces/trb_net16_lsm_sfp.vhd +++ b/media_interfaces/trb_net16_lsm_sfp.vhd @@ -15,7 +15,8 @@ use work.trb_net_std.all; entity trb_net16_lsm_sfp is generic( - CHECK_FOR_CV : integer := c_YES + CHECK_FOR_CV : integer := c_YES; + HIGHSPEED_STARTUP : integer := c_NO ); port( SYSCLK : in std_logic; -- fabric clock (100MHz) @@ -113,7 +114,11 @@ begin if ( rst_tctr = '1' ) then timing_ctr <= (others => '0'); elsif( ce_tctr = '1' ) then - timing_ctr <= timing_ctr + 1; + if HIGHSPEED_STARTUP = c_NO then + timing_ctr <= timing_ctr + 1; + else + timing_ctr <= timing_ctr + 4; + end if; end if; end if; end process THE_TIMING_COUNTER_PROC; @@ -344,7 +349,7 @@ begin -- end if; when others => NEXT_STATE <= QRST; end case; - if ( (sfp_missing_in = '1') or (sfp_los_in = '1') or RESET = '1') and CURRENT_STATE /= QRST then + if ( (sfp_missing_in = '1') or (sfp_los_in = '1') or RESET = '1' or CTRL_OP(13) = '1') and CURRENT_STATE /= QRST then NEXT_STATE <= SLEEP; -- wait for SFP present signal next_ce_tctr <= '1'; next_rst_tctr <= '1'; diff --git a/media_interfaces/trb_net16_med_ecp3_sfp.vhd b/media_interfaces/trb_net16_med_ecp3_sfp.vhd index fdd7ed3..d0dafda 100644 --- a/media_interfaces/trb_net16_med_ecp3_sfp.vhd +++ b/media_interfaces/trb_net16_med_ecp3_sfp.vhd @@ -388,6 +388,9 @@ THE_TX_SYNC: signal_sync -------------------------------------------------------------------------- THE_SFP_LSM: trb_net16_lsm_sfp + generic map ( + HIGHSPEED_STARTUP => c_YES + ) port map( SYSCLK => sysclk, RESET => reset_i, diff --git a/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd b/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd index 1b9e80e..7fc591e 100644 --- a/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd +++ b/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd @@ -507,6 +507,9 @@ tx_allow_qtx <= tx_allow when rising_edge(clk_tx); -------------------------------------------------------------------------- gen_LSM : for i in 0 to 3 generate THE_SFP_LSM: trb_net16_lsm_sfp + generic map ( + HIGHSPEED_STARTUP => c_YES + ) port map( SYSCLK => clk_sys, RESET => reset_i, diff --git a/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd b/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd index f06d02f..23d3604 100644 --- a/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd @@ -265,11 +265,15 @@ signal buf_med_dataready_out : std_logic_vector(3 downto 0); signal buf_med_data_out : std_logic_vector(63 downto 0); signal buf_med_packet_num_out : std_logic_vector(11 downto 0); - +signal delay_counter : std_logic_vector(7 downto 0); signal led_counter : std_logic_vector(15 downto 0); signal rx_led : std_logic_vector(3 downto 0); signal tx_led : std_logic_vector(3 downto 0); +signal med_state_shift_i : std_logic_vector(3 downto 0); +signal med_state_shift_ii : std_logic_vector(3 downto 0); +signal med_state_i : std_logic_vector(11 downto 0); + signal FSM_STAT_OP : std_logic_vector(4*16-1 downto 0); signal FSM_STAT_DEBUG : std_logic_vector(4*32-1 downto 0); signal FSM_CTRL_OP : std_logic_vector(4*16-1 downto 0); @@ -749,12 +753,30 @@ end generate; begin if( rising_edge(CLK) ) then led_counter <= led_counter + 1; + if led_counter = 0 then + delay_counter <= delay_counter + 1; + end if; end if; end process; - - - + gen_med_state : for i in 0 to 3 generate + proc_med_state : process begin + wait until rising_edge(CLK); + if FSM_STAT_OP(i*16+2 downto i*16) /= "000" then + med_state_i(i*3+2 downto i*3) <= FSM_STAT_OP(i*16+2 downto i*16); + med_state_shift_i(i) <= '0'; + med_state_shift_ii(i) <= '0'; + elsif delay_counter = 0 then + med_state_shift_i(i) <= '1'; + med_state_shift_ii(i) <= med_state_shift_i(i); + if med_state_shift_ii(i) = '1' then + med_state_i(i*3+2 downto i*3) <= ERROR_OK; + else + med_state_i(i*3+2 downto i*3) <= ERROR_WAIT; + end if; + end if; + end process; + end generate; ----------------------------------------------------------------------- @@ -820,11 +842,13 @@ end generate; FSM_CTRL_OP <= CTRL_OP; + ----------------------------------------------------------------------- --Status & Debug ----------------------------------------------------------------------- gen_stat : for i in 0 to 3 generate - STAT_OP(i*16+7 downto i*16+0) <= FSM_STAT_OP(i*16+7 downto i*16+0); + STAT_OP(i*16+2 downto i*16+0) <= med_state_i(i*3+2 downto i*3); + STAT_OP(i*16+7 downto i*16+3) <= FSM_STAT_OP(i*16+7 downto i*16+3); STAT_OP(i*16+8) <= start_retransmit_i(i); STAT_OP(i*16+9) <= FSM_STAT_OP(i*16+9); STAT_OP(i*16+10) <= rx_led(i); diff --git a/pinout/mdc_oep3.lpf b/pinout/mdc_oep3.lpf index ee53144..b093ea7 100644 --- a/pinout/mdc_oep3.lpf +++ b/pinout/mdc_oep3.lpf @@ -69,12 +69,16 @@ IOBUF PORT "COM_STOP_P" IO_TYPE=LVDS25; ################################################################# #JTAG to CPLD ################################################################# -# LOCATE COMP "JTAG_TCK" SITE "L6"; -# LOCATE COMP "JTAG_TMS" SITE "N5"; -# LOCATE COMP "JTAG_TDO" SITE "M6"; -# LOCATE COMP "JTAG_TDI" SITE "M5"; -# DEFINE PORT GROUP "jtag_grp" "JTAG*" ; -# IOBUF GROUP "jtag_grp" IO_TYPE=LVTTL33 PULLMODE=DOWN ; +#LOCATE COMP "JTAG_TCK" SITE "L6"; +#IOBUF PORT "JTAG_TCK" IO_TYPE=LVTTL33 PULLMODE=DOWN ; +#LOCATE COMP "JTAG_TMS" SITE "N5"; +#IOBUF PORT "JTAG_TMS" IO_TYPE=LVTTL33 PULLMODE=UP ; +#LOCATE COMP "JTAG_TDO" SITE "M6"; +#IOBUF PORT "JTAG_TDO" IO_TYPE=LVTTL33 PULLMODE=DOWN ; +#LOCATE COMP "JTAG_TDI" SITE "M5"; +#IOBUF PORT "JTAG_TDI" IO_TYPE=LVTTL33 PULLMODE=DOWN ; +#DEFINE PORT GROUP "jtag_grp" "JTAG*" ; +# IOBUF GROUP "jtag_grp" IO_TYPE=LVTTL33 PULLMODE=UP ; ################################################################# #Optical Link Status diff --git a/pinout/mdchub_fpga1234.lpf b/pinout/mdchub_fpga1234.lpf index e95469e..570ee05 100644 --- a/pinout/mdchub_fpga1234.lpf +++ b/pinout/mdchub_fpga1234.lpf @@ -24,25 +24,25 @@ ##################################################################### # Test connector ##################################################################### -# LOCATE COMP "TEST_LINE_0" SITE "F7"; -# LOCATE COMP "TEST_LINE_1" SITE "D8"; -# LOCATE COMP "TEST_LINE_2" SITE "J13"; -# LOCATE COMP "TEST_LINE_3" SITE "G11"; -# LOCATE COMP "TEST_LINE_4" SITE "H13"; -# LOCATE COMP "TEST_LINE_5" SITE "H12"; -# LOCATE COMP "TEST_LINE_6" SITE "E8"; -# LOCATE COMP "TEST_LINE_7" SITE "D9"; -# LOCATE COMP "TEST_LINE_8" SITE "D12"; -# LOCATE COMP "TEST_LINE_9" SITE "E13"; -# LOCATE COMP "TEST_LINE_10" SITE "J12"; -# LOCATE COMP "TEST_LINE_11" SITE "H10"; -# LOCATE COMP "TEST_LINE_12" SITE "E12"; -# LOCATE COMP "TEST_LINE_13" SITE "D11"; -# LOCATE COMP "TEST_LINE_14" SITE "H11"; -# LOCATE COMP "TEST_LINE_15" SITE "F11"; -# -# DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; -# IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; + LOCATE COMP "TEST_LINE_0" SITE "F7"; + LOCATE COMP "TEST_LINE_1" SITE "D8"; + LOCATE COMP "TEST_LINE_2" SITE "J13"; + LOCATE COMP "TEST_LINE_3" SITE "G11"; + LOCATE COMP "TEST_LINE_4" SITE "H13"; + LOCATE COMP "TEST_LINE_5" SITE "H12"; + LOCATE COMP "TEST_LINE_6" SITE "E8"; + LOCATE COMP "TEST_LINE_7" SITE "D9"; + LOCATE COMP "TEST_LINE_8" SITE "D12"; + LOCATE COMP "TEST_LINE_9" SITE "E13"; + LOCATE COMP "TEST_LINE_10" SITE "J12"; + LOCATE COMP "TEST_LINE_11" SITE "H10"; + LOCATE COMP "TEST_LINE_12" SITE "E12"; + LOCATE COMP "TEST_LINE_13" SITE "D11"; + LOCATE COMP "TEST_LINE_14" SITE "H11"; + LOCATE COMP "TEST_LINE_15" SITE "F11"; + + DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; + IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; ##################################################################### diff --git a/special/trb_net_bridge_pcie_endpoint_hub.vhd b/special/trb_net_bridge_pcie_endpoint_hub.vhd index 715f023..2e1116f 100644 --- a/special/trb_net_bridge_pcie_endpoint_hub.vhd +++ b/special/trb_net_bridge_pcie_endpoint_hub.vhd @@ -766,13 +766,13 @@ THE_DMA_CORE : dma_core end generate; SEND_RESET_OUT <= not send_reset_counter(10); - MAKE_RESET_OUT <= and_all(std_logic_vector(send_reset_counter(9 downto 0))); + MAKE_RESET_OUT <= '1' when and_all(std_logic_vector(send_reset_counter(9 downto 0))) = '1' or (BUS_ADDR_IN = x"00000011" and bus_write_i = '1') else '0'; process(CLK) begin if rising_edge(CLK) then if RESET = '1' then - send_reset_counter <= (others => '1'); + send_reset_counter <= "10000000000"; elsif BUS_ADDR_IN = x"00000010" and bus_write_i = '1' and BUS_WDAT_IN(15) = '1' then send_reset_counter <= (others => '0'); elsif send_reset_counter(10) = '0' then diff --git a/testbenches/hub_tb.vhd b/testbenches/hub_tb.vhd index 23391c7..277fb12 100644 --- a/testbenches/hub_tb.vhd +++ b/testbenches/hub_tb.vhd @@ -47,7 +47,8 @@ component trb_net16_hub_base is -- settings for external api connections INT_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0; INT_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3); - INT_IBUF_DEPTH : hub_api_config_t := (6,6,6,6,6,6,6,6) + INT_IBUF_DEPTH : hub_api_config_t := (6,6,6,6,6,6,6,6); + RESET_IOBUF_AT_TIMEOUT : integer range 0 to 1 := c_NO ); port ( CLK : in std_logic; @@ -337,14 +338,19 @@ end component; constant POINT_NUMBER : integer := 4; type cmd_arr is array (0 to 3) of std_logic_vector(15 downto 0); type num_arr is array (0 to 4) of std_logic_vector(2 downto 0); -constant initcommands : cmd_arr := (x"0080",x"0000",x"affe",x"dead"); - +constant initcommands : cmd_arr := (x"0000",x"8100",x"0000",x"0000"); + signal blocked : std_logic := '0'; signal ms_tick : std_logic := '0'; signal us_tick : std_logic := '0'; signal CLK : std_logic := '1'; signal RESET : std_logic := '1'; + signal bMED_DATAREADY_IN : std_logic_vector (POINT_NUMBER-1 downto 0); + signal bMED_DATA_IN : std_logic_vector (16*POINT_NUMBER-1 downto 0); + signal bMED_PACKET_NUM_IN : std_logic_vector (3*POINT_NUMBER-1 downto 0); + + signal MED_DATAREADY_IN : std_logic_vector (POINT_NUMBER-1 downto 0); signal MED_DATA_IN : std_logic_vector (16*POINT_NUMBER-1 downto 0); signal MED_PACKET_NUM_IN : std_logic_vector (3*POINT_NUMBER-1 downto 0); @@ -361,7 +367,9 @@ constant initcommands : cmd_arr := (x"0080",x"0000",x"affe",x"dead"); signal apl_dataready_i : std_logic_vector(3 downto 0); signal apl_read_i : std_logic_vector(3 downto 0); signal apl_send_i : std_logic_vector(3 downto 0); - + signal apl_run_out_i : std_logic_vector(3 downto 0); + + signal regio_read : std_logic_vector(3 downto 0); begin CLK <= not CLK after 5 ns; @@ -374,6 +382,10 @@ begin apl_send_i <= (others => '0'); wait for 1 us; + if apl_run_out_i(3) = '1' then + wait until apl_run_out_i(3) = '0'; + end if; + wait for 5 us; wait until rising_edge(CLK); wait for 1 ns; send_cmd : for i in 0 to initcommands'length-1 loop apl_dataready_i(3) <= '1'; @@ -384,7 +396,6 @@ begin apl_send_i(3) <= '1'; wait until rising_edge(CLK); wait for 1 ns; apl_send_i(3) <= '0'; - wait for 5 us; end process; @@ -413,13 +424,13 @@ begin APL_DTYPE_IN => x"8000", APL_ERROR_PATTERN_IN => (others => '0'), APL_SEND_IN => apl_send_i, - APL_TARGET_ADDRESS_IN => (others => '1'), --x"f001f001f001f001", + APL_TARGET_ADDRESS_IN => x"f401f001f001f001",--(others => '1'), --x"f001f001f001f001", APL_DATA_OUT => open, APL_PACKET_NUM_OUT => open, APL_TYP_OUT => open, APL_DATAREADY_OUT => open, APL_READ_IN => (others => '1'), - APL_RUN_OUT => open, + APL_RUN_OUT => apl_run_out_i, APL_MY_ADDRESS_IN => x"F00A", APL_SEQNR_OUT => open, APL_LENGTH_IN => (others => '0'), @@ -431,7 +442,14 @@ begin THE_HUB : trb_net16_hub_base generic map( - MII_NUMBER => POINT_NUMBER + MII_NUMBER => POINT_NUMBER, + RESET_IOBUF_AT_TIMEOUT => c_YES, + CLOCK_FREQUENCY => 3, + INIT_CTRL_REGS => + x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_003e1000_00000000" & + x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" ) port map( CLK => CLK, @@ -447,7 +465,7 @@ begin MED_DATA_IN => MED_DATA_IN, MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, MED_READ_OUT => MED_READ_OUT, - MED_STAT_OP => (others => '0'), + MED_STAT_OP => MED_STAT_OP,--(others => '0'), MED_CTRL_OP => MED_CTRL_OP, --INT: interfaces to connect APIs INT_INIT_DATAREADY_OUT => open, @@ -505,15 +523,16 @@ begin THE_ENDP_0 : trb_net16_endpoint_hades_full generic map( REGIO_INIT_ADDRESS => x"F000", + BROADCAST_BITMASK => x"00", REGIO_NUM_STAT_REGS => 1 ) port map( CLK => CLK, RESET => RESET, CLK_EN => '1', - MED_DATAREADY_OUT => MED_DATAREADY_IN(0), - MED_DATA_OUT => MED_DATA_IN(15 downto 0), - MED_PACKET_NUM_OUT => MED_PACKET_NUM_IN(2 downto 0), + MED_DATAREADY_OUT => bMED_DATAREADY_IN(0), + MED_DATA_OUT => bMED_DATA_IN(15 downto 0), + MED_PACKET_NUM_OUT => bMED_PACKET_NUM_IN(2 downto 0), MED_READ_IN => MED_READ_OUT(0), MED_DATAREADY_IN => MED_DATAREADY_OUT(0), MED_DATA_IN => MED_DATA_OUT(15 downto 0), @@ -558,11 +577,11 @@ THE_ENDP_0 : trb_net16_endpoint_hades_full STAT_REG_STROBE => open, CTRL_REG_STROBE => open, REGIO_ADDR_OUT => open, - REGIO_READ_ENABLE_OUT => open, + REGIO_READ_ENABLE_OUT => regio_read(0), REGIO_WRITE_ENABLE_OUT => open, REGIO_DATA_OUT => open, REGIO_DATA_IN => (others => '0'), - REGIO_DATAREADY_IN => '0', + REGIO_DATAREADY_IN => regio_read(0), REGIO_NO_MORE_DATA_IN => '0', REGIO_WRITE_ACK_IN => '0', REGIO_UNKNOWN_ADDR_IN => '0', @@ -594,15 +613,16 @@ THE_ENDP_0 : trb_net16_endpoint_hades_full THE_ENDP_2 : trb_net16_endpoint_hades_full generic map( REGIO_NUM_STAT_REGS => 1, + BROADCAST_BITMASK => x"00", REGIO_INIT_ADDRESS => x"F002" ) port map( CLK => CLK, RESET => RESET, CLK_EN => '1', - MED_DATAREADY_OUT => MED_DATAREADY_IN(2), - MED_DATA_OUT => MED_DATA_IN(47 downto 32), - MED_PACKET_NUM_OUT => MED_PACKET_NUM_IN(8 downto 6), + MED_DATAREADY_OUT => bMED_DATAREADY_IN(2), + MED_DATA_OUT => bMED_DATA_IN(47 downto 32), + MED_PACKET_NUM_OUT => bMED_PACKET_NUM_IN(8 downto 6), MED_READ_IN => MED_READ_OUT(2), MED_DATAREADY_IN => MED_DATAREADY_OUT(2), MED_DATA_IN => MED_DATA_OUT(47 downto 32), @@ -647,11 +667,11 @@ THE_ENDP_2 : trb_net16_endpoint_hades_full STAT_REG_STROBE => open, CTRL_REG_STROBE => open, REGIO_ADDR_OUT => open, - REGIO_READ_ENABLE_OUT => open, + REGIO_READ_ENABLE_OUT => regio_read(2), REGIO_WRITE_ENABLE_OUT => open, REGIO_DATA_OUT => open, REGIO_DATA_IN => (others => '0'), - REGIO_DATAREADY_IN => '0', + REGIO_DATAREADY_IN => regio_read(2), REGIO_NO_MORE_DATA_IN => '0', REGIO_WRITE_ACK_IN => '0', REGIO_UNKNOWN_ADDR_IN => '0', @@ -684,15 +704,16 @@ THE_ENDP_2 : trb_net16_endpoint_hades_full THE_ENDP_3 : trb_net16_endpoint_hades_full generic map( REGIO_NUM_STAT_REGS => 1, + BROADCAST_BITMASK => x"00", REGIO_INIT_ADDRESS => x"F003" ) port map( CLK => CLK, RESET => RESET, CLK_EN => '1', - MED_DATAREADY_OUT => MED_DATAREADY_IN(3), - MED_DATA_OUT => MED_DATA_IN(63 downto 48), - MED_PACKET_NUM_OUT => MED_PACKET_NUM_IN(11 downto 9), + MED_DATAREADY_OUT => bMED_DATAREADY_IN(3), + MED_DATA_OUT => bMED_DATA_IN(63 downto 48), + MED_PACKET_NUM_OUT => bMED_PACKET_NUM_IN(11 downto 9), MED_READ_IN => MED_READ_OUT(3), MED_DATAREADY_IN => MED_DATAREADY_OUT(3), MED_DATA_IN => MED_DATA_OUT(63 downto 48), @@ -737,11 +758,11 @@ THE_ENDP_3 : trb_net16_endpoint_hades_full STAT_REG_STROBE => open, CTRL_REG_STROBE => open, REGIO_ADDR_OUT => open, - REGIO_READ_ENABLE_OUT => open, + REGIO_READ_ENABLE_OUT => regio_read(3), REGIO_WRITE_ENABLE_OUT => open, REGIO_DATA_OUT => open, REGIO_DATA_IN => (others => '0'), - REGIO_DATAREADY_IN => '0', + REGIO_DATAREADY_IN => regio_read(3), REGIO_NO_MORE_DATA_IN => '0', REGIO_WRITE_ACK_IN => '0', REGIO_UNKNOWN_ADDR_IN => '0', @@ -770,4 +791,23 @@ THE_ENDP_3 : trb_net16_endpoint_hades_full DEBUG_LVL1_HANDLER_OUT => open ); -end architecture; \ No newline at end of file +MED_DATAREADY_IN(3) <= transport bMED_DATAREADY_IN(3) after 499 ns; +MED_DATA_IN(63 downto 48)<= transport bMED_DATA_IN(63 downto 48) after 499 ns; +MED_PACKET_NUM_IN(11 downto 9) <= transport bMED_PACKET_NUM_IN(11 downto 9) after 499 ns; + +MED_DATAREADY_IN(2) <= transport bMED_DATAREADY_IN(2) after 499 ns; +MED_DATA_IN(47 downto 32)<= transport bMED_DATA_IN(47 downto 32) after 499 ns; +MED_PACKET_NUM_IN(8 downto 6) <= transport bMED_PACKET_NUM_IN(8 downto 6) after 499 ns; + +blocked <= '0', '1' after 12200 ns, '0' after 1014000 ns; +MED_DATAREADY_IN(0) <= transport bMED_DATAREADY_IN(0) and not blocked after 799 ns; +MED_DATA_IN(15 downto 0)<= transport bMED_DATA_IN(15 downto 0) after 799 ns; +MED_PACKET_NUM_IN(2 downto 0) <= transport bMED_PACKET_NUM_IN(2 downto 0) after 799 ns; + +MED_STAT_OP <= x"0000000000000000"; --, x"0000000000004003" after 13000 ns, + --x"0000000000000003" after 89600 ns, + --x"0000000000000000" after 102200 ns; + +end architecture; + + diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 65e5705..0ec1733 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -44,7 +44,8 @@ entity trb_net16_hub_base is -- settings for external api connections INT_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0; INT_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3); - INT_IBUF_DEPTH : hub_api_config_t := (6,6,6,6,6,6,6,6) + INT_IBUF_DEPTH : hub_api_config_t := (6,6,6,6,6,6,6,6); + RESET_IOBUF_AT_TIMEOUT : integer range 0 to 1 := c_NO ); port ( CLK : in std_logic; @@ -207,6 +208,7 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal buf_HC_STAT_REGS : std_logic_vector (64*32-1 downto 0); signal HC_STAT_ack_waiting : std_logic_vector(127 downto 0) := (others => '0'); signal HUB_CTRL_LOCAL_NETWORK_RESET : std_logic_vector(MII_NUMBER-1 downto 0); + signal ctrl_local_net_reset_changed : std_logic_vector(3 downto 0); signal HUB_MED_CONNECTED : std_logic_vector (31 downto 0); signal HUB_CTRL_final_activepoints : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0); @@ -225,7 +227,7 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal resync : std_logic_vector(MII_NUMBER-1 downto 0); signal reset_i : std_logic; - signal reset_i_mux_io : std_logic_vector(MII_NUMBER-1 downto 0); + signal reset_i_mux_io : std_logic_vector((MII_NUMBER*2**(c_MUX_WIDTH-1))-1 downto 0); signal combined_resync : std_logic; @@ -255,6 +257,7 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal DAT_TIMEOUT_OUT : std_logic; signal STAT_TIMEOUT : std_logic_vector(4*32-1 downto 0); + signal last_STAT_TIMEOUT : std_logic_vector(4*32-1 downto 0); signal local_network_reset : std_logic_vector(MII_NUMBER-1 downto 0); signal local_reset_med : std_logic_vector(MII_NUMBER-1 downto 0); @@ -305,13 +308,15 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is type tv_t is array (2**(c_MUX_WIDTH-1)-1 downto 0) of std_logic_vector(15 downto 0); signal current_timeout_value : tv_t := (others => (others => '0')); - signal hub_level : std_logic_vector(3 downto 0); + signal hub_level : std_logic_vector(7 downto 0); type cnt_t is array (MII_NUMBER-1 downto 0) of unsigned(31 downto 0); signal busy_counter_excl : cnt_t := (others => (others => '0')); signal busy_counter_incl : cnt_t := (others => (others => '0')); signal reg_STAT_POINTS_locked : std_logic_vector(MII_NUMBER-1 downto 0); signal reg_excl_enable : std_logic_vector(MII_NUMBER-1 downto 0); + signal delay1_media_reset_me : std_logic_vector(MII_NUMBER-1 downto 0); + signal delay2_media_reset_me : std_logic_vector(MII_NUMBER-1 downto 0); signal mii_error : std_logic_vector(31 downto 0); @@ -330,6 +335,7 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal last_lsm_read : std_logic; signal next_last_lsm_read : std_logic; + signal hub_ctrl_disabled_ports : std_logic_vector(31 downto 0); signal buf_HUB_MISMATCH_PATTERN : std_logic_vector(31 downto 0); type counter8b_t is array (0 to 15) of unsigned(7 downto 0); @@ -375,20 +381,47 @@ begin begin if rising_edge(CLK) then reset_i <= RESET; + last_STAT_TIMEOUT <= STAT_TIMEOUT; end if; end process; +-- STAT_TIMEOUT - - gen_internal_reset : for i in 0 to MII_NUMBER-1 generate - SYNC_RESET_MUX_IO : process(CLK) - begin - if rising_edge(CLK) then - reset_i_mux_io(i) <= MED_STAT_OP(i*16+14) or RESET; - end if; - end process; + gen_iobuf_noreset : if RESET_IOBUF_AT_TIMEOUT = c_NO generate + gen_internal_reset : for i in 0 to MII_NUMBER-1 generate + gen_int_reset_2 : for j in 0 to 2**(c_MUX_WIDTH-1)-1 generate + SYNC_RESET_MUX_IO : process(CLK) + begin + if rising_edge(CLK) then + reset_i_mux_io(i+j*MII_NUMBER) <= MED_STAT_OP(i*16+14) or RESET; + end if; + end process; + end generate; + end generate; + end generate; + + gen_iobuf_reset : if RESET_IOBUF_AT_TIMEOUT = c_YES generate + gen_int_reset_3 : for i in 0 to MII_NUMBER-1 generate + gen_int_reset_4 : for j in 0 to 2**(c_MUX_WIDTH-1)-1 generate + SYNC_RESET_MUX_IO : process begin + wait until rising_edge(CLK); + if j /= 2 then + if HUB_locked(j) = '1' then + reset_i_mux_io(i+j*MII_NUMBER) <= RESET or (STAT_TIMEOUT(j*32+i) and not last_STAT_TIMEOUT(j*32+i)) + or reset_i_mux_io(i+j*MII_NUMBER) or delay2_media_reset_me(i); + else + reset_i_mux_io(i+j*MII_NUMBER) <= MED_STAT_OP(i*16+14) or RESET; + end if; + else + reset_i_mux_io(i+j*MII_NUMBER) <= (MED_STAT_OP(i*16+14) and (not or_all(HUB_locked) or reset_i_mux_io(i+j*MII_NUMBER))) + or RESET; + end if; + end process; + end generate; + end generate; end generate; + --generate media resync gen_resync : for i in 0 to MII_NUMBER-1 generate resync(i) <= MED_STAT_OP(i*16+15) when MII_IS_UPLINK(i) = c_YES else '0'; @@ -413,26 +446,47 @@ begin gen_local_network_reset : process(CLK) begin if rising_edge(CLK) then - if CTRL_REG_STROBE(6) = '1' then + if reset_i = '1' then + local_network_reset <= (others => '0'); + local_reset_med <= (others => '0'); + network_reset_counter <= (others => '0'); + elsif ctrl_local_net_reset_changed(3) = '1' then local_network_reset <= HUB_CTRL_LOCAL_NETWORK_RESET; local_reset_med <= (others => '0'); network_reset_counter <= x"001"; - end if; - if network_reset_counter(10) = '1' then + + elsif network_reset_counter(10) = '1' then network_reset_counter <= (others => '0'); local_network_reset <= (others => '0'); local_reset_med <= (others => '0'); elsif and_all(network_reset_counter(9 downto 0)) = '1' then local_reset_med <= local_network_reset; - elsif network_reset_counter /= 0 then - network_reset_counter <= network_reset_counter + 1; - else local_network_reset <= (others => '0'); - local_reset_med <= (others => '0'); end if; + if network_reset_counter(9 downto 0) /= 0 then + network_reset_counter <= network_reset_counter + 1; + end if; + end if; + end process; + + gen_delayed_link_off : for i in 0 to MII_NUMBER-1 generate + process begin + wait until rising_edge(CLK); + if timer_us_tick = '1' then + delay1_media_reset_me(i) <= MED_STAT_OP(i*16+14); + delay2_media_reset_me(i) <= delay1_media_reset_me(i); end if; end process; + end generate; + gen_local_net_reset_ctrl_reg : process begin + wait until rising_edge(CLK); + ctrl_local_net_reset_changed(0) <= (CTRL_REG_STROBE(6) or ctrl_local_net_reset_changed(0)) + and not ctrl_local_net_reset_changed(1); + if timer_us_tick = '1' then + ctrl_local_net_reset_changed(3 downto 1) <= ctrl_local_net_reset_changed(2 downto 0); + end if; + end process; --------------------------------------------------------------------- --Multiplexer @@ -450,7 +504,7 @@ begin ) port map ( CLK => CLK, - RESET => reset_i_mux_io(i), + RESET => reset_i_mux_io(i+2*MII_NUMBER), --use reset from ch.2 here (not influenced by timeouts) CLK_EN => CLK_EN, MED_DATAREADY_IN => MED_DATAREADY_IN(i), MED_DATA_IN => MED_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), @@ -504,7 +558,7 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; port map ( -- Misc CLK => CLK , - RESET => reset_i_mux_io(j), + RESET => reset_i_mux_io(j+k*MII_NUMBER), CLK_EN => CLK_EN, -- Media direction port MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), @@ -543,8 +597,8 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; STAT_IBUF_BUFFER => IOBUF_IBUF_BUFFER((i+1)*32-1 downto i*32), STAT_DATA_COUNTER => IOBUF_STAT_DATA_COUNTER((i+1)*32-1 downto i*32), CTRL_GEN => IOBUF_CTRL_GEN((i+1)*32-1 downto i*32), - CTRL_OBUF_settings(15 downto 0) => current_timeout_value(k),--HUB_CTRL_TIMEOUT_TIME(k*4+19 downto k*4+16), - CTRL_OBUF_settings(31 downto 16) => current_timeout_value(k),--HUB_CTRL_TIMEOUT_TIME(k*4+19 downto k*4+16), + CTRL_OBUF_settings(15 downto 0) => (others => '0'), -- current_timeout_value(k),--HUB_CTRL_TIMEOUT_TIME(k*4+19 downto k*4+16), + CTRL_OBUF_settings(31 downto 16) => (others => '0'), -- current_timeout_value(k),--HUB_CTRL_TIMEOUT_TIME(k*4+19 downto k*4+16), STAT_INIT_OBUF_DEBUG => iobuf_stat_init_obuf_debug_i((i+1)*32-1 downto i*32), STAT_REPLY_OBUF_DEBUG => iobuf_stat_reply_obuf_debug_i((i+1)*32-1 downto i*32), TIMER_TICKS_IN(0) => timer_us_tick, @@ -901,6 +955,7 @@ end generate; STAT_ALL_ERRORBITS => buf_HUB_ALL_ERROR_BITS((i+1)*32*16-1 downto i*32*16), CTRL_TIMEOUT_TIME => current_timeout_value(i),--HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4), CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32), + CTRL_DISABLED_PORTS => hub_ctrl_disabled_ports, CTRL_TIMER_TICK(0) => timer_us_tick, CTRL_TIMER_TICK(1) => timer_ms_tick ); @@ -942,6 +997,7 @@ end generate; STAT_MISMATCH => buf_HUB_MISMATCH_PATTERN(31 downto 0), CTRL_TIMEOUT_TIME => current_timeout_value(i),--HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4), CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32), + CTRL_DISABLED_PORTS => hub_ctrl_disabled_ports, CTRL_TIMER_TICK(0) => timer_us_tick, CTRL_TIMER_TICK(1) => timer_ms_tick ); @@ -1297,22 +1353,18 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); --Timeouts 88-8B if reg_STROBES(8) = '1' then HC_STAT_REGS(8*32+31 downto 8*32) <= (others => '0'); - elsif combined_resync = '0' and reset_i = '0' and timer_ms_tick = '1' then + elsif combined_resync = '0' and reset_i = '0' and timer_us_tick = '1' then HC_STAT_REGS(8*32+31 downto 8*32) <= STAT_TIMEOUT(0*32+31 downto 0*32) or HC_STAT_REGS(8*32+31 downto 8*32); end if; if reg_STROBES(9) = '1' then HC_STAT_REGS(9*32+31 downto 9*32) <= (others => '0'); - elsif combined_resync = '0' and reset_i = '0' and timer_ms_tick = '1' then + elsif combined_resync = '0' and reset_i = '0' and timer_us_tick = '1' then HC_STAT_REGS(9*32+31 downto 9*32) <= STAT_TIMEOUT(1*32+31 downto 1*32) or HC_STAT_REGS(9*32+31 downto 9*32); end if; --- if reg_STROBES(10) = '1' then - HC_STAT_REGS(10*32+31 downto 10*32) <= (others => '0'); --- elsif combined_resync = '0' and reset_i = '0' and timer_ms_tick = '1' then --- HC_STAT_REGS(10*32+31 downto 10*32) <= STAT_TIMEOUT(2*32+31 downto 2*32) or HC_STAT_REGS(10*32+31 downto 10*32); --- end if; + HC_STAT_REGS(10*32+31 downto 10*32) <= (others => '0'); if reg_STROBES(11) = '1' then HC_STAT_REGS(11*32+31 downto 11*32) <= (others => '0'); - elsif combined_resync = '0' and reset_i = '0' and timer_ms_tick = '1' then + elsif combined_resync = '0' and reset_i = '0' and timer_us_tick = '1' then HC_STAT_REGS(11*32+31 downto 11*32) <= STAT_TIMEOUT(3*32+31 downto 3*32) or HC_STAT_REGS(11*32+31 downto 11*32); end if; @@ -1569,23 +1621,33 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); HUB_CTRL_activepoints(i*32+MII_NUMBER+1) <= HC_CTRL_REGS(i*32+MII_NUMBER+1) and stream_port_connected; end if; else - HUB_CTRL_activepoints(i*32+31 downto i*32) <= HUB_CTRL_activepoints(i*32+31 downto i*32) and not HC_STAT_ack_waiting(i*32+31 downto i*32); + HUB_CTRL_activepoints(i*32+31 downto i*32) <= HUB_CTRL_activepoints(i*32+31 downto i*32); -- and not HC_STAT_ack_waiting(i*32+31 downto i*32) if i < 2 and INT_NUMBER >= 3 then - HUB_CTRL_activepoints(i*32+MII_NUMBER) <= HUB_CTRL_activepoints(i*32+MII_NUMBER) and not HC_STAT_ack_waiting(i*32+MII_NUMBER) and stream_port_connected; + HUB_CTRL_activepoints(i*32+MII_NUMBER) <= HUB_CTRL_activepoints(i*32+MII_NUMBER) and stream_port_connected; -- and not HC_STAT_ack_waiting(i*32+31 downto i*32) else - HUB_CTRL_activepoints(i*32+MII_NUMBER+1) <= HUB_CTRL_activepoints(i*32+MII_NUMBER+1) and not HC_STAT_ack_waiting(i*32+MII_NUMBER+1) and stream_port_connected; + HUB_CTRL_activepoints(i*32+MII_NUMBER+1) <= HUB_CTRL_activepoints(i*32+MII_NUMBER+1) and stream_port_connected; -- and not HC_STAT_ack_waiting(i*32+31 downto i*32) end if; end if; end loop; end if; end process; + PROC_ports_disable_after_timeout: process begin + wait until rising_edge(CLK); + if HUB_CTRL_TIMEOUT_TIME(31) = '0' or reset_i = '1' then + hub_ctrl_disabled_ports <= not HUB_MED_CONNECTED; --(others => '0'); + else + hub_ctrl_disabled_ports(31 downto MII_NUMBER) <= (others => '0'); + hub_ctrl_disabled_ports(MII_NUMBER-1 downto 0) <= STAT_TIMEOUT(3*32+MII_NUMBER-1+16 downto 3*32+16) or not HUB_MED_CONNECTED(MII_NUMBER-1 downto 0); + end if; + end process; + PROC_timeout_settings : process (CLK) begin if rising_edge(CLK) then -- if CTRL_REG_STROBE(5) = '1' then HUB_CTRL_TIMEOUT_TIME <= HC_CTRL_REGS(5*32+31 downto 5*32); - hub_level <= HC_CTRL_REGS(5*32+19 downto 5*32+16); + hub_level <= HC_CTRL_REGS(5*32+23 downto 5*32+16); -- end if; end if; end process; @@ -1649,8 +1711,24 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); --------------------------------------------------------------------- --Debugging Signals --------------------------------------------------------------------- - - buf_STAT_DEBUG(31 downto 0) <= (others => '0'); +-- buf_STAT_DEBUG(0) <= hub_to_buf_INIT_DATAREADY(2**(c_MUX_WIDTH-1)*MII_NUMBER); +-- buf_STAT_DEBUG(1) <= hub_to_buf_INIT_READ(2**(c_MUX_WIDTH-1)*MII_NUMBER); +-- buf_STAT_DEBUG(2) <= hub_to_buf_REPLY_DATAREADY(2**(c_MUX_WIDTH-1)*MII_NUMBER); +-- buf_STAT_DEBUG(3) <= hub_to_buf_REPLY_READ(2**(c_MUX_WIDTH-1)*MII_NUMBER); +-- buf_STAT_DEBUG(6 downto 4) <= hub_to_buf_INIT_DATA(2**(c_MUX_WIDTH-1)*MII_NUMBER*16+2 downto 2**(c_MUX_WIDTH-1)*MII_NUMBER*16); +-- buf_STAT_DEBUG(7) <= buf_HUB_STAT_CHANNEL(3*16+1); +-- +-- buf_STAT_DEBUG(8) <= reset_i_mux_io(2*MII_NUMBER+6); +-- buf_STAT_DEBUG(9) <= reset_i_mux_io(3*MII_NUMBER+6); +-- buf_STAT_DEBUG(10) <= HUB_CTRL_final_activepoints(3*32+6); +-- buf_STAT_DEBUG(11) <= STAT_TIMEOUT(3*32+6); +-- buf_STAT_DEBUG(12) <= buf_to_hub_REPLY_DATAREADY(6*4+3); +-- buf_STAT_DEBUG(13) <= buf_to_hub_REPLY_READ(6*4+3); +-- buf_STAT_DEBUG(14) <= buf_HUB_STAT_CHANNEL(3*16+2); +-- +-- buf_STAT_DEBUG(15) <= buf_to_hub_INIT_DATAREADY(0*4+3); + + buf_STAT_DEBUG(31 downto 16) <= (others => '0'); IOBUF_STAT_INIT_OBUF_DEBUG <= iobuf_stat_init_obuf_debug_i; diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index e27b99f..b4b9903 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -117,7 +117,8 @@ package trb_net16_hub_func is -- settings for external api connections INT_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0; INT_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3); - INT_IBUF_DEPTH : hub_api_config_t := (6,6,6,6,6,6,6,6) + INT_IBUF_DEPTH : hub_api_config_t := (6,6,6,6,6,6,6,6); + RESET_IOBUF_AT_TIMEOUT : integer range 0 to 1 := c_NO ); port ( CLK : in std_logic; @@ -330,6 +331,7 @@ component trb_net16_hub_streaming_port is STAT_MISMATCH : out std_logic_vector (31 downto 0); CTRL_TIMEOUT_TIME : in std_logic_vector (15 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1'); + CTRL_DISABLED_PORTS : in std_logic_vector (31 downto 0) := (others => '0'); CTRL_TIMER_TICK : in std_logic_vector (1 downto 0) ); end component; @@ -370,6 +372,7 @@ component trb_net16_hub_streaming_port is STAT_ALL_ERRORBITS : out std_logic_vector (16*32-1 downto 0); CTRL_TIMEOUT_TIME : in std_logic_vector (15 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0); + CTRL_DISABLED_PORTS : in std_logic_vector (31 downto 0) := (others => '0'); CTRL_TIMER_TICK : in std_logic_vector (1 downto 0) ); end component; diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd index 716f8dd..bd8ae97 100644 --- a/trb_net16_hub_ipu_logic.vhd +++ b/trb_net16_hub_ipu_logic.vhd @@ -50,6 +50,7 @@ entity trb_net16_hub_ipu_logic is STAT_MISMATCH : out std_logic_vector (31 downto 0); CTRL_TIMEOUT_TIME : in std_logic_vector (15 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1'); + CTRL_DISABLED_PORTS : in std_logic_vector (31 downto 0) := (others => '0'); CTRL_TIMER_TICK : in std_logic_vector (1 downto 0) ); end entity; @@ -770,9 +771,10 @@ begin begin if rising_edge(CLK) then if locked = '0' then - real_activepoints <= CTRL_activepoints(POINT_NUMBER-1 downto 0); + real_activepoints <= CTRL_activepoints(POINT_NUMBER-1 downto 0) and not CTRL_DISABLED_PORTS(POINT_NUMBER-1 downto 0); else - real_activepoints <= real_activepoints and CTRL_activepoints(POINT_NUMBER-1 downto 0) and not connection_timed_out; + real_activepoints <= real_activepoints and CTRL_activepoints(POINT_NUMBER-1 downto 0) + and not connection_timed_out and not CTRL_DISABLED_PORTS(POINT_NUMBER-1 downto 0); end if; end if; end process; diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index e9ff6c9..272e57e 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -43,6 +43,7 @@ entity trb_net16_hub_logic is STAT_ALL_ERRORBITS : out std_logic_vector (16*32-1 downto 0); CTRL_TIMEOUT_TIME : in std_logic_vector (15 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1'); + CTRL_DISABLED_PORTS: in std_logic_vector (31 downto 0) := (others => '0'); CTRL_TIMER_TICK : in std_logic_vector (1 downto 0) ); end entity; diff --git a/trb_net16_hub_logic_2.vhd b/trb_net16_hub_logic_2.vhd index 736a8a4..ef19f50 100644 --- a/trb_net16_hub_logic_2.vhd +++ b/trb_net16_hub_logic_2.vhd @@ -6,6 +6,7 @@ library work; use work.trb_net_std.all; use work.trb_net_components.all; use work.trb_net16_hub_func.all; +use work.lattice_ecp2m_fifo.all; entity trb_net16_hub_logic is generic ( @@ -43,6 +44,7 @@ entity trb_net16_hub_logic is STAT_ALL_ERRORBITS : out std_logic_vector (16*32-1 downto 0); CTRL_TIMEOUT_TIME : in std_logic_vector (15 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1'); + CTRL_DISABLED_PORTS: in std_logic_vector (31 downto 0) := (others => '0'); CTRL_TIMER_TICK : in std_logic_vector (1 downto 0) ); end entity; @@ -99,10 +101,13 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal init_pool_dataready_out : std_logic; signal init_read_out_i : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); signal init_has_read_from_pool : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + signal init_pool_full : std_logic; + signal init_pool_empty : std_logic; --Reply Pool signal reply_selected_dataready : std_logic; + signal reply_selected_read : std_logic; signal reply_selected_data : std_logic_vector(15 downto 0) := (others => '0'); signal reply_selected_packet_num : std_logic_vector(2 downto 0) := (others => '0'); signal reply_pool_reading : std_logic; @@ -114,6 +119,8 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal reply_pool_packet_num_out : std_logic_vector(2 downto 0) := (others => '0'); signal reply_pool_read_out : std_logic; signal reply_pool_dataready_out : std_logic; + signal reply_pool_full : std_logic; + signal reply_pool_empty : std_logic; --Control Signals signal real_active_points : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); @@ -132,8 +139,11 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal REPLY_combined_trm_F3 : std_logic_vector(15 downto 0); signal send_trm_cnt : integer; - + type arr4_t is array (0 to POINT_NUMBER-1) of unsigned(3 downto 0); + signal timeout_cntr : arr4_t; + signal timeout_disabled : std_logic; signal timeout_ports : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + signal timeout_ports_disable : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); attribute syn_keep of reset_i : signal is true; begin @@ -157,7 +167,7 @@ begin config_wait_free_init_pool <= x"00" & unsigned(CTRL_TIMEOUT_TIME) & x"00"; --mult. by 256/1024, e.q. 1/4 of given value config_wait_reply <= x"00" & "00" & unsigned(CTRL_TIMEOUT_TIME) & "000000"; --mult. by 64/1024, e.q. 1/16 of given value - + timeout_disabled <= not or_all(CTRL_TIMEOUT_TIME); ---------------------------------- --connect init input signals @@ -184,7 +194,7 @@ begin ); - reply_select_input <= REPLY_DATAREADY_IN and not reply_reading_trm and not TRM_packet; + reply_select_input <= REPLY_DATAREADY_IN and not reply_reading_trm and not TRM_packet and not reply_got_trm; THE_REPLY_SELECT : priority_arbiter generic map( @@ -203,6 +213,7 @@ begin ---------------------------------- --choose from all reply data the selected one + reply_selected_read <= reply_mux_read_out_i(act_reply_port); reply_selected_dataready <= REPLY_DATAREADY_IN(act_reply_port); reply_selected_data <= REPLY_DATA_IN(16*act_reply_port+15 downto 16*act_reply_port); reply_selected_packet_num <= REPLY_PACKET_NUM_IN(3*act_reply_port+2 downto 3*act_reply_port); @@ -225,9 +236,16 @@ begin ---------------------------------- --combine error pattern ---------------------------------- - - reply_reading_trm <= reply_reading_trm or TRM_packet when currentstate /= IDLE else (others => '0'); - reply_got_trm <= reply_got_trm or reading_trmF3 when currentstate /= IDLE else (others => '0'); + process begin + wait until rising_edge(CLK); + if currentstate = IDLE or currentstate = SELECT_INIT then + reply_reading_trm <= (others => '0'); + reply_got_trm <= not real_active_points; + else + reply_reading_trm <= reply_reading_trm or TRM_packet; + reply_got_trm <= reply_got_trm or reading_trmF3 or timeout_ports or CTRL_DISABLED_PORTS(POINT_NUMBER-1 downto 0); + end if; + end process; gen_reading_trmFn : for i in 0 to POINT_NUMBER-1 generate reading_trmF1(i) <= '1' when REPLY_PACKET_NUM_IN(i*3+2 downto i*3) = c_F1 @@ -280,20 +298,24 @@ begin init_pool_dataready_in <= '0'; reply_pool_dataready_in <= '0'; init_select_enable <= '0'; - timer_us_reset <= '0'; + timer_us_reset <= timeout_disabled; reply_open <= '0'; - + reply_pool_data_in <= (others => '0'); + reply_pool_packet_num_in <= (others => '0'); case currentstate is when IDLE => - real_active_points <= CTRL_activepoints(POINT_NUMBER-1 downto 0); --- reply_reading_trm <= (others => '0'); + real_active_points <= CTRL_activepoints(POINT_NUMBER-1 downto 0) + and not timeout_ports_disable + and not CTRL_DISABLED_PORTS(POINT_NUMBER-1 downto 0); + timer_us_reset <= '1'; if or_all(INIT_DATAREADY_IN and real_active_points) = '1' then currentstate <= SELECT_INIT; init_select_enable <= '1'; end if; when SELECT_INIT => + timeout_ports <= (others => '0'); currentstate <= FORWARD_INIT; init_current_type <= (others => '0'); @@ -310,23 +332,23 @@ begin currentstate <= SELECT_REPLY; end if; else - if timer_us = config_wait_free_init_pool then - timeout_ports <= timeout_ports or act_init_mask; - real_active_points <= real_active_points and not INIT_READ_IN; + if timer_us = config_wait_free_init_pool and timeout_disabled = '0' then + timeout_ports <= timeout_ports or (not init_has_read_from_pool);--INIT_READ_IN and not act_init_mask); + real_active_points <= real_active_points and init_has_read_from_pool; --(INIT_READ_IN or act_init_mask); end if; end if; when SELECT_REPLY => init_read_out_i <= (others => '0'); reply_select_enable <= '1'; - if or_all(REPLY_DATAREADY_IN and CTRL_activepoints(POINT_NUMBER-1 downto 0) and not reply_reading_trm) = '1' then + if or_all(REPLY_DATAREADY_IN and real_active_points and not reply_reading_trm and not TRM_packet) = '1' then timer_us_reset <= '1'; currentstate <= WAIT_FOR_SELECT; end if; - if timer_us = config_wait_reply then - timeout_ports <= timeout_ports or (not reply_reading_trm and not TRM_packet and real_active_points); + if timer_us = config_wait_reply and timeout_disabled = '0' then + timeout_ports <= timeout_ports or (not reply_got_trm and real_active_points and not act_init_mask); --not reply_reading_trm and ---TODO: add proper handling +--TODO: add proper handling - should be ok like it is? end if; if and_all(reply_got_trm or act_init_mask) = '1' then currentstate <= SEND_TRM; @@ -338,19 +360,20 @@ begin reply_open <= '1'; when FORWARD_REPLY => - if TRM_packet(act_reply_port) = '1' then + reply_pool_data_in <= reply_selected_data; + reply_pool_packet_num_in <= reply_selected_packet_num; + + if TRM_packet(act_reply_port) = '1' or reply_reading_trm(act_reply_port) = '1' then currentstate <= SELECT_REPLY; reply_pool_dataready_in <= '0'; - elsif timer_us = config_wait_reply then --assume alsways full packets due to error correction + elsif timer_us = config_wait_reply and timeout_disabled = '0' then --assume alsways full packets due to error correction real_active_points <= real_active_points and not act_reply_mask; timer_us_reset <= '1'; timeout_ports <= timeout_ports or act_reply_mask; currentstate <= SELECT_REPLY; else reply_open <= '1'; - reply_pool_data_in <= reply_selected_data; - reply_pool_packet_num_in <= reply_selected_packet_num; - reply_pool_dataready_in <= reply_selected_dataready; + reply_pool_dataready_in <= reply_selected_dataready and reply_selected_read; end if; if reply_selected_dataready = '1' then timer_us_reset <= '1'; @@ -394,37 +417,46 @@ begin when REPLY_TIMEOUT => null; end case; + if reset_i = '1' then + currentstate <= IDLE; + end if; end process; -reply_mux_read_out_i(act_reply_port) <= reply_pool_free and reply_open; + +process(reply_pool_free, reply_open,act_reply_port) + begin + reply_mux_read_out_i <= (others => '0'); + reply_mux_read_out_i(act_reply_port) <= reply_pool_free and reply_open; + end process; ---------------------------------- --SBuf for init output ---------------------------------- - INIT_POOL_SBUF: trb_net16_sbuf - generic map ( - Version => std_SBUF_VERSION - ) - port map ( - CLK => CLK, - RESET => reset_i, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => init_pool_dataready_in, - COMB_next_READ_OUT => init_pool_free, - COMB_READ_IN => '1', - COMB_DATA_IN => init_pool_data_in, - COMB_PACKET_NUM_IN => init_pool_packet_num_in, - SYN_DATAREADY_OUT => init_pool_dataready_out, - SYN_DATA_OUT => init_pool_data_out, - SYN_PACKET_NUM_OUT => init_pool_packet_num_out, - SYN_READ_IN => init_pool_read_out + + INIT_POOL_SBUF : fifo_19x16 + port map( + Data(15 downto 0) => init_pool_data_in, + Data(18 downto 16) => init_pool_packet_num_in, + Clock => CLK, + WrEn => init_pool_dataready_in, + RdEn => init_pool_read_out, + Reset => reset_i, + Q(15 downto 0) => init_pool_data_out, + Q(18 downto 16) => init_pool_packet_num_out, + WCNT => open, + Empty => init_pool_empty, + Full => open, + AlmostFull => init_pool_full ); - - init_pool_reading <= init_pool_free when rising_edge(CLK); - init_pool_read_out <= and_all(INIT_READ_IN or init_has_read_from_pool); + init_pool_free <= not init_pool_full when rising_edge(CLK); + init_pool_dataready_out <= (not init_pool_empty and init_pool_read_out) + or (init_pool_dataready_out and not init_pool_read_out) when rising_edge(CLK); + init_pool_read_out <= and_all(INIT_READ_IN or init_has_read_from_pool); + + --Which ports have read data from pool gen_hasread: for i in 0 to POINT_NUMBER-1 generate process(CLK) @@ -444,43 +476,61 @@ reply_mux_read_out_i(act_reply_port) <= reply_pool_free and reply_open; end generate; + ---------------------------------- --SBuf for reply output ---------------------------------- - REPLY_POOL_SBUF: trb_net16_sbuf - generic map ( - Version => std_SBUF_VERSION - ) - port map ( - CLK => CLK, - RESET => reset_i, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => reply_pool_dataready_in, - COMB_next_READ_OUT => reply_pool_free, - COMB_READ_IN => '1', - COMB_DATA_IN => reply_pool_data_in, - COMB_PACKET_NUM_IN => reply_pool_packet_num_in, - SYN_DATAREADY_OUT => reply_pool_dataready_out, - SYN_DATA_OUT => reply_pool_data_out, - SYN_PACKET_NUM_OUT => reply_pool_packet_num_out, - SYN_READ_IN => reply_pool_read_out + + REPLY_POOL_SBUF : fifo_19x16 + port map( + Data(15 downto 0) => reply_pool_data_in, + Data(18 downto 16) => reply_pool_packet_num_in, + Clock => CLK, + WrEn => reply_pool_dataready_in, + RdEn => reply_pool_read_out, + Reset => reset_i, + Q(15 downto 0) => reply_pool_data_out, + Q(18 downto 16) => reply_pool_packet_num_out, + WCNT => open, + Empty => reply_pool_empty, + Full => open, + AlmostFull => reply_pool_full ); - reply_pool_reading <= reply_pool_free when rising_edge(CLK); - reply_pool_read_out <= REPLY_READ_IN(act_init_port); + reply_pool_free <= not reply_pool_full when rising_edge(CLK); + reply_pool_dataready_out <= (not reply_pool_empty and reply_pool_read_out) + or (reply_pool_dataready_out and not reply_pool_read_out) when rising_edge(CLK); + + reply_pool_read_out <= REPLY_READ_IN(act_init_port); + ---------------------------------- --connect output signals ---------------------------------- gen_init_output : for i in 0 to POINT_NUMBER-1 generate INIT_DATA_OUT(16*i+15 downto 16*i) <= init_pool_data_out; INIT_PACKET_NUM_OUT(3*i+2 downto 3*i) <= init_pool_packet_num_out; - INIT_DATAREADY_OUT(i) <= init_pool_dataready_out and not init_has_read_from_pool(i); + INIT_DATAREADY_OUT(i) <= init_pool_dataready_out and not init_has_read_from_pool(i) and real_active_points(i); REPLY_DATA_OUT(16*i+15 downto 16*i) <= reply_pool_data_out; REPLY_PACKET_NUM_OUT(3*i+2 downto 3*i)<= reply_pool_packet_num_out; REPLY_DATAREADY_OUT(i) <= reply_pool_dataready_out and act_init_mask(i); end generate; + + + proc_timeout_cntr : process begin + wait until rising_edge(CLK); + for i in 0 to POINT_NUMBER-1 loop + timeout_ports_disable(i) <= timeout_cntr(i)(1); + if reset_i = '1' or CTRL_activepoints(i) = '0' then + timeout_cntr(i) <= (others => '0'); + elsif currentstate = FINISHED and timeout_ports(i) = '1' and timeout_cntr(i)(1) = '0' then + timeout_cntr(i) <= timeout_cntr(i) + 1; + end if; + end loop; + end process; + + ---------------------------------- --Status registers @@ -491,7 +541,7 @@ reply_mux_read_out_i(act_reply_port) <= reply_pool_free and reply_open; proc_stat_errorbits : process begin wait until rising_edge(CLK); if currentstate /= IDLE then - STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= not reply_got_trm or not real_active_points or not act_init_mask; + STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= not reply_got_trm and real_active_points and not act_init_mask; else STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= (others => '0'); end if; @@ -515,13 +565,29 @@ reply_mux_read_out_i(act_reply_port) <= reply_pool_free and reply_open; end process; STAT_ALL_ERRORBITS(15*32+31 downto POINT_NUMBER*32) <= (others => '0'); - STAT_TIMEOUT(POINT_NUMBER-1 downto 0) <= timeout_ports; - STAT_TIMEOUT(31 downto POINT_NUMBER) <= (others => '0'); + STAT_TIMEOUT(POINT_NUMBER-1 downto 0) <= timeout_ports; + STAT_TIMEOUT(15 downto POINT_NUMBER) <= (others => '0'); + STAT_TIMEOUT(16+POINT_NUMBER-1 downto 16) <= timeout_ports_disable; + STAT_TIMEOUT(31 downto 16+POINT_NUMBER) <= (others => '0'); STAT_locked <= '0' when currentstate = IDLE else '1'; - STAT <= (others => '0'); - + + PROC_FSMstate : process begin + wait until rising_edge(CLK); + case currentstate is + when IDLE => STAT(3 downto 0) <= x"1"; + when SELECT_INIT => STAT(3 downto 0) <= x"2"; + when FORWARD_INIT => STAT(3 downto 0) <= x"3"; + when SELECT_REPLY => STAT(3 downto 0) <= x"4"; + when WAIT_FOR_SELECT => STAT(3 downto 0) <= x"5"; + when FORWARD_REPLY => STAT(3 downto 0) <= x"6"; + when REPLY_TIMEOUT => STAT(3 downto 0) <= x"7"; + when SEND_TRM => STAT(3 downto 0) <= x"8"; + when FINISHED => STAT(3 downto 0) <= x"F"; + end case; + end process; + end architecture; diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index cacd049..d488859 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -258,8 +258,8 @@ begin ) variable regnum_STAT : integer range 0 to 2**NUM_STAT_REGS-1; variable regnum_CTRL : integer range 0 to 2**NUM_CTRL_REGS-1; - variable regnum_cSTAT : integer range 0 to std_COMSTATREG-1; - variable regnum_cCTRL : integer range 0 to std_COMCTRLREG-1; + variable regnum_cSTAT : integer range 0 to 15; --std_COMSTATREG-1; + variable regnum_cCTRL : integer range 0 to 2**std_COMneededwidth-1; --std_COMCTRLREG-1; begin next_state <= current_state; next_address <= address; diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 6e33b9c..76800fb 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -1647,7 +1647,8 @@ end component; component trb_net16_lsm_sfp is generic( - CHECK_FOR_CV : integer := c_YES + CHECK_FOR_CV : integer := c_YES; + HIGHSPEED_STARTUP : integer := c_NO ); port( SYSCLK : in std_logic; -- fabric clock