From: Jan Michel Date: Fri, 28 Jun 2013 11:41:40 +0000 (+0200) Subject: added JTAG status registers X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=4b1513c583b482d6c235954c12e3f5611e615d49;p=daqtools.git added JTAG status registers --- diff --git a/xml-db/database/jtag_registers_SPEC.xml b/xml-db/database/jtag_registers_SPEC.xml index 00dc239..7805ffe 100644 --- a/xml-db/database/jtag_registers_SPEC.xml +++ b/xml-db/database/jtag_registers_SPEC.xml @@ -1,102 +1,207 @@ - - - - Wait time between write sequence and start signal. - - The number of MAPS clock cycles to wait after last write before sending the start signal. - - - - - Trigger the init sequence. - - A bitmask to trigger the init sequence on individual JTAG chains. - - - - - Trigger the init sequence. - - A bitmask to trigger sending a reset pulse on individual JTAG chains - - - - - Trigger sending a start pulse. - - A bitmask to trigger sending a start pulse on individual JTAG chains - - - - - Trigger running JTAG write. - - A bitmask to trigger writing the JTAG registers three times on individual JTAG chains - - - - - Generate a reset before doing init sequence - - Enable to send a reset pulse before starting init sequence - - - - - Generate a reset after first register write sequence - - Enable to send a reset pulse after the first writing of JTAG registers - - - - - Trigger writing all JTAG registers once - - Trigger writing all JTAG registers once on individual JTAG chains - - - - - Sets fixed values for all outputs for JTAG and sensor control and inverts the outputs if needed. One register for each JTAG chain. - - + xsi:noNamespaceSchemaLocation="TrbNet.xsd" + name="JtagController" + offset="0000" + > + + + + + + Wait time between write sequence and start signal. + + The number of MAPS clock cycles to wait after last write before sending the start signal. + + + + Trigger the init sequence. + + A bitmask to trigger the init sequence on individual JTAG chains. + + + + Trigger the init sequence. + + A bitmask to trigger sending a reset pulse on individual JTAG chains + + + + Trigger sending a start pulse. + + A bitmask to trigger sending a start pulse on individual JTAG chains + + + + Trigger running JTAG write. + + A bitmask to trigger writing the JTAG registers three times on individual JTAG chains + + + + Generate a reset before doing init sequence + + Enable to send a reset pulse before starting init sequence + + + + Generate a reset after first register write sequence + + Enable to send a reset pulse after the first writing of JTAG registers + + + + Trigger writing all JTAG registers once + + Trigger writing all JTAG registers once on individual JTAG chains + + + + Sets fixed values for all outputs for JTAG and sensor control and inverts the outputs if needed. One register for each JTAG chain. + + Sets fixed values for all outputs for JTAG and sensor control and inverts the outputs if needed. One register for each JTAG chain. + + Invert TDO input signal + + + Invert TDI output signal + + + Invert TMS output signal + + + Invert TCK output signal + + + Invert Start output signal + + + Invert Reset output signal + + + Invert Clock output signal + + + Enable TDO input signal + + + Enable TDI output signal + + + Enable TMS output signal + + + Enable TCK output signal + + + Enable Start output signal + + + Enable Reset output signal + + + Enable Clock output signal + + + + + + + + + + + + Number of read errors during "read id" operation + + + Number of read errors during write operation + + + + + Number of times data read back from the sensor was not identical to the data written to the sensor. + + + Number of sampling errors of TDI signal. The signal from the sensor is sampled three times for each bit, all occurrences must be equal. + + + + + Number of times the JTAG controller run a full sequence + + + + + JTAG has been started + + + Last JTAG run was successful + + + Data in the sensor was corrupted at last JTAG run + + + Last run had a JTAG write error + + + Last run had a JTAG read error + + + Last run had a JTAG CRC error + + + - - -