From: hadaq <hadaq>
Date: Wed, 23 Jun 2010 17:25:03 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~265
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=4b57a7a9b366beb1fdd4cc8f57dbe3d48b1acdd3;p=trbnet.git

*** empty log message ***
---

diff --git a/trb_net_sbuf5.vhd b/trb_net_sbuf5.vhd
index b5eb11f..b810473 100644
--- a/trb_net_sbuf5.vhd
+++ b/trb_net_sbuf5.vhd
@@ -49,6 +49,18 @@ port(
 );
 end component fifo_19x16_obuf;
 
+
+--component dbg_reg is
+--generic(
+--	WIDTH      : integer := 1
+--);
+--port(
+--	DEBUG_IN   : in  std_logic_vector(WIDTH-1 downto 0);
+--	DEBUG_OUT  : out std_logic_vector(WIDTH-1 downto 0)
+--);
+--end component dbg_reg;
+
+
 type STATES is (IDLE, RD1, RD2, RD3, RD4, RD5, WT5, WR5, WD5, DEL);
 signal CURRENT_STATE, NEXT_STATE: STATES;
 signal bsm_x                 : std_logic_vector(3 downto 0);
@@ -63,6 +75,7 @@ signal syn_data              : std_logic_vector(18 downto 0);
 
 signal p_wait_x              : std_logic;
 signal p_avail_x             : std_logic;
+signal p_really_x            : std_logic;
 
 signal fifo_data_i           : std_logic_vector(18 downto 0);
 signal fifo_data_o           : std_logic_vector(18 downto 0);
@@ -90,8 +103,30 @@ attribute syn_keep of bsm                 : signal is true;
 attribute syn_hier : string;
 attribute syn_hier of trb_net_sbuf5_arch : architecture is "flatten, firm";
 
+--attribute syn_noprune : boolean;
+--attribute syn_noprune of THE_DBG_REG : label is true;
+--signal my_debug                 : std_logic_vector(26 downto 0);
+
 begin
 
+
+---------------------------------------------------------------------
+-- VHDL / Synplify workaround for fixed nodes... creepy.
+---------------------------------------------------------------------
+--THE_DBG_REG: dbg_reg
+--generic map(
+--	WIDTH      => 27
+--)
+--port map(
+--	DEBUG_IN   => my_debug,
+--	DEBUG_OUT  => open
+--);
+--
+--my_debug(8 downto 4)   <= fifo_wcnt;
+--my_debug(3 downto 0)   <= bsm;
+---------------------------------------------------------------------
+---------------------------------------------------------------------
+
 ---------------------------------------------------------------------
 -- I/O
 ---------------------------------------------------------------------
@@ -125,10 +160,11 @@ port map(
 	AlmostFull     => fifo_almostfull --open
 );
 
-p_wait_x  <= '1' when (unsigned(fifo_wcnt) > x"0") else '0';
-p_avail_x <= '1' when ((unsigned(fifo_wcnt) >= x"2") and (COMB_DATAREADY_IN = '1')) or
+p_wait_x   <= '1' when (unsigned(fifo_wcnt) > x"0") else '0';
+p_avail_x  <= '1' when ((unsigned(fifo_wcnt) >= x"2") and (COMB_DATAREADY_IN = '1')) or
                        (unsigned(fifo_wcnt) >= x"3")
-                 else '0';
+                  else '0';
+p_really_x <= '1' when (unsigned(fifo_wcnt) >= x"3") else '0';
 
 -- was 3 and 4
 
@@ -154,7 +190,7 @@ begin
 end process STATE_MEM;
 
 -- state transitions
-STATE_TRANSFORM: process( CURRENT_STATE, p_wait_x, p_avail_x, SYN_READ_IN, syn_dataready, COMB_DATAREADY_IN )
+STATE_TRANSFORM: process( CURRENT_STATE, p_wait_x, p_avail_x, p_really_x, SYN_READ_IN, syn_dataready, COMB_DATAREADY_IN )
 begin
 	NEXT_STATE      <= IDLE; -- avoid latches
 	fifo_rd_en_x    <= '0';
@@ -215,7 +251,7 @@ begin
 						else
 							NEXT_STATE      <= RD5;
 						end if;
-		when WR5    =>  if( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then
+		when WR5    =>  if( (SYN_READ_IN = '1') and (p_really_x = '1') ) then
 							NEXT_STATE      <= RD2;
 							fifo_rd_en_x    <= '1';
 							--syn_dataready_x <= '1';