From: Tobias Weber <toweber86@gmail.com>
Date: Wed, 21 Feb 2018 14:01:31 +0000 (+0100)
Subject: Block Memory Reset
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=4ba55d5269597c3cef4e866df76aeef9074eeedc;p=trb3.git

Block Memory Reset
---

diff --git a/mupix/Mupix8/sources/BlockMemory.vhd b/mupix/Mupix8/sources/BlockMemory.vhd
index 8be5746..06055ec 100644
--- a/mupix/Mupix8/sources/BlockMemory.vhd
+++ b/mupix/Mupix8/sources/BlockMemory.vhd
@@ -8,6 +8,7 @@ entity BlockMemory is
     AddressWidth : integer := 10); --address width
   port (
     clk    : in  std_logic;-- clock
+    reset  : in  std_logic;-- reset
     WrEn   : in  std_logic;-- write enable
     WrAddr : in  std_logic_vector(AddressWidth - 1 downto 0);-- write address
     Din    : in  std_logic_vector(DataWidth - 1 downto 0);-- data in
@@ -24,11 +25,15 @@ begin
 
   MemoryControll : process(clk)
   begin  -- process MemoryControll
-    if rising_edge(clk) then
-      Dout <= memory(to_integer(unsigned(ReAddr)));   --read memory
-      if(WrEn = '1') then
-        memory(to_integer(unsigned(WrAddr))) <= Din;  -- write memory
-      end if;
+  	if rising_edge(clk) then
+  		if reset = '1' then
+  			Dout <= (others => '0');
+  		else
+      		Dout <= memory(to_integer(unsigned(ReAddr)));   --read memory
+      		if(WrEn = '1') then
+        		memory(to_integer(unsigned(WrAddr))) <= Din;  -- write memory
+      		end if;
+    	end if;
     end if;
   end process MemoryControll;
 
diff --git a/mupix/Mupix8/sources/CircularMemory.vhd b/mupix/Mupix8/sources/CircularMemory.vhd
index eada2cc..b929e24 100644
--- a/mupix/Mupix8/sources/CircularMemory.vhd
+++ b/mupix/Mupix8/sources/CircularMemory.vhd
@@ -44,6 +44,7 @@ architecture RTL of CircularMemory is
 		);
 		port(
 			clk    : in  std_logic;
+			reset  : in  std_logic;
 			WrEn   : in  std_logic;
 			WrAddr : in  std_logic_vector(AddressWidth - 1 downto 0);
 			Din    : in  std_logic_vector(DataWidth - 1 downto 0);
@@ -86,6 +87,7 @@ begin
 		)
 		port map(
 			clk    => clk,
+			reset  => rst,
 			WrEn   => WrEn_mem,
 			WrAddr => WrAddr_mem,
 			Din    => Din_mem,
diff --git a/mupix/Mupix8/sources/Histogram.vhd b/mupix/Mupix8/sources/Histogram.vhd
index e2e0e15..939838f 100644
--- a/mupix/Mupix8/sources/Histogram.vhd
+++ b/mupix/Mupix8/sources/Histogram.vhd
@@ -31,6 +31,7 @@ architecture Behavioral of Histogram is
       AddressWidth : integer);
     port (
       clk    : in  std_logic;
+      reset  : in  std_logic;
       WrEn   : in  std_logic;
       WrAddr : in  std_logic_vector(AddressWidth - 1 downto 0);
       Din    : in  std_logic_vector(DataWidth - 1 downto 0);
@@ -59,6 +60,7 @@ begin
       AddressWidth => HistogramRange)
     port map (
       clk    => clk,
+      reset  => reset,
       WrEn   => MemWrEn,
       WrAddr => MemWrAddr,
       Din    => MemDIn,