From: Jan Michel Date: Tue, 14 Jul 2015 16:22:00 +0000 (+0200) Subject: update to trb3sc_pulser, ADC connection X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=4cd69437dbb44a10a2774d18698e39bcb870ce17;p=trb3sc.git update to trb3sc_pulser, ADC connection --- diff --git a/code/trb3sc_tools.vhd b/code/trb3sc_tools.vhd index 981e11d..277584d 100644 --- a/code/trb3sc_tools.vhd +++ b/code/trb3sc_tools.vhd @@ -134,7 +134,7 @@ begin busadc_tx.ack <= '0'; busadc_tx.data <= (others => '0'); - + --------------------------------------------------------------------------- -- SPI @@ -161,7 +161,13 @@ begin SPI_CS_OUT <= spi_cs; SPI_CLK_OUT <= (others => spi_sck); SPI_MOSI_OUT <= (others => spi_sdo); - spi_sdi <= or_all(SPI_MISO_IN and not spi_cs); + spi_sdi <= (ADC_MISO and not spi_cs(7)) or or_all(SPI_MISO_IN and not spi_cs and x"ff7f"); + + ADC_CLK <= not spi_sck; + ADC_CS <= spi_cs(7); + ADC_MOSI <= spi_sdo; + + end generate; busspi_tx.unknown <= '0'; diff --git a/pulser/trb3sc_pulser.lpf b/pulser/trb3sc_pulser.lpf index 3515067..73650b3 100644 --- a/pulser/trb3sc_pulser.lpf +++ b/pulser/trb3sc_pulser.lpf @@ -1,8 +1,8 @@ # PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ; # PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ; -PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_tx_full" ; -PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_tx_full" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_tx_full" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_tx_full" ; MULTICYCLE FROM CLKNET clk_sys TO CLKNET THE_PULSER/clk_slow_right 20 ns; MULTICYCLE FROM CLKNET clk_sys TO CLKNET THE_PULSER/clk_slow_left 20 ns; diff --git a/pulser/trb3sc_pulser.prj b/pulser/trb3sc_pulser.prj index b88f67e..a165503 100644 --- a/pulser/trb3sc_pulser.prj +++ b/pulser/trb3sc_pulser.prj @@ -98,7 +98,7 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" - +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/ram_18x256_oreg.vhd" #Flash & Reload, Tools add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" diff --git a/pulser/trb3sc_pulser.vhd b/pulser/trb3sc_pulser.vhd index 0dbbe0f..59e54e7 100644 --- a/pulser/trb3sc_pulser.vhd +++ b/pulser/trb3sc_pulser.vhd @@ -400,6 +400,7 @@ THE_PULSER : entity work.pulser HDR_IO(6) <= spi_cs(8); HDR_IO(10 downto 7) <= (others => '0'); + RJ_IO <= "0000"; @@ -434,7 +435,7 @@ THE_PULSER : entity work.pulser led(1) <= time_counter(20); --- TEST_LINE <= med_stat_debug(15 downto 0); +TEST_LINE <= med_stat_debug(15 downto 0); end architecture;