From: Cahit <c.ugur@gsi.de>
Date: Thu, 24 Apr 2014 21:38:10 +0000 (+0200)
Subject: corrected clock name for timing constraints
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=4cdec521da2c2cbdf57bcf827dc25f9e290b6349;p=trb3.git

corrected clock name for timing constraints
---

diff --git a/base/trb3_periph_ada.lpf b/base/trb3_periph_ada.lpf
index 2006ebd..e02c344 100644
--- a/base/trb3_periph_ada.lpf
+++ b/base/trb3_periph_ada.lpf
@@ -94,8 +94,8 @@ BLOCK RD_DURING_WR_PATHS ;
   FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
   FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
 
-MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
-MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
+MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_PCLK_LEFT_c" 1 X ;
+MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT_c" TO CLKNET "clk_100_i_c" 2 X ;
 
 LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;