From: Jan Michel Date: Fri, 16 Oct 2015 13:13:57 +0000 (+0200) Subject: updating TDC projects with some VHDL changes / new tools, new clock input to media... X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=4da172c613aacd99e6ef1a46be071bf0b538a8e6;p=trb3sc.git updating TDC projects with some VHDL changes / new tools, new clock input to media interface --- diff --git a/padiwa/trb3sc_padiwa.prj b/padiwa/trb3sc_padiwa.prj index cf089ce..4880165 100644 --- a/padiwa/trb3sc_padiwa.prj +++ b/padiwa/trb3sc_padiwa.prj @@ -72,7 +72,6 @@ add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" - #Fifos add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" diff --git a/padiwa/trb3sc_padiwa.vhd b/padiwa/trb3sc_padiwa.vhd index 19d9c65..ab61d7d 100644 --- a/padiwa/trb3sc_padiwa.vhd +++ b/padiwa/trb3sc_padiwa.vhd @@ -204,7 +204,8 @@ begin IS_SYNC_SLAVE => c_YES ) port map( - CLK => clk_full_osc, + CLK_REF_FULL => med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, SYSCLK => clk_sys, RESET => reset_i, CLEAR => clear_i, diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj index ef3b94b..128a7f8 100644 --- a/tdctemplate/trb3sc_tdctemplate.prj +++ b/tdctemplate/trb3sc_tdctemplate.prj @@ -73,6 +73,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record. add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" + #Fifos add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" @@ -113,6 +114,8 @@ add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index d683dfe..6e6521e 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -132,14 +132,14 @@ architecture trb3sc_arch of trb3sc_tdctemplate is signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to 0); - signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bustdc_rx : CTRLBUS_RX; - signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bustdc_tx : CTRLBUS_TX; + signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bustdc_rx, bus_master_out, handlerbus_rx : CTRLBUS_RX; + signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bustdc_tx, bus_master_in : CTRLBUS_TX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); signal sed_error_i : std_logic; - signal clock_select : std_logic; + signal bus_master_active : std_logic; signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); @@ -205,7 +205,8 @@ begin IS_SYNC_SLAVE => c_YES ) port map( - CLK => clk_full_osc, + CLK_REF_FULL => med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, SYSCLK => clk_sys, RESET => reset_i, CLEAR => clear_i, @@ -284,7 +285,6 @@ begin TIMERS_OUT => timer ); - --------------------------------------------------------------------------- -- Bus Handler @@ -300,7 +300,7 @@ begin CLK => clk_sys, RESET => reset_i, - REGIO_RX => ctrlbus_rx, + REGIO_RX => handlerbus_rx, REGIO_TX => ctrlbus_tx, BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED @@ -315,6 +315,8 @@ begin STAT_DEBUG => open ); + handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out; + --------------------------------------------------------------------------- -- Control Tools --------------------------------------------------------------------------- @@ -349,7 +351,10 @@ begin --Slowcontrol BUS_RX => bustools_rx, BUS_TX => bustools_tx, - + --Control master for default settings + BUS_MASTER_IN => ctrlbus_tx, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, DEBUG_OUT => open );