From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Thu, 2 Dec 2021 15:28:21 +0000 (+0100)
Subject: first working link up
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=4eb5b08f5050a65b9767f40d6f3377f49d4fc5f5;p=trb3sc.git

first working link up
---

diff --git a/tdctemplate/config_compile_gsi.pl b/tdctemplate/config_compile_gsi.pl
index 7ef1463..80de18f 100644
--- a/tdctemplate/config_compile_gsi.pl
+++ b/tdctemplate/config_compile_gsi.pl
@@ -9,7 +9,7 @@ nodelist_file                => 'nodelist.txt',
 pinout_file                  => 'trb3sc_padiwa',
 par_options                  => '../par.p2t',
     
-include_TDC                  => 1,
+include_TDC                  => 0,
 include_GBE                  => 0,
 
 firefox_open                 => 0,
diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj
index e737c79..fba5625 100644
--- a/tdctemplate/trb3sc_tdctemplate.prj
+++ b/tdctemplate/trb3sc_tdctemplate.prj
@@ -184,10 +184,11 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_lsm_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_rsl.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd"
diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd
index 2379684..fcdcb31 100644
--- a/tdctemplate/trb3sc_tdctemplate.vhd
+++ b/tdctemplate/trb3sc_tdctemplate.vhd
@@ -216,6 +216,7 @@ end generate;
 
   THE_MEDIA_INTERFACE : entity med_ecp3_sfp_sync_all_RS
     generic map(
+      SERDES_NUM         => 3,
       SIM_MODE           => 0,
       IS_MODE            => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE),
       IS_WAP_ZERO        => 1
@@ -224,8 +225,8 @@ end generate;
       -- Clocks and reset
       CLK_REF_FULL       => clk_full_osc,
       SYSCLK             => clk_sys,
-      RESET              => master_reset_i, --reset_i,
-      CLEAR              => master_reset_i, --clear_i,
+      RESET              => master_reset_i,
+      CLEAR              => master_reset_i,
       -- Media Interface TX/RX
       MEDIA_MED2INT(0)   => open, 
       MEDIA_MED2INT(1)   => open,
@@ -603,29 +604,29 @@ end generate;
 -------------------------------------------------------------------------------
 -- TDC
 -------------------------------------------------------------------------------
-  THE_TDC : TDC_record
-    generic map (
-      CHANNEL_NUMBER => NUM_TDC_CHANNELS,  -- Number of TDC channels per module
-      STATUS_REG_NR  => 21,             -- Number of status regs
-      DEBUG          => c_YES,
-      SIMULATION     => c_NO)
-    port map (
-      RESET              => reset_i,
-      CLK_TDC            => clk_full_osc,
-      CLK_READOUT        => clk_sys,    -- Clock for the readout
-      REFERENCE_TIME     => TRIG_LEFT,  -- Reference time input
-      HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
-      HIT_CAL_IN         => clk_cal,    -- Hits for calibrating the TDC
-      -- Trigger signals from handler
-      BUSRDO_RX          => readout_rx,
-      BUSRDO_TX          => readout_tx(0),
-      -- Slow control bus
-      BUS_RX             => bustdc_rx,
-      BUS_TX             => bustdc_tx,
-      -- Dubug signals
-      INFO_IN            => timer,
-      LOGIC_ANALYSER_OUT => logic_analyser_i
-      );
+--  THE_TDC : TDC_record
+--    generic map (
+--      CHANNEL_NUMBER => NUM_TDC_CHANNELS,  -- Number of TDC channels per module
+--      STATUS_REG_NR  => 21,             -- Number of status regs
+--      DEBUG          => c_YES,
+--      SIMULATION     => c_NO)
+--    port map (
+--      RESET              => reset_i,
+--      CLK_TDC            => clk_full_osc,
+--      CLK_READOUT        => clk_sys,    -- Clock for the readout
+--      REFERENCE_TIME     => TRIG_LEFT,  -- Reference time input
+--      HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
+--      HIT_CAL_IN         => clk_cal,    -- Hits for calibrating the TDC
+--      -- Trigger signals from handler
+--      BUSRDO_RX          => readout_rx,
+--      BUSRDO_TX          => readout_tx(0),
+--      -- Slow control bus
+--      BUS_RX             => bustdc_rx,
+--      BUS_TX             => bustdc_tx,
+--      -- Dubug signals
+--      INFO_IN            => timer,
+--      LOGIC_ANALYSER_OUT => logic_analyser_i
+--      );
 
       
 gen_normal_pins : if PINOUT = 1 or PINOUT = 2 or PINOUT = 3 generate