From: hadeshyp Date: Tue, 3 Aug 2010 13:39:55 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~202 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=50b93a62ff73242b4ac7a20eab24e5817ba1d3ae;p=trbnet.git *** empty log message *** --- diff --git a/gbe_ecp2m/trb_net16_gbe_buf.vhd b/gbe_ecp2m/trb_net16_gbe_buf.vhd index e5ec7ec..863c81b 100755 --- a/gbe_ecp2m/trb_net16_gbe_buf.vhd +++ b/gbe_ecp2m/trb_net16_gbe_buf.vhd @@ -19,8 +19,7 @@ generic( port( CLK : in std_logic; TEST_CLK : in std_logic; -- only for simulation! - CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode - CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode + CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode RESET : in std_logic; GSR_N : in std_logic; -- Debug @@ -434,6 +433,9 @@ signal monitor_dropped : std_logic_vector(31 downto 0); signal monitor_sm : std_logic_vector(31 downto 0); signal monitor_lr : std_logic_vector(31 downto 0); signal monitor_hr : std_logic_vector(31 downto 0); +signal monitor_fifos : std_logic_vector(31 downto 0); +signal monitor_fifos_q : std_logic_vector(31 downto 0); + begin @@ -494,6 +496,7 @@ port map( MONITOR_SM_IN => monitor_sm, MONITOR_LR_IN => monitor_lr, MONITOR_HDR_IN => monitor_hr, + MONITOR_FIFOS_IN => monitor_fifos_q, -- gk 01.06.10 DBG_IPU2GBE1_IN => dbg_ipu2gbe1, DBG_IPU2GBE2_IN => dbg_ipu2gbe2, @@ -615,6 +618,7 @@ port map( MONITOR_OUT(95 downto 64) => monitor_hr, MONITOR_OUT(127 downto 96) => monitor_sm, MONITOR_OUT(159 downto 128) => monitor_lr, + MONITOR_OUT(191 downto 160) => monitor_fifos, DEBUG_OUT(31 downto 0) => dbg_ipu2gbe1, DEBUG_OUT(63 downto 32) => dbg_ipu2gbe2, DEBUG_OUT(95 downto 64) => dbg_ipu2gbe3, @@ -663,22 +667,29 @@ port map( DEBUG_OUT(31 downto 0) => dbg_pc1, DEBUG_OUT(63 downto 32) => dbg_pc2 ); - + +monitor_fifos_q(3 downto 0) <= monitor_fifos(3 downto 0); +monitor_fifos_q(7 downto 4) <= b"1111" when ((dbg_pc1(28) = '1') or (dbg_pc1(31) = '1')) + else b"0000"; +monitor_fifos_q(11 downto 8) <= b"1111" when (dbg_fc1(28) = '1') else b"0000"; +monitor_fifos_q(15 downto 12) <= b"1111" when (pcs_an_complete = '0') else b"0000"; + -- Third stage: Frame Constructor FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr port map( -- ports for user logic - RESET => RESET, - CLK => CLK, + RESET => RESET, + CLK => CLK, + LINK_OK_IN => pcs_an_complete, -- gk 03.08.10 -- - WR_EN_IN => fc_wr_en, - DATA_IN => fc_data, + WR_EN_IN => fc_wr_en, + DATA_IN => fc_data, START_OF_DATA_IN => fc_sod, END_OF_DATA_IN => fc_eod, IP_F_SIZE_IN => fc_ip_size, UDP_P_SIZE_IN => fc_udp_size, HEADERS_READY_OUT => fc_h_ready, - READY_OUT => fc_ready, + READY_OUT => fc_ready, DEST_MAC_ADDRESS_IN => fc_dest_mac, DEST_IP_ADDRESS_IN => fc_dest_ip, DEST_UDP_PORT_IN => fc_dest_udp, @@ -687,49 +698,50 @@ port map( SRC_UDP_PORT_IN => fc_src_udp, FRAME_TYPE_IN => fc_type, IHL_VERSION_IN => fc_ihl_version, - TOS_IN => fc_tos, + TOS_IN => fc_tos, IDENTIFICATION_IN => fc_ident, FLAGS_OFFSET_IN => fc_flags_offset, - TTL_IN => fc_ttl, - PROTOCOL_IN => fc_protocol, + TTL_IN => fc_ttl, + PROTOCOL_IN => fc_protocol, -- ports for packetTransmitter - RD_CLK => serdes_clk_125, + RD_CLK => serdes_clk_125, FT_DATA_OUT => ft_data, --FT_EOD_OUT => ft_eod, -- gk 04.05.10 FT_TX_EMPTY_OUT => ft_tx_empty, FT_TX_RD_EN_IN => mac_tx_read, - FT_START_OF_PACKET_OUT => ft_start_of_packet, + FT_START_OF_PACKET_OUT => ft_start_of_packet, FT_TX_DONE_IN => mac_tx_done, -- debug ports BSM_CONSTR_OUT => fc_bsm_constr, BSM_TRANS_OUT => fc_bsm_trans, DEBUG_OUT(31 downto 0) => dbg_fc1, DEBUG_OUT(63 downto 32) => dbg_fc2 -); - +); + FRAME_TRANSMITTER: trb_net16_gbe_frame_trans port map( - CLK => CLK, - RESET => RESET, - TX_MAC_CLK => serdes_clk_125, - TX_EMPTY_IN => ft_tx_empty, + CLK => CLK, + RESET => RESET, + LINK_OK_IN => pcs_an_complete, -- gk 03.08.10 + TX_MAC_CLK => serdes_clk_125, + TX_EMPTY_IN => ft_tx_empty, START_OF_PACKET_IN => ft_start_of_packet, DATA_ENDFLAG_IN => ft_data(8), -- ft_eod -- gk 04.05.10 -- MAC interface - HADDR_OUT => mac_haddr, - HDATA_OUT => mac_hdataout, - HCS_OUT => mac_hcs, - HWRITE_OUT => mac_hwrite, - HREAD_OUT => mac_hread, - HREADY_IN => mac_hready, - HDATA_EN_IN => mac_hdata_en, + HADDR_OUT => mac_haddr, + HDATA_OUT => mac_hdataout, + HCS_OUT => mac_hcs, + HWRITE_OUT => mac_hwrite, + HREAD_OUT => mac_hread, + HREADY_IN => mac_hready, + HDATA_EN_IN => mac_hdata_en, TX_FIFOAVAIL_OUT => mac_fifoavail, TX_FIFOEOF_OUT => mac_fifoeof, TX_FIFOEMPTY_OUT => mac_fifoempty, - TX_DONE_IN => mac_tx_done, + TX_DONE_IN => mac_tx_done, -- Debug BSM_INIT_OUT => ft_bsm_init, - BSM_MAC_OUT => ft_bsm_mac, + BSM_MAC_OUT => ft_bsm_mac, BSM_TRANS_OUT => ft_bsm_trans, DBG_RD_DONE_OUT => open, DBG_INIT_DONE_OUT => open, @@ -830,10 +842,7 @@ imp_gen: if (DO_SIMULATION = 0) generate RESET => RESET, GSR_N => GSR_N, CLK_125_OUT => serdes_clk_125, - CLK_RX_OUT => open, - CLK_TX_OUT => open, - CLK_125_TX_IN => CLK_125_TX_IN, - CLK_125_RX_IN => CLK_125_RX_IN, + CLK_125_IN => CLK_125_IN, FT_TX_CLK_EN_OUT => mac_tx_clk_en, FT_RX_CLK_EN_OUT => mac_rx_clk_en, --connection to frame transmitter (tsmac) @@ -878,10 +887,7 @@ imp_gen: if (DO_SIMULATION = 0) generate port map( RESET => RESET, GSR_N => GSR_N, CLK_125_OUT => serdes_clk_125, - CLK_RX_OUT => open, - CLK_TX_OUT => open, - CLK_125_TX_IN => '0', -- not used - CLK_125_RX_IN => '0', -- not used + CLK_125_IN => '0', -- not used FT_TX_CLK_EN_OUT => mac_tx_clk_en, FT_RX_CLK_EN_OUT => mac_rx_clk_en, --connection to frame transmitter (tsmac) diff --git a/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd b/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd index d9ece24..4e5f0e8 100755 --- a/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd +++ b/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd @@ -13,6 +13,7 @@ port( -- ports for user logic RESET : in std_logic; CLK : in std_logic; + LINK_OK_IN : in std_logic; -- gk 03.08.10 -- WR_EN_IN : in std_logic; DATA_IN : in std_logic_vector(7 downto 0); @@ -51,6 +52,11 @@ end trb_net16_gbe_frame_constr; architecture trb_net16_gbe_frame_constr of trb_net16_gbe_frame_constr is +-- -- Placer Directives +-- attribute HGROUP : string; +-- -- for whole architecture +-- attribute HGROUP of trb_net16_gbe_frame_constr : architecture is "GBE_frame_constr_group"; + component fifo_4096x9 is port( Data : in std_logic_vector(8 downto 0); @@ -76,7 +82,7 @@ signal constructCurrentState, constructNextState : constructStates; signal bsm_constr : std_logic_vector(7 downto 0); attribute sys_encoding of constructCurrentState: signal is "safe,gray"; -type transmitStates is (T_IDLE, T_LOAD, T_TRANSMIT, T_CLEANUP); +type transmitStates is (T_IDLE, T_LOAD, T_TRANSMIT, T_PAUSE, T_CLEANUP); signal transmitCurrentState, transmitNextState : transmitStates; signal bsm_trans : std_logic_vector(3 downto 0); @@ -450,11 +456,16 @@ begin end if; when T_TRANSMIT => bsm_trans <= x"2"; - if( ft_tx_done_in = '1' ) then + -- gk 03.08.10 + if (LINK_OK_IN = '1') and (ft_tx_done_in = '1') then transmitNextState <= T_CLEANUP; + elsif (LINK_OK_IN = '0') then + transmitNextState <= T_PAUSE; else transmitNextState <= T_TRANSMIT; end if; + when T_PAUSE => + transmitNextState <= T_CLEANUP; when T_CLEANUP => bsm_trans <= x"3"; transmitNextState <= T_IDLE; @@ -464,6 +475,8 @@ begin end case; end process transmitMachine; + + sopProc: process( RD_CLK ) begin if rising_edge(RD_CLK) then @@ -482,7 +495,8 @@ begin if rising_edge(RD_CLK) then if ( RESET = '1' ) then sent_frames_ctr <= (others => '0'); - elsif( ft_tx_done_in = '1' ) then + -- gk 03.08.10 + elsif( ft_tx_done_in = '1' ) or (transmitCurrentState = T_PAUSE) then sent_frames_ctr <= sent_frames_ctr + 1; end if; end if; diff --git a/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd b/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd index 284b26f..b1cc4f1 100755 --- a/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd +++ b/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd @@ -12,6 +12,7 @@ entity trb_net16_gbe_frame_trans is port ( CLK : in std_logic; RESET : in std_logic; + LINK_OK_IN : in std_logic; -- gk 03.08.10 TX_MAC_CLK : in std_logic; TX_EMPTY_IN : in std_logic; START_OF_PACKET_IN : in std_logic; @@ -43,6 +44,11 @@ end trb_net16_gbe_frame_trans; architecture trb_net16_gbe_frame_trans of trb_net16_gbe_frame_trans is +-- -- Placer Directives +-- attribute HGROUP : string; +-- -- for whole architecture +-- attribute HGROUP of trb_net16_gbe_frame_trans : architecture is "GBE_frame_trans_group"; + component mac_init_mem is port ( Address : in std_logic_vector(5 downto 0); @@ -127,7 +133,7 @@ begin end if; when T_WAITFORFIFO => bsm_trans <= x"2"; - if (TX_DONE_IN = '1') then + if (TX_DONE_IN = '1') or (LINK_OK_IN = '0') then -- gk 03.08.10 transmitNextState <= T_IDLE; else transmitNextState <= T_WAITFORFIFO; diff --git a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd index d09e4b0..d69d976 100755 --- a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd +++ b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd @@ -45,6 +45,11 @@ end trb_net16_gbe_packet_constr; architecture trb_net16_gbe_packet_constr of trb_net16_gbe_packet_constr is +-- -- Placer Directives +-- attribute HGROUP : string; +-- -- for whole architecture +-- attribute HGROUP of trb_net16_gbe_packet_constr : architecture is "GBE_packet_constr_group"; + component fifo_64kx9 port ( Data : in std_logic_vector(8 downto 0); diff --git a/gbe_ecp2m/trb_net16_ipu2gbe.vhd b/gbe_ecp2m/trb_net16_ipu2gbe.vhd index 0755d2c..cb01006 100755 --- a/gbe_ecp2m/trb_net16_ipu2gbe.vhd +++ b/gbe_ecp2m/trb_net16_ipu2gbe.vhd @@ -56,6 +56,11 @@ end entity; architecture trb_net16_ipu2gbe of trb_net16_ipu2gbe is +-- -- Placer Directives +-- attribute HGROUP : string; +-- -- for whole architecture +-- attribute HGROUP of trb_net16_ipu2gbe : architecture is "GBE_ipu2gbe_group"; + component fifo_32kx16x8_mb2 port( Data : in std_logic_vector(17 downto 0);