From: hadeshyp <hadeshyp>
Date: Mon, 31 Aug 2009 11:30:09 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~382
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=50c355f66de8b30fb87bafe50d6ec421585d44a5;p=trbnet.git

*** empty log message ***
---

diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd
index a4e0130..426e79d 100644
--- a/trb_net16_endpoint_hades_full.vhd
+++ b/trb_net16_endpoint_hades_full.vhd
@@ -676,14 +676,14 @@ begin
       INT_DATA_IN        => MED_IO_DATA_OUT,
       INT_PACKET_NUM_IN  => MED_IO_PACKET_NUM_OUT,
       INT_READ_OUT       => MED_IO_READ_IN,
-      STAT               => STAT_DEBUG_1,
+      STAT               => open,
       CTRL               => CTRL_MPLEX
       );
 
 buf_CTRL_GEN <= IOBUF_CTRL_GEN;
 REGIO_COMMON_CTRL_REG_OUT <= buf_REGIO_COMMON_CTRL_REG_OUT;
 
---STAT_DEBUG_1 <= STAT_MPLEX;
+STAT_DEBUG_1 <= REGIO_REGIO_STAT;
 STAT_DEBUG_2(3 downto 0)  <= MED_IO_DATA_OUT(7*16+3 downto 7*16);
 STAT_DEBUG_2(7 downto 4)  <= apl_to_buf_REPLY_DATA(3*16+3 downto 3*16);
 STAT_DEBUG_2(8)           <= apl_to_buf_REPLY_DATAREADY(3);
diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd
index 7123784..4d5f0c0 100644
--- a/trb_net16_regIO.vhd
+++ b/trb_net16_regIO.vhd
@@ -832,11 +832,11 @@ begin
   process(CLK)
     begin
       if rising_edge(CLK) then
-        if RESET = '1' then
+        if RESET = '1'  or current_state = IDLE then
           DAT_DATAREADY_IN_before <= '0';
         elsif DAT_DATAREADY_IN = '1' then
           DAT_DATAREADY_IN_before <= '1';
-        elsif API_READ_IN = '1' and buf_API_DATAREADY_OUT = '1' then
+        elsif (API_READ_IN = '1' and buf_API_DATAREADY_OUT = '1')then
           DAT_DATAREADY_IN_before <= '0';
         end if;
       end if;
@@ -1017,7 +1017,15 @@ begin
   STAT(6 downto 4) <= buf_API_PACKET_NUM_OUT;
   STAT(7) <= next_API_DATAREADY_OUT;
   STAT(15 downto 8) <= next_API_DATA_OUT(7 downto 0);
-  STAT(31 downto 16) <= (others => '0');
+  STAT(23 downto 16) <= DAT_ADDR_OUT(7 downto 0);
+  STAT(24) <= DAT_DATAREADY_IN;
+  STAT(25) <= DAT_DATAREADY_IN_before;
+  STAT(26) <= DAT_READ_ENABLE_OUT;
+  STAT(27) <= DAT_WRITE_ENABLE_OUT;
+  STAT(28) <= DAT_NO_MORE_DATA_IN;
+  STAT(29) <= DAT_UNKNOWN_ADDR_IN;
+  STAT(30) <= API_READ_IN;
+  STAT(31) <= '0';
 
   process(current_state)
     begin