From: hadaq Date: Mon, 12 Mar 2012 01:06:13 +0000 (+0000) Subject: added TRB3 support X-Git-Tag: v6.0~53 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=50cf413be2e28faf909771f234a505542b785ab9;p=trbnettools.git added TRB3 support --- diff --git a/libtrbnet/Makefile b/libtrbnet/Makefile index e4bd80f..e2430ce 100644 --- a/libtrbnet/Makefile +++ b/libtrbnet/Makefile @@ -1,14 +1,18 @@ # ------------ Compiler / Linker Options ------------------------------- -ifdef AXIS_TOP_DIR +ifdef ETRAX AXIS_USABLE_LIBS = UCLIBC GLIBC include $(AXIS_TOP_DIR)/tools/build/Rules.axis CPPFLAGS = -DETRAX else CC = gcc ifeq ($(shell uname -m), x86_64) - CPPFLAGS = -DX86_64 -DPEXOR + ARCH = -DX86_64 + endif + + ifdef TRB3 + CPPFLAGS = $(ARCH) -DTRB3 else - CPPFLAGS = -DPEXOR + CPPFLAGS = $(ARCH) -DPEXOR endif endif diff --git a/libtrbnet/Makefile.gbit b/libtrbnet/Makefile.gbit deleted file mode 100644 index 702b554..0000000 --- a/libtrbnet/Makefile.gbit +++ /dev/null @@ -1,113 +0,0 @@ -# ------------ Compiler / Linker Options ------------------------------- - -ifeq ($(shell uname -m), x86_64) - CPPFLAGS = -DX86_64 -DGBE -else - CPPFLAGS = -DGBE -endif - -CC = gcc -INCDIR = -I. -CPPFLAGS += #-DTRB_DEBUGGER #-DHEXMODE - -CFLAGS = -pipe -g -Wall -Winline -O3 -fPIC -finline-functions -finline-limit=600000 - -LD = $(CC) -LDFLAGS = -LIBDIR = -LOADLIBES = - -# ------------ TARGETS ------------------------------------------------- - -TARGETS = trbcmd trbdhcp trbflash - -LIB_TARGETS = libtrbnet.a - -# ------------ Libaries ------------------------------------------------ - -ifeq ($ARCH, crisv32) - AR = ar-cris -else - AR = ar -endif -ARFLAGS = -srv - -# ------------ Pattern Rules ------------------------------------------- - -# C Code: -%.o: %.c - $(CC) $< -c $(CFLAGS) $(CPPFLAGS) $(INCDIR) -o $@ - -# C++ Code: -%.o: %.cpp - $(CXX) $< -c $(CXXFLAGS) $(CPPFLAGS) $(INCDIR) -o $@ - -%.o: %.cc - $(CXX) $< -c $(CXXFLAGS) $(CPPFLAGS) $(INCDIR) -o $@ - -%.o: %.C - $(CXX) $< -c $(CXXFLAGS) $(CPPFLAGS) $(INCDIR) -o $@ - -# C/C++ Objects (set LD accordingly) -%: %.o - @echo LINKING $@ - $(LD) $^ $(LDFLAGS) $(LIBDIR) $(LOADLIBES) -o $@ - @echo DONE! - -# Libaries -%.a: $% - @echo CREATING library $@ - $(AR) $(ARFLAGS) $@ $^ - @echo DONE! - -%.so: $% - @echo CREATING shared library $@ - $(LD) -shared -O $^ -o $@ - @echo DONE! - -# ------------ Targets ------------------------------------------------- - -.PHONY: all -all: $(LIB_TARGETS) $(TARGETS) - -.PHONY: clean -clean: - rm -f *.o core core.* - rcsclean - -.PHONY: distclean -distclean: clean - rm -f $(TARGETS) $(LIB_TARGETS) - find . -type l -exec rm {} \; - rcsclean -u - -.PHONY: depend -depend: - $(CC) -MM $(CFLAGS) $(CPPFLAGS) $(INCDIR) *.c - -# ------------ Dependencies -------------------------------------------- - -ifndef AXIS_TOP_DIR -pexor_user.h: - ln -s ../pexor/kernel-module/pexor_user.h - -trbnet.o: trbnet.c trberror.h trbnet.h pexor_user.h -else -trbnet.o: trbnet.c trberror.h trbnet.h -endif - -trberror.o: trberror.c trberror.h - -libtrbnet.a: trberror.o trbnet.o - -libtrbnet.so: trberror.o trbnet.o - -trbcmd: trbcmd.o libtrbnet.a -trbcmd.o: trbcmd.c trbnet.h trberror.h - -trbdhcp: trbdhcp.o libtrbnet.a -trbdhcp.o: trbdhcp.c trbnet.h trberror.h - -trbflash: trbflash.o libtrbnet.a -trbflash.o: trbflash.c - diff --git a/libtrbnet/trbcmd.c b/libtrbnet/trbcmd.c index d70ca8c..9144dc2 100644 --- a/libtrbnet/trbcmd.c +++ b/libtrbnet/trbcmd.c @@ -25,7 +25,7 @@ static int hexMode = HEXMODE; -static const char trbcmd_version[] = "$Revision: 2.79 $"; +static const char trbcmd_version[] = "$Revision: 2.80 $"; #define BACKLOG 10 static uint16_t tcp_port = 55555; @@ -811,7 +811,8 @@ int start(int argc, char **argv) } if (network_reset() == -1) { - logError(ERROR, "TRBNet RESET failed\n"); + logError(ERROR, "TRBNet RESET failed: %s\n", + trb_strerror()); return -1; } @@ -1086,10 +1087,10 @@ int start(int argc, char **argv) } if (fpga_register_write(reg_address, value) == -1) { - logError(ERROR, "fpga_register_write failed\n"); + logError(ERROR, "fpga_register_write failed: %s\n", + trb_strerror()); return -1; } - } else if (strncmp(cmd[0], "setbit", CMD_SIZE) == 0) { /*******************************************/ diff --git a/libtrbnet/trberror.c b/libtrbnet/trberror.c index 88c0dec..2b5d460 100644 --- a/libtrbnet/trberror.c +++ b/libtrbnet/trberror.c @@ -88,10 +88,12 @@ const char* trb_errorstr(int trberrno) "Pexor Device Error ioctl call, Out of DMA buffers", "Pexor Device Error ioctl call, Invalid DMA Size", "Pexor Device Error ioctl call, Lost Credential(s)", - "Pexor Device Error ioctl call, FIFO Transfer Error" + "Pexor Device Error ioctl call, FIFO Transfer Error", + "Command is not supported by TRB3", + "TRB3 Socket Error" }; - if (trberrno < 36) { + if (trberrno < 38) { return errorstring[trberrno]; } if (trberrno >= 256) { diff --git a/libtrbnet/trberror.h b/libtrbnet/trberror.h index a5b8cde..dde90c3 100644 --- a/libtrbnet/trberror.h +++ b/libtrbnet/trberror.h @@ -43,7 +43,9 @@ typedef enum { TRB_PEXOR_DEVICE_DMA_EMPTY = 32, TRB_PEXOR_DEVICE_INVALID_DMA_SIZE = 33, TRB_PEXOR_DEVICE_LOST_CREDENTIAL = 34, - TRB_PEXOR_DEVICE_FIFO_TRANSFER = 35 + TRB_PEXOR_DEVICE_FIFO_TRANSFER = 35, + TRB_TRB3_CMD_NOT_SUPPORTED = 36, + TRB_TRB3_SOCKET_ERROR = 37 } TRB_ERROR; /* last TRBNet-TermPackage */ diff --git a/libtrbnet/trbnet.c b/libtrbnet/trbnet.c index ce773a0..f0775ec 100644 --- a/libtrbnet/trbnet.c +++ b/libtrbnet/trbnet.c @@ -1,4 +1,4 @@ -const char trbnet_version[] = "$Revision: 4.19 $ Local"; +const char trbnet_version[] = "$Revision: 4.20 $ Local"; #include #include @@ -29,8 +29,23 @@ int dma_size = 0; char pexor_deviceName[256] = "/dev/pexor-0"; int pexorFileHandle = -1; int pexor_dma = 1; + +#elif defined TRB3 + +#include +#include +#include +#include + +static uint16_t udpBuffer[750]; /* Maxminum is payload of one Ethernet-Frame */ +static uint32_t dataBuffer[4096 * 1024]; +static unsigned int dataBufferSize = 0; +static int trb3_sockfd = -1; +static uint16_t trb3_port = 26000; +uint16_t sender_address = 0x5555; #endif + #include #include "trbnet.h" @@ -257,7 +272,9 @@ static inline void com_reset_FPGA() fifoToggleBit = 0; } -#else /* PEXOR */ +#endif + +#ifdef PEXOR /* PEXOR */ static int pexor_to_trb_error() { @@ -348,6 +365,29 @@ static inline void com_reset_FPGA() #endif /* End PEXOR */ +#ifdef TRB3 + +static int sendTrbPackage(size_t size) +{ + int status; + + if (send(trb3_sockfd, (void*)udpBuffer, size, MSG_CONFIRM) == -1) { + trb_errno = TRB_TRB3_SOCKET_ERROR; + return -1; + } + + /* GetData */ + status = recv(trb3_sockfd, (void*)dataBuffer, 1500, 0); + if (status == -1) { + trb_errno = TRB_TRB3_SOCKET_ERROR; + return -1; + } + dataBufferSize = status; + + return status; +} +#endif /* TRB3 */ + /* ------ Internal Functions -------------------------------------------- */ static void TRB_Package_dump(const TRB_Package* pkg) @@ -454,6 +494,10 @@ static void TRB_Package_dump(const TRB_Package* pkg) static void fifo_flush(uint8_t channel) { +#ifdef TRB3 + return; +#else + uint32_t tmp = 0; uint32_t fifoAddress; unsigned int counter = 0; @@ -471,12 +515,14 @@ static void fifo_flush(uint8_t channel) counter++; } } while ((tmp & MASK_FIFO_VALID) != 0); + +#endif } static int trb_init_transfer(uint8_t channel) { +#ifndef TRB3 uint32_t tmp = 0; - if (channel >= 4) { trb_errno = TRB_INVALID_CHANNEL; return -1; @@ -485,17 +531,21 @@ static int trb_init_transfer(uint8_t channel) /* Check for TX not Busy */ read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp); if (tmp != 0) { + #ifdef ETRAX /* FIFO_TOGGLE_BIT-BUG Workaround */ com_reset_FPGA(); -#else +#endif + +#ifdef PEXOR /* First try to resolve it by flushing the fifo */ if (trb_debug > 0) { fprintf(stderr,"trb_init_transfer: flushing fifo because of TX Busy\n"); } fifo_flush(channel); #endif - /* Try again */ + + /* Try again */ read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp); if (tmp != 0) { trb_errno = TRB_TX_BUSY; @@ -519,6 +569,7 @@ static int trb_init_transfer(uint8_t channel) trb_errno = TRB_FIFO_NOT_EMPTY; return -1; } +#endif /* No Errors */ return 0; @@ -547,7 +598,7 @@ static int trb_fifo_read(uint8_t channel, uint32_t* tmp = &dataBuffer; uint32_t fifoBuffer = 0; unsigned int timeout = 0; -#else /* Pexor DMA */ +#elif defined PEXOR || defined TRB3 uint32_t* tmp = dataBuffer; #endif @@ -567,18 +618,7 @@ static int trb_fifo_read(uint8_t channel, uint32_t memLen = 0; /* used by FIFO_MODE_REG_READ_MEM and FIFO_MODE_IPU_DATA Mode */ -#ifdef PEXOR - if (dataBufferSize == 0) { - trb_errno = TRB_PEXOR_DATA_ERROR; - return -1; - } - if (read(pexorFileHandle, - (void*)dataBuffer, dataBufferSize * 4) != dataBufferSize * 4) { - trb_errno = TRB_PEXOR_DATA_ERROR; - return -1; - } -#else - +#ifdef ETRAX /* Determin FIFO-Address */ if (channel >= 4) { trb_errno = TRB_INVALID_CHANNEL; @@ -597,8 +637,20 @@ static int trb_fifo_read(uint8_t channel, trb_errno = TRB_FIFO_TIMEOUT; return -1; } +#else + if (dataBufferSize == 0) { + trb_errno = TRB_PEXOR_DATA_ERROR; + return -1; + } +#ifdef PEXOR + if (read(pexorFileHandle, + (void*)dataBuffer, dataBufferSize * 4) != dataBufferSize * 4) { + trb_errno = TRB_PEXOR_DATA_ERROR; + return -1; + } #endif - +#endif + /* Read FIFO-Buffer, copy to User-Buffer */ while ((*tmp & MASK_FIFO_VALID) != 0) { @@ -711,9 +763,7 @@ static int trb_fifo_read(uint8_t channel, != channel)) { /* Error Package inconsistencies, flush FIFO-BUFFER and exit */ -#ifdef ETRAX fifo_flush(channel); -#endif trb_errno = TRB_FIFO_HEADERS; return -1; } @@ -1122,14 +1172,7 @@ static int trb_fifo_read(uint8_t channel, if (headerType == HEADER_TRM) { break; } - -#ifdef PEXOR - if (tmp - dataBuffer >= dataBufferSize) { - trb_errno = TRB_PEXOR_DATA_ERROR; - return -1; - } - tmp++; -#else +#ifdef ETRAX timeout = 0; do { read32_from_FPGA(fifoBuffer, tmp); @@ -1140,8 +1183,13 @@ static int trb_fifo_read(uint8_t channel, trb_errno = TRB_FIFO_TIMEOUT; return -1; } +#else + if (tmp - dataBuffer >= dataBufferSize) { + trb_errno = TRB_PEXOR_DATA_ERROR; + return -1; + } + tmp++; #endif - } /* end while () */ /* Copy StatusBits and Sequenze of TerminationPackage */ @@ -1370,7 +1418,7 @@ void close_ports() GPIOC_OUT_OFFSET = NULL; } -#else /* PEXOR */ +#elif defined PEXOR void close_ports() { @@ -1406,7 +1454,63 @@ int init_ports() return 0; } -#endif /* End Pexor */ +#elif defined TRB3 + +void close_ports() +{ + /* Close FileHandler */ + return; +} + +int init_ports() +{ + char* trb3_name = NULL; + struct sockaddr_in server_addr; + struct hostent *host = NULL; + + trb_errno = TRB_NONE; + + if (trb_debug > 0) { + fprintf(stderr, "init_ports: called\n"); + } + + trb3_name = getenv("TRB3_SERVER"); + if (trb3_name == NULL) { + trb3_name = "pexor"; + } + + if ((host = gethostbyname(trb3_name)) == NULL) { + trb_errno = TRB_TRB3_SOCKET_ERROR; + return -1; + } + + trb3_sockfd = socket(AF_INET, SOCK_DGRAM, 0); + if (trb3_sockfd == -1) { + trb_errno = TRB_TRB3_SOCKET_ERROR; + return -1; + } + server_addr.sin_family = AF_INET; + server_addr.sin_port = htons(trb3_port); + server_addr.sin_addr = *((struct in_addr *)host->h_addr); + memset(&(server_addr.sin_zero), 0, 8); + if (connect(trb3_sockfd, + (struct sockaddr *)&server_addr, + sizeof(struct sockaddr)) == -1) { + trb_errno = TRB_TRB3_SOCKET_ERROR; + return -1; + } + + if (trb_debug > 0) { + fprintf(stderr, "init_ports: TRB3-Socket opened = %d\n", trb3_sockfd); + } + + /* Init semaphore and signal handling */ + if (init_semaphore() == -1) return -1; + + return 0; +} + +#endif int trb_fifo_flush(uint8_t channel) { @@ -1461,8 +1565,36 @@ int trb_register_read(uint16_t trb_address, write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ); -#else +#elif defined TRB3 + /* Create TRBPackage */ + udpBuffer[0] = HEADER_HDR; + udpBuffer[1] = sender_address; + udpBuffer[2] = trb_address; + udpBuffer[3] = 0; + udpBuffer[4] = CMD_REGISTER_READ; + + udpBuffer[5] = HEADER_DAT; + udpBuffer[6] = reg_address; + udpBuffer[7] = 0; + udpBuffer[8] = 0; + udpBuffer[9] = 0; + + udpBuffer[10] = HEADER_TRM; + udpBuffer[11] = 0; + udpBuffer[12] = 0; + udpBuffer[13] = 0; + udpBuffer[14] = CMD_REGISTER_READ; + + status = sendTrbPackage(15); + + if (status < 0) { + unlockPorts(0); + return -1; + } + dataBufferSize = status; + +#else /* Send command to pexor driver */ pexorDescriptor.trb_address = trb_address; @@ -1529,6 +1661,35 @@ int trb_registertime_read(uint16_t trb_address, write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ); + +#elif defined TRB3 + /* Create TRBPackage */ + udpBuffer[0] = HEADER_HDR; + udpBuffer[1] = sender_address; + udpBuffer[2] = trb_address; + udpBuffer[3] = 0; + udpBuffer[4] = CMD_REGISTER_READ; + + udpBuffer[5] = HEADER_DAT; + udpBuffer[6] = reg_address; + udpBuffer[7] = 0; + udpBuffer[8] = 0; + udpBuffer[9] = 0; + + udpBuffer[10] = HEADER_TRM; + udpBuffer[11] = 0; + udpBuffer[12] = 0; + udpBuffer[13] = 0; + udpBuffer[14] = CMD_REGISTER_READ; + + status = sendTrbPackage(15); + + if (status < 0) { + unlockPorts(0); + return -1; + } + dataBufferSize = status; + #else /* Send command to pexor driver */ pexorDescriptor.trb_address = trb_address; @@ -1607,7 +1768,37 @@ int trb_register_read_mem(uint16_t trb_address, write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ_MEM); + +#elif defined TRB3 + /* Create TRBPackage */ + udpBuffer[0] = HEADER_HDR; + udpBuffer[1] = sender_address; + udpBuffer[2] = trb_address; + udpBuffer[3] = 0; + udpBuffer[4] = CMD_REGISTER_READ_MEM; + + udpBuffer[5] = HEADER_DAT; + udpBuffer[6] = reg_address; + udpBuffer[7] = length; + udpBuffer[8] = 0; + udpBuffer[9] = 0; + + udpBuffer[10] = HEADER_TRM; + + udpBuffer[12] = 0; + udpBuffer[13] = 0; + udpBuffer[14] = CMD_REGISTER_READ_MEM; + + status = sendTrbPackage(15); + + if (status < 0) { + unlockPorts(0); + return -1; + } + dataBufferSize = status; + #else + /* Send command to pexor driver */ pexorDescriptor.trb_address = trb_address; pexorDescriptor.reg_address = reg_address; @@ -1695,7 +1886,37 @@ int trb_registertime_read_mem(uint16_t trb_address, write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ_MEM); + +#elif defined TRB3 + + udpBuffer[0] = HEADER_HDR; + udpBuffer[1] = sender_address; + udpBuffer[2] = trb_address; + udpBuffer[3] = 0; + udpBuffer[4] = CMD_REGISTER_READ_MEM; + + udpBuffer[5] = HEADER_DAT; + udpBuffer[6] = reg_address; + udpBuffer[7] = length; + udpBuffer[8] = 0; + udpBuffer[9] = 0; + + udpBuffer[10] = HEADER_TRM; + udpBuffer[11] = 0; + udpBuffer[12] = 0; + udpBuffer[13] = 0; + udpBuffer[14] = CMD_REGISTER_READ_MEM; + + status = sendTrbPackage(15); + + if (status < 0) { + unlockPorts(0); + return -1; + } + dataBufferSize = status; + #else + /* Send command to pexor driver */ pexorDescriptor.trb_address = trb_address; pexorDescriptor.reg_address = reg_address; @@ -1772,6 +1993,35 @@ int trb_register_write(uint16_t trb_address, write32_to_FPGA(CHANNEL_3_SENDER_DATA, value & 0xffff); write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE); + +#elif defined TRB3 + + udpBuffer[0] = HEADER_HDR; + udpBuffer[1] = sender_address; + udpBuffer[2] = trb_address; + udpBuffer[3] = 0; + udpBuffer[4] = CMD_REGISTER_WRITE; + + udpBuffer[5] = HEADER_DAT; + udpBuffer[6] = reg_address; + udpBuffer[7] = (value >> 16) & 0xffff; + udpBuffer[8] = value & 0xffff; + udpBuffer[9] = 0; + + udpBuffer[10] = HEADER_TRM; + udpBuffer[11] = 0; + udpBuffer[12] = 0; + udpBuffer[13] = 0; + udpBuffer[14] = CMD_REGISTER_WRITE; + + status = sendTrbPackage(15); + + if (status < 0) { + unlockPorts(0); + return -1; + } + dataBufferSize = status; + #else /* Send command to pexor driver */ pexorDescriptor.trb_address = trb_address; @@ -1812,9 +2062,12 @@ int trb_register_write_mem(uint16_t trb_address, uint16_t config; uint16_t ctr = 0; int status = -1; -#ifdef ETRAX +#if defined ETRAX || defined TRB3 uint16_t i; #endif +#ifdef TRB3 + unsigned int udpCtr = 0; +#endif trb_errno = TRB_NONE; @@ -1860,7 +2113,50 @@ int trb_register_write_mem(uint16_t trb_address, write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); } write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE_MEM); + +#elif defined TRB3 + + udpBuffer[0] = HEADER_HDR; + udpBuffer[1] = sender_address; + udpBuffer[2] = trb_address; + udpBuffer[3] = 0; + udpBuffer[4] = CMD_REGISTER_WRITE_MEM; + + udpBuffer[5] = HEADER_DAT; + if (option == 0) { + udpBuffer[6] = reg_address + ctr; + } else { + udpBuffer[6] = reg_address; + } + udpBuffer[7] = config; + udpBuffer[8] = 0; + udpBuffer[9] = 0; + + udpCtr = 10; + for (i = 0; i < len; i++, ctr++) { + udpBuffer[udpCtr++] = HEADER_DAT; + udpBuffer[udpCtr++] = 0x00000000; + udpBuffer[udpCtr++] = (data[ctr] >> 16) & 0xffff; + udpBuffer[udpCtr++] = data[ctr] & 0xffff; + udpBuffer[udpCtr++] = 0x00000000; + } + + udpBuffer[udpCtr++] = HEADER_TRM; + udpBuffer[udpCtr++] = 0; + udpBuffer[udpCtr++] = 0; + udpBuffer[udpCtr++] = 0; + udpBuffer[udpCtr++] = CMD_REGISTER_WRITE_MEM; + + status = sendTrbPackage(udpCtr); + + if (status < 0) { + unlockPorts(0); + return -1; + } + dataBufferSize = status; + #else + /* Send command to pexor driver */ if (write(pexorFileHandle, (void*)(data + ctr), len * 4) != len * 4) { @@ -1935,6 +2231,35 @@ int trb_read_uid(uint16_t trb_address, write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_NETADMINISTRATION); + +#elif defined TRB3 + + udpBuffer[0] = HEADER_HDR; + udpBuffer[1] = sender_address; + udpBuffer[2] = trb_address; + udpBuffer[3] = 0; + udpBuffer[4] = CMD_NETADMINISTRATION; + + udpBuffer[5] = HEADER_DAT; + udpBuffer[6] = NET_READUNIQUEID; + udpBuffer[7] = 0; + udpBuffer[8] = 0; + udpBuffer[9] = 0; + + udpBuffer[10] = HEADER_TRM; + udpBuffer[11] = 0; + udpBuffer[12] = 0; + udpBuffer[13] = 0; + udpBuffer[14] = CMD_NETADMINISTRATION; + + status = sendTrbPackage(15); + + if (status < 0) { + unlockPorts(0); + return -1; + } + dataBufferSize = status; + #else /* Send command to pexor driver */ pexorDescriptor.trb_address = trb_address; @@ -2008,7 +2333,43 @@ int trb_set_address(uint64_t uid, write32_to_FPGA(CHANNEL_3_SENDER_DATA, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_NETADMINISTRATION); + +#elif defined TRB3 + + udpBuffer[0] = HEADER_HDR; + udpBuffer[1] = sender_address; + udpBuffer[2] = trb_address; + udpBuffer[3] = 0; + udpBuffer[4] = CMD_NETADMINISTRATION; + + udpBuffer[5] = HEADER_DAT; + udpBuffer[6] = NET_SETADDRESS; + udpBuffer[7] = (uint16_t)(uid); + udpBuffer[8] = (uint16_t)(uid >> 16); + udpBuffer[9] = (uint16_t)(uid >> 32); + + udpBuffer[10] = HEADER_DAT; + udpBuffer[11] = (uint16_t)(uid >> 48); + udpBuffer[12] = endpoint; + udpBuffer[13] = trb_address; + udpBuffer[14] = 0; + + udpBuffer[15] = HEADER_TRM; + udpBuffer[16] = 0; + udpBuffer[17] = 0; + udpBuffer[18] = 0; + udpBuffer[19] = CMD_NETADMINISTRATION; + + status = sendTrbPackage(15); + + if (status < 0) { + unlockPorts(0); + return -1; + } + dataBufferSize = status; + #else + /* Send command to pexor driver */ pexorDescriptor.trb_address = trb_address; pexorDescriptor.arg0 = (unsigned long)(uid & 0xffffffff); @@ -2045,6 +2406,7 @@ int trb_set_address(uint64_t uid, return 0; } +#ifndef TRB3 int trb_ipu_data_read(uint8_t type, uint8_t trg_info, uint8_t trg_random, @@ -2513,6 +2875,75 @@ int trb_register_modify(uint16_t trb_address, return 0; } +#else /* NOT TRB3 */ + +int trb_ipu_data_read(uint8_t type, + uint8_t trg_info, + uint8_t trg_random, + uint16_t trg_number, + uint32_t *data, + unsigned int dsize) +{ + trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED; + return -1; +} + +int trb_send_trigger(uint8_t type, + uint32_t trg_info, + uint8_t trg_random, + uint16_t trg_number) +{ + trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED; + return -1; +} + +int trb_send_trigger_rich(uint8_t trg_input, + uint8_t type, + uint32_t trg_info, + uint8_t trg_random, + uint16_t trg_number) +{ + trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED; + return -1; +} + +int fpga_register_read(uint32_t reg_address, uint32_t* value) +{ + trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED; + return -1; +} + +int fpga_register_write(uint32_t reg_address, uint32_t value) +{ + trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED; + return -1; +} + +int network_reset() +{ + trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED; + return -1; +} + +int com_reset() +{ + trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED; + return -1; +} + +int trb_register_modify(uint16_t trb_address, + uint16_t reg_address, + int mode, + uint32_t bitMask, + uint32_t bitValue) +{ + trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED; + return -1; +} + + + +#endif int trb_nettrace(uint16_t trb_address, uint32_t *data, diff --git a/trbrich/Makefile b/trbrich/Makefile index 2065325..435cf57 100644 --- a/trbrich/Makefile +++ b/trbrich/Makefile @@ -1,14 +1,18 @@ # ------------ Compiler / Linker Options ------------------------------- - -ifdef AXIS_TOP_DIR +ifdef ETRAX AXIS_USABLE_LIBS = UCLIBC GLIBC include $(AXIS_TOP_DIR)/tools/build/Rules.axis + CPPFLAGS = -DETRAX else CC = gcc ifeq ($(shell uname -m), x86_64) - CPPFLAGS = -DPEXOR -DX86_64 + ARCH = -DX86_64 + endif + + ifdef TRB3 + CPPFLAGS = $(ARCH) -DTRB3 else - CPPFLAGS = -DPEXOR + CPPFLAGS = $(ARCH) -DPEXOR endif endif