From: Jan Michel <j.michel@gsi.de>
Date: Mon, 5 Mar 2018 12:40:17 +0000 (+0100)
Subject: Refine calibration timing. Fix montioring inputs for ADA AddOn and NINO input scheme.
X-Git-Tag: v2.3~18
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=527026dc9bef6315278ce192bb10b243684f9d0c;p=tdc.git

Refine calibration timing. Fix montioring inputs for ADA AddOn and NINO input scheme.
---

diff --git a/releases/tdc_v2.3/TDC_record.vhd b/releases/tdc_v2.3/TDC_record.vhd
index ad4e121..bbe33ee 100644
--- a/releases/tdc_v2.3/TDC_record.vhd
+++ b/releases/tdc_v2.3/TDC_record.vhd
@@ -243,7 +243,11 @@ begin
   begin
     if rising_edge(HIT_CAL_IN) then     -- rising clock edge
       if cal_cntr_start = '0' then
-        cal_cntr <= "01000";
+        if FPGA_TYPE = 3 then
+          cal_cntr <= "11100";
+        elsif FPGA_TYPE = 5 then
+          cal_cntr <= "01000";
+        end if;  
       else
         cal_cntr <= std_logic_vector(unsigned(cal_cntr) + to_unsigned(1, 5));
       end if;
diff --git a/releases/tdc_v2.3/trb3_periph_ADA.vhd b/releases/tdc_v2.3/trb3_periph_ADA.vhd
index 84074a4..d326232 100644
--- a/releases/tdc_v2.3/trb3_periph_ADA.vhd
+++ b/releases/tdc_v2.3/trb3_periph_ADA.vhd
@@ -108,6 +108,7 @@ architecture trb3_periph_ADA_arch of trb3_periph_ADA is
   signal clear_i                  : std_logic;
   signal reset_i                  : std_logic;
   signal GSR_N                    : std_logic;
+  signal osc_int                  : std_logic;
   attribute syn_keep of GSR_N     : signal is true;
   attribute syn_preserve of GSR_N : signal is true;
 
@@ -183,7 +184,11 @@ begin
       CLKOK => clk_200_i,               -- 200 MHz, bypass
       LOCK  => pll_lock);
 
-
+pll_calibration: entity work.pll_in125_out33
+  port map (
+    CLK   => CLK_GPLL_LEFT,
+    CLKOP => osc_int,
+    LOCK  => open);
 
 ---------------------------------------------------------------------------
 -- The TrbNet media interface (to other FPGA)
@@ -335,9 +340,9 @@ begin
       DEBUG_TX_OUT  => debug_tx,
 
       --Trigger & Monitor 
-      MONITOR_INPUTS(31 downto 0) => INP(31 downto 0),
+      MONITOR_INPUTS(31 downto 0) => hit_in_i(32 downto 1),
       MONITOR_INPUTS(35 downto 32) => trig_gen_out_i,
-      TRIG_GEN_INPUTS  => INP(31 downto 0),
+      TRIG_GEN_INPUTS  => hit_in_i(32 downto 1),
       TRIG_GEN_OUTPUTS => trig_gen_out_i,
       LCD_OUT => lcd_out,
       --SED
@@ -413,7 +418,7 @@ begin
       CLK_READOUT        => clk_100_i,  -- Clock for the readout
       REFERENCE_TIME     => timing_trg_received_i,  -- Reference time input
       HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
-      HIT_CAL_IN         => CLK_GPLL_LEFT,    -- Hits for calibrating the TDC
+      HIT_CAL_IN         => osc_int,    -- Hits for calibrating the TDC
       -- Trigger signals from handler
       BUSRDO_RX          => readout_rx,
       BUSRDO_TX          => readout_tx(0),