From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Tue, 28 Jun 2022 14:13:25 +0000 (+0200)
Subject: changed directories for cores
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=532cc93af7d4085ff8f159590fad54f6eeb048ae;p=trbnet.git

changed directories for cores
---

diff --git a/gbe_trb/base/gbe_med_interface_5G.vhd b/gbe_trb/base/gbe_med_interface_5G.vhd
deleted file mode 100644
index bc3610d..0000000
--- a/gbe_trb/base/gbe_med_interface_5G.vhd
+++ /dev/null
@@ -1,662 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net_gbe_components.all;
-use work.med_sync_define_RS.all;
-
-entity gbe_med_interface_5G is
-  generic (
-    DO_SIMULATION : integer range 0 to 1;
-    NUMBER_OF_GBE_LINKS : integer range 1 to 4;
-    LINKS_ACTIVE : std_logic_vector(3 downto 0)
-  );
-  port (
-    RESET                 : in  std_logic;
-    GSR_N                 : in  std_logic;
-    CLK_SYS_IN            : in  std_logic;
-    CLK_125_OUT           : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    CLK_125_IN            : in  std_logic;
-    CLK_125_RX_OUT        : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    
-    -- MAC status and config
-    MAC_READY_CONF_OUT    : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    MAC_RECONF_IN         : in  std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    MAC_AN_READY_OUT      : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    
-    -- MAC data interface
-    MAC_FIFOAVAIL_IN      : in  std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    MAC_FIFOEOF_IN        : in  std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    MAC_FIFOEMPTY_IN      : in  std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    MAC_RX_FIFOFULL_IN    : in  std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    
-    MAC_TX_DATA_IN        : in  std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
-    MAC_TX_READ_OUT       : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    MAC_TX_DISCRFRM_OUT   : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    MAC_TX_STAT_EN_OUT    : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    MAC_TX_STATS_OUT      : out std_logic_vector(NUMBER_OF_GBE_LINKS * 31 - 1 downto 0);
-    MAC_TX_DONE_OUT       : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-
-    MAC_RX_FIFO_ERR_OUT   : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    MAC_RX_STATS_OUT      : out std_logic_vector(NUMBER_OF_GBE_LINKS * 32 - 1 downto 0);
-    MAC_RX_DATA_OUT       : out std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
-    MAC_RX_WRITE_OUT      : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    MAC_RX_STAT_EN_OUT    : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    MAC_RX_EOF_OUT        : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    MAC_RX_ERROR_OUT      : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    
-    --SFP Connection
-    SD_RXD_P_IN           : in  std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    SD_RXD_N_IN           : in  std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    SD_TXD_P_OUT          : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    SD_TXD_N_OUT          : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    SD_PRSNT_N_IN         : in  std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-    SD_LOS_IN             : in  std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-    SD_TXDIS_OUT          : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP disable
-
-    DEBUG_OUT             : out std_logic_vector(255 downto 0)		
-  );
-end entity gbe_med_interface_5G;
-
-architecture RTL of gbe_med_interface_5G is
-  
-  component sgmii_gbe_core -- checked for ECP5-5G core 
-  port( 
-    rst_n                  : in  std_logic;
-    signal_detect          : in  std_logic;
-    gbe_mode               : in  std_logic;
-    sgmii_mode             : in  std_logic;
-    operational_rate       : in  std_logic_vector(1 downto 0);
-    debug_link_timer_short : in  std_logic;
-
-    force_isolate          : in  std_logic;
-    force_loopback         : in  std_logic;
-    force_unidir           : in  std_logic;
-
-    rx_compensation_err    : out std_logic;
-
-    ctc_drop_flag          : out std_logic;
-    ctc_add_flag           : out std_logic;
-    an_link_ok             : out std_logic;
-
-    tx_clk_125             : in  std_logic;                    
-    tx_clock_enable_source : out std_logic;
-    tx_clock_enable_sink   : in  std_logic;          
-    tx_d                   : in  std_logic_vector(7 downto 0); 
-    tx_en                  : in  std_logic;       
-    tx_er                  : in  std_logic;       
-    rx_clk_125             : in  std_logic; 
-    rx_clock_enable_source : out std_logic;
-    rx_clock_enable_sink   : in  std_logic;          
-    rx_d                   : out std_logic_vector(7 downto 0);       
-    rx_dv                  : out std_logic;  
-    rx_er                  : out std_logic; 
-    col                    : out std_logic;  
-    crs                    : out std_logic;  
-    tx_data                : out std_logic_vector(7 downto 0);  
-    tx_kcntl               : out std_logic; 
-    tx_disparity_cntl      : out std_logic; 
-
-    xmit_autoneg           : out std_logic;
-
-    serdes_recovered_clk   : in  std_logic; 
-    rx_data                : in  std_logic_vector(7 downto 0);  
-    rx_even                : in  std_logic;  
-    rx_kcntl               : in  std_logic; 
-    rx_disp_err            : in  std_logic; 
-    rx_cv_err              : in  std_logic; 
-    rx_err_decode_mode     : in  std_logic; 
-    mr_an_complete         : out std_logic; 
-    mr_page_rx             : out std_logic; 
-    mr_lp_adv_ability      : out std_logic_vector(15 downto 0); 
-    mr_main_reset          : in  std_logic; 
-    mr_an_enable           : in  std_logic; 
-    mr_restart_an          : in  std_logic; 
-    mr_adv_ability         : in  std_logic_vector(15 downto 0)  
-  );
-  end component;
-
-  component rate_resolution 
-  port (
-    gbe_mode               : in  std_logic;
-    sgmii_mode             : in  std_logic;
-    an_enable              : in  std_logic; 
-    advertised_rate        : in  std_logic_vector(1 downto 0);
-    link_partner_rate      : in  std_logic_vector(1 downto 0);
-    non_an_rate            : in  std_logic_vector(1 downto 0);
-    operational_rate       : out std_logic_vector(1 downto 0)  
-  );
-  end component;
-
-  component register_interface_hb port (
-    rst_n                  : in  std_logic;
-    hclk                   : in  std_logic;
-    gbe_mode               : in  std_logic;
-    sgmii_mode             : in  std_logic;
-    hcs_n                  : in  std_logic;
-    hwrite_n               : in  std_logic;
-    haddr                  : in  std_logic_vector(3 downto 0);
-    hdatain                : in  std_logic_vector(7 downto 0);
-    hdataout               : out std_logic_vector(7 downto 0);   
-    hready_n               : out std_logic;
-    mr_an_complete         : in  std_logic; 
-    mr_page_rx             : in  std_logic; 
-    mr_lp_adv_ability      : in  std_logic_vector(15 downto 0); 
-    mr_main_reset          : out std_logic; 
-    mr_an_enable           : out std_logic; 
-    mr_restart_an          : out std_logic; 
-    mr_adv_ability         : out std_logic_vector(15 downto 0) 
-  );
-  end component;
-
-  component tsmac_gbe -- checked for ECP5-5G core
-  port(
-    --------------- clock and reset port declarations ------------------
-    hclk            : in  std_logic;
-    txmac_clk       : in  std_logic;
-    rxmac_clk       : in  std_logic;
-    reset_n         : in  std_logic;
-    ------------------- Input signals to the GMII ----------------
-    rxd             : in  std_logic_vector(7 downto 0);
-    rx_dv           : in  std_logic;
-    rx_er           : in  std_logic;
-    -------------------- Input signals to the CPU I/F -------------------
-    haddr           : in  std_logic_vector(7 downto 0);
-    hdatain         : in  std_logic_vector(7 downto 0);
-    hcs_n           : in  std_logic;
-    hwrite_n        : in  std_logic;
-    hread_n         : in  std_logic;
-    ---------------- Input signals to the Tx MAC FIFO I/F ---------------
-    tx_fifodata     : in  std_logic_vector(7 downto 0);
-    tx_fifoavail    : in  std_logic;
-    tx_fifoeof      : in  std_logic;
-    tx_fifoempty    : in  std_logic;
-    tx_sndpaustim   : in  std_logic_vector(15 downto 0);
-    tx_sndpausreq   : in  std_logic;
-    tx_fifoctrl     : in  std_logic;
-    ---------------- Input signals to the Rx MAC FIFO I/F --------------- 
-    rx_fifo_full    : in  std_logic;
-    ignore_pkt      : in  std_logic;
-    -------------------- Output signals from the GMII -----------------------
-    txd             : out std_logic_vector(7 downto 0);  
-    tx_en           : out std_logic;
-    tx_er           : out std_logic;
-    -------------------- Output signals from the CPU I/F -------------------
-    hdataout        : out std_logic_vector(7 downto 0);
-    hdataout_en_n   : out std_logic;
-    hready_n        : out std_logic;
-    cpu_if_gbit_en  : out std_logic;
-    ---------------- Output signals from the Tx MAC FIFO I/F --------------- 
-    tx_macread      : out std_logic;
-    tx_discfrm      : out std_logic;
-    tx_staten       : out std_logic;
-    tx_done         : out std_logic;
-    tx_statvec      : out std_logic_vector(30 downto 0);
-    ---------------- Output signals from the Rx MAC FIFO I/F ---------------   
-    rx_fifo_error   : out std_logic;
-    rx_stat_vector  : out std_logic_vector(31 downto 0);
-    rx_dbout        : out std_logic_vector(7 downto 0);
-    rx_write        : out std_logic;
-    rx_stat_en      : out std_logic;
-    rx_eof          : out std_logic;
-    rx_error        : out std_logic
-  );
-  end component; 
-
-  signal sd_rx_clk                                : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal sd_tx_clk                                : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal sd_tx_kcntl_q, sd_tx_kcntl               : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal sd_tx_data_q, sd_tx_data                 : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
-  signal xmit                                     : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal sd_tx_correct_disp_q, sd_tx_correct_disp : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal sd_rx_data, sd_rx_data_q                 : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
---  signal sd_rx_data, sd_rx_data_q                 : std_logic_vector(7 downto 0);
-  signal sd_rx_kcntl, sd_rx_kcntl_q               : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal sd_rx_disp_error, sd_rx_disp_error_q     : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal sd_rx_cv_error, sd_rx_cv_error_q         : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal tx_power, rx_power                       : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal los, signal_detected                     : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal rx_clk_en                                : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal tx_clk_en                                : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal operational_rate                         : std_logic_vector(NUMBER_OF_GBE_LINKS * 2 - 1 downto 0);
-  signal an_complete                              : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal mr_page_rx                               : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal mr_lp_adv_ability                        : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0);
-  signal mr_main_reset                            : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal mr_restart_an                            : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal mr_adv_ability                           : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0);
-  signal mr_an_enable                             : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal pcs_rxd                                  : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
-  signal pcs_rx_en                                : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal pcs_rx_er                                : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal pcs_txd                                  : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
-  signal pcs_tx_en                                : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal pcs_tx_er                                : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal tsm_hdataout_en_n                        : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal tsm_hready_n                             : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal tsm_hread_n                              : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal tsm_hwrite_n                             : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal tsm_hcs_n                                : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal tsm_hdata                                : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
-  signal tsm_haddr                                : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
-  
-  signal synced_rst, ff : std_logic;
-  
-  signal fifo_eof_q, fifo_eof_qq, fifo_eof_qqq, fifo_eof_qqqq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-
-  signal link_rx_ready                            : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal rx_los_low                               : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal rx_cdr_lol                               : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal rst_dual                                 : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal rx_pcs_rst                               : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal rx_pcs_rst_q                             : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal rx_serdes_rst                            : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal rx_serdes_rst_q                          : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal tx_pcs_rst                               : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal link_tx_ready                            : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal pll_lol                                  : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-  signal init_dual                                : std_logic;
-  
-  signal debug                                    : std_logic_vector(255 downto 0);
-
-  signal delay_q : std_logic_vector(7 downto 0);
-  signal pulse   : std_logic;
-  signal pulse2  : std_logic;
-  
-begin
-  --------------------------------------------------------------------
-  --------------------------------------------------------------------
---  debug(255 downto 0) <= (others => '0');
-  DEBUG_OUT <= debug;
-  --------------------------------------------------------------------
-  --------------------------------------------------------------------
-
-  init_dual <= not GSR_N;
-  
-  rx_power <= "1111";
-  tx_power <= "1111";
-    
-  reset_sync : process(GSR_N, CLK_SYS_IN)
-  begin
-    if (GSR_N = '0') then
-      ff <= '0';
-      synced_rst <= '0';
-    elsif rising_edge(CLK_SYS_IN) then
-      ff <= '1';
-      synced_rst <= ff;
-    end if;
-  end process reset_sync;
-  
-  SD_TXDIS_OUT <= "0000";
-  
-  CLK_125_OUT    <= CLK_125_IN & CLK_125_IN & CLK_125_IN & CLK_125_IN;
-  CLK_125_RX_OUT <= sd_rx_clk;
-
-  impl_gen : if DO_SIMULATION = 0 generate
-    
-    pcs_gen : for i in 0 to NUMBER_OF_GBE_LINKS - 1 generate
-    
-      pcs_active_gen : if LINKS_ACTIVE(i) = '1' generate
-
-        gbe_serdes: entity serdes_gbe
-        port map(
-        -- external I/Os
-          hdinp             => SD_RXD_P_IN(i), 
-          hdinn             => SD_RXD_N_IN(i),
-          hdoutp            => SD_TXD_P_OUT(i),
-          hdoutn            => SD_TXD_N_OUT(i),
-        -- clocks
-          pll_refclki       => CLK_125_IN,
-          rxrefclk          => CLK_125_IN,
-          txi_clk           => CLK_125_IN, -- REALLY?
-          tx_pclk           => sd_tx_clk(i), -- not really needed?
-          rx_pclk           => sd_rx_clk(i), -- recovered RX clock
-        -- TX channel
-          txdata            => sd_tx_data_q( (i + 1) * 8 - 1 downto i * 8),
---          txdata            => sd_tx_data_q(7 downto 0),
-          tx_k              => sd_tx_kcntl_q(i downto i),
-          tx_disp_correct   => sd_tx_correct_disp_q(i downto i),
-          xmit              => xmit(i downto i),
-        -- RX channel
-          rxdata            => sd_rx_data( (i + 1) * 8 - 1 downto i * 8),
---          rxdata            => sd_rx_data(7 downto 0),
-          rx_k              => sd_rx_kcntl(i downto i),
-          rx_disp_err       => sd_rx_disp_error(i downto i),
-          rx_cv_err         => sd_rx_cv_error(i downto i),
-          lsm_status_s      => signal_detected(i),
-          signal_detect_c   => '1', -- enable internal LSM
-        -- Status signals
-          pll_lol           => pll_lol(i),
-          rx_cdr_lol_s      => rx_cdr_lol(i),
-          rx_los_low_s      => rx_los_low(i),
-        -- Power control
-          rx_pwrup_c        => rx_power(i),
-          tx_pwrup_c        => tx_power(i),
-          serdes_pdb        => '1', -- DUAL is powered up 
-        -- Resets
-          sli_rst           => '0', -- soft logic reset (?)
-          rst_dual_c        => rst_dual(i),
-          rx_pcs_rst_c      => rx_pcs_rst_q(i),
-          rx_serdes_rst_c   => rx_serdes_rst_q(i),
-          tx_pcs_rst_c      => tx_pcs_rst(i),
-          serdes_rst_dual_c => '0',
-          tx_serdes_rst_c   => '0'
-        );
-
-        rst_dual(i) <= init_dual;
-        
-        THE_MAIN_TX_RST: main_tx_reset_RS
-        port map (
-          CLEAR                => init_dual,
-          CLK_REF              => CLK_125_IN,
-          TX_PLL_LOL_IN        => pll_lol(i),
-          TX_CLOCK_AVAIL_IN    => '1', -- not needed here
-          TX_PCS_RST_CH_C_OUT  => tx_pcs_rst(i),
-          SYNC_TX_QUAD_OUT     => open,
-          LINK_TX_READY_OUT    => link_tx_ready(i),
-          STATE_OUT            => open
-        );
-                
-        THE_MAIN_RX_RST: main_rx_reset_RS 
-        port map(
-          CLEAR             => init_dual,
-          CLK_REF           => CLK_125_IN,
-          CDR_LOL_IN        => rx_cdr_lol(i),
-          CV_IN             => sd_rx_cv_error(i),
-          LSM_IN            => signal_detected(i),
-          LOS_IN            => rx_los_low(i),
-          WAP_ZERO_IN       => '1', -- not used here
-          -- outputs
-          WAP_REQ_OUT       => open, -- not used here
-          RX_SERDES_RST_OUT => rx_serdes_rst(i), -- CLK_REF based
-          RX_PCS_RST_OUT    => rx_pcs_rst(i), -- CLK_REF based
-          LINK_RX_READY_OUT => link_rx_ready(i), -- CLK_REF based
-          STATE_OUT         => open
-        );
-
-        -- reset signals for RX SerDes need to be sync'ed to real RX clock for ECP5
-        SYNC_RST_SIGS: entity work.signal_sync 
-        generic map( WIDTH => 2 )
-        port map(
-          RESET    => '0',
-          CLK0     => sd_rx_clk(i), 
-          CLK1     => sd_rx_clk(i),
-          D_IN(0)  => rx_pcs_rst(i),
-          D_IN(1)  => rx_serdes_rst(i),
-          D_OUT(0) => rx_pcs_rst_q(i),
-          D_OUT(1) => rx_serdes_rst_q(i)
-        );
-
-        debug(0)  <= init_dual;
-        debug(1)  <= pll_lol(i);
-        debug(2)  <= rx_cdr_lol(i);
-        debug(3)  <= rx_los_low(i);
-        debug(4)  <= sd_rx_cv_error(i);
-        debug(5)  <= signal_detected(i);
-        debug(6)  <= tx_pcs_rst(i);
-        debug(7)  <= rx_serdes_rst(i);
-        debug(8)  <= rx_pcs_rst(i);
-        debug(9)  <= link_rx_ready(i);
-        debug(10) <= link_tx_ready(i);
-        
-        -- one register between SGMII and SerDes
-        SYNC_TX_PROC : process(CLK_125_IN)
-        begin
-          if rising_edge(CLK_125_IN) then
-            sd_tx_data_q( (0 + 1) * 8 - 1 downto i * 8) <= sd_tx_data( (0 + 1) * 8 - 1 downto i * 8);
---            sd_tx_data_q(7 downto 0) <= sd_tx_data(7 downto 0);
-            sd_tx_kcntl_q(i)                            <= sd_tx_kcntl(i);
-            sd_tx_correct_disp_q(i)                     <= sd_tx_correct_disp(i);
-          end if;
-        end process SYNC_TX_PROC;
-
-        -- one register between SerDes and SGMII
-        SYNC_RX_PROC : process(sd_rx_clk(i))
-        begin
-          if rising_edge(sd_rx_clk(i)) then
-            sd_rx_data_q( (0 + 1) * 8 - 1 downto i * 8) <= sd_rx_data( (0 + 1) * 8 - 1 downto i * 8);
---            sd_rx_data_q(7 downto 0) <= sd_rx_data(7 downto 0);
-            sd_rx_kcntl_q(i)                            <= sd_rx_kcntl(i);
-            sd_rx_disp_error_q(i)                       <= sd_rx_disp_error(i);
-            sd_rx_cv_error_q(i)                         <= sd_rx_cv_error(i);
-          end if;
-        end process SYNC_RX_PROC;	
-        
-        -- SGMII core
-        SGMII_GBE_PCS : sgmii_gbe_core
-        port map(
-          rst_n                   => synced_rst,
-          signal_detect           => link_rx_ready(i), --signal_detected(i),
-          gbe_mode                => '1',
-          sgmii_mode              => '0',
-          operational_rate        => operational_rate( (i + 1) * 2 - 1 downto (i * 2)),
-          debug_link_timer_short  => '0',
-          force_isolate           => '0',
-          force_loopback          => '0',
-          force_unidir            => '0',
-          rx_compensation_err     => open,
-          ctc_drop_flag           => open,
-          ctc_add_flag            => open,
-          an_link_ok              => open,
-        -- MAC interface
-          tx_clk_125              => CLK_125_IN, -- was sd_tx_clk(i)
-          tx_clock_enable_source  => tx_clk_en(i),
-          tx_clock_enable_sink    => tx_clk_en(i),
-          tx_d                    => pcs_txd( (i + 1) * 8 - 1 downto i * 8), -- TX data from MAC
-          tx_en                   => pcs_tx_en(i), -- TX data enable from MAC
-          tx_er                   => pcs_tx_er(i), -- TX error from MAC
-          rx_clk_125              => CLK_125_IN, -- was sd_rx_clk(i)
-          rx_clock_enable_source  => rx_clk_en(i),
-          rx_clock_enable_sink    => rx_clk_en(i),
-          rx_d                    => pcs_rxd( (i + 1) * 8 - 1 downto i * 8), -- RX data to MAC
-          rx_dv                   => pcs_rx_en(i), -- RX data enable to MAC
-          rx_er                   => pcs_rx_er(i), -- RX error to MAC
-          col                     => open,
-          crs                     => open,
-          -- SerDes interface
-          tx_data                 => sd_tx_data( (i + 1) * 8 - 1 downto i * 8), -- TX data to SerDes
---          tx_data                 => sd_tx_data(7 downto 0), -- TX data to SerDes
-          tx_kcntl                => sd_tx_kcntl(i), -- TX komma control to SerDes
-          tx_disparity_cntl       => sd_tx_correct_disp(i), -- idle parity state control in IPG (to SerDes)
-          xmit_autoneg            => xmit(i),
-          serdes_recovered_clk    => sd_rx_clk(i), -- 125MHz recovered from receive bit stream
-          rx_data                 => sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8), -- RX data from SerDes
---          rx_data                 => sd_rx_data_q(7 downto 0), -- RX data from SerDes
-          rx_kcntl                => sd_rx_kcntl_q(i), -- RX komma control from SerDes
-          rx_err_decode_mode      => '0', -- receive error control mode fixed to normal
-          rx_even                 => '0', -- unused (receive error control mode = normal, tie to GND)
-          rx_disp_err             => sd_rx_disp_error_q(i), -- RX disparity error from SerDes
-          rx_cv_err               => sd_rx_cv_error_q(i), -- RX code violation error from SerDes
-          -- Autonegotiation stuff
-          mr_an_complete          => an_complete(i),
-          mr_page_rx              => mr_page_rx(i),
-          mr_lp_adv_ability       => mr_lp_adv_ability( (i + 1) * 16 - 1 downto i * 16),
-          mr_main_reset           => mr_main_reset(i),
-          mr_an_enable            => mr_an_enable(i), --'1',
-          mr_restart_an           => mr_restart_an(i),
-          mr_adv_ability          => mr_adv_ability( (i + 1) * 16 - 1 downto i * 16)
-        );
-                
-        MAC_AN_READY_OUT(i) <= an_complete(i);
-        
-        debug(11)           <= sd_rx_kcntl_q(i);
-        debug(19 downto 12) <= sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8);
-
-        debug(20)           <= sd_tx_kcntl_q(i);
-        debug(28 downto 21) <= sd_tx_data_q( (i + 1) * 8 - 1 downto i * 8);
-
-        debug(29) <= xmit(i);
-        debug(30) <= mr_main_reset(i);
-        debug(31) <= mr_restart_an(i);
-        debug(32) <= mr_page_rx(i);
-        debug(33) <= an_complete(i);
-        
-        u0_rate_resolution : rate_resolution port map(
-          gbe_mode          => '1',
-          sgmii_mode        => '0',
-          an_enable         => mr_an_enable(i), --'1',
-          advertised_rate   => mr_adv_ability(i * 16 + 11 downto i * 16 + 10),
-          link_partner_rate => mr_lp_adv_ability(i * 16 + 11 downto i * 16 + 10),
-          non_an_rate       => "10", -- 1Gbps is rate when auto-negotiation disabled
-          operational_rate  => operational_rate( (i + 1) * 2 - 1 downto i * 2)
-        );
-
-      --- SIMPLE ---
-        mr_main_reset(i) <= init_dual;
-        mr_restart_an(i) <= pulse;
-        mr_an_enable(i)  <= link_rx_ready(i);
-
-        mr_adv_ability( (i + 1 ) * 16 - 1 downto i * 16) <= x"0020";
-
-        SYNC_PROC: process( sd_tx_clk(i) ) 
-        begin
-          if( rising_edge(sd_tx_clk(i)) ) then
-            delay_q <= delay_q(6 downto 0) & link_rx_ready(i);
-          end if;
-        end process SYNC_PROC;
-
-        pulse  <= not delay_q(5) and delay_q(4);
-        pulse2 <= not delay_q(7) and delay_q(6);
-      --- /SIMPLE ---
-
---        u0_ri : register_interface_hb port map(
---          -- Control Signals
---          rst_n             => synced_rst,
---          hclk              => CLK_125_IN,
---          gbe_mode          => '1',
---          sgmii_mode        => '0',
---          -- Host Bus
---          hcs_n             => '1',
---          hwrite_n          => '1',
---          haddr             => (others => '0'),
---          hdatain           => (others => '0'),
---          hdataout          => open,
---          hready_n          => open,
---          -- Register Outputs
---          mr_an_enable      => mr_an_enable(i),
---          mr_restart_an     => mr_restart_an(i),
---          mr_main_reset     => mr_main_reset(i),
---          mr_adv_ability    => mr_adv_ability( (i + 1 ) * 16 - 1 downto i * 16),
---          -- Register Inputs
---          mr_an_complete    => an_complete(i),
---          mr_page_rx        => mr_page_rx(i),
---          mr_lp_adv_ability => mr_lp_adv_ability( (i + 1 ) * 16 - 1 downto i * 16)
---        );
-        
-        MAC: tsmac_gbe
-        port map(
-        ----------------- clock and reset port declarations ------------------
-          hclk            => CLK_SYS_IN,
-          txmac_clk       => sd_tx_clk(i),
-          rxmac_clk       => sd_rx_clk(i),
-          reset_n         => GSR_N,
-        ------------------- Input signals to the GMII ----------------
-          rxd             => pcs_rxd( (i + 1) * 8 - 1 downto i * 8),
-          rx_dv           => pcs_rx_en(i),
-          rx_er           => pcs_rx_er(i),
-        -------------------- Input signals to the CPU I/F -------------------
-          haddr           => tsm_haddr( (i + 1) * 8 - 1 downto i * 8),
-          hdatain         => tsm_hdata( (i + 1) * 8 - 1 downto i * 8),
-          hcs_n           => tsm_hcs_n(i),
-          hwrite_n        => tsm_hwrite_n(i),
-          hread_n         => tsm_hread_n(i),
-        ---------------- Input signals to the Tx MAC FIFO I/F ---------------
-          tx_fifodata     => MAC_TX_DATA_IN( (i + 1) * 8 - 1 downto i * 8),
-          tx_fifoavail    => MAC_FIFOAVAIL_IN(i),
-          tx_fifoeof      => MAC_FIFOEOF_IN(i),
-          tx_fifoempty    => MAC_FIFOEMPTY_IN(i),
-          tx_sndpaustim   => x"0000",
-          tx_sndpausreq   => '0',
-          tx_fifoctrl     => '0',  -- always data frame
-        ---------------- Input signals to the Rx MAC FIFO I/F --------------- 
-          rx_fifo_full    => MAC_RX_FIFOFULL_IN(i), --'0',
-          ignore_pkt      => '0',
-        ---------------- Output signals from the GMII -----------------------
-          txd             => pcs_txd( (i + 1) * 8 - 1 downto i * 8),
-          tx_en           => pcs_tx_en(i),
-          tx_er           => pcs_tx_er(i),
-        ----------------- Output signals from the CPU I/F -------------------
-          hdataout        => open,
-          hdataout_en_n   => tsm_hdataout_en_n(i),
-          hready_n        => tsm_hready_n(i),
-          cpu_if_gbit_en  => open,
-        ------------- Output signals from the Tx MAC FIFO I/F --------------- 
-          tx_macread      => MAC_TX_READ_OUT(i),
-          tx_discfrm      => MAC_TX_DISCRFRM_OUT(i),
-          tx_staten       => MAC_TX_STAT_EN_OUT(i),
-          tx_statvec      => MAC_TX_STATS_OUT( (i + 1) * 31 - 1 downto i * 31),
-          tx_done         => MAC_TX_DONE_OUT(i),
-        ------------- Output signals from the Rx MAC FIFO I/F ---------------   
-          rx_fifo_error   => MAC_RX_FIFO_ERR_OUT(i),
-          rx_stat_vector  => MAC_RX_STATS_OUT( (i + 1) * 32 - 1 downto i * 32),
-          rx_dbout        => MAC_RX_DATA_OUT( (i + 1) * 8 - 1 downto i * 8),
-          rx_write        => MAC_RX_WRITE_OUT(i),
-          rx_stat_en      => MAC_RX_STAT_EN_OUT(i),
-          rx_eof          => MAC_RX_EOF_OUT(i),
-          rx_error        => MAC_RX_ERROR_OUT(i)
-        );
-        
-        TSMAC_CONTROLLER : trb_net16_gbe_mac_control
-        port map(
-          CLK                 => CLK_SYS_IN,
-          RESET               => RESET, 
-        -- signals to/from main controller
-          MC_TSMAC_READY_OUT  => MAC_READY_CONF_OUT(i),
-          MC_RECONF_IN        => MAC_RECONF_IN(i),
-          MC_GBE_EN_IN        => '1',
-          MC_RX_DISCARD_FCS   => '0',
-          MC_PROMISC_IN       => '1',
-          MC_MAC_ADDR_IN      => (others => '0'),
-        -- signal to/from Host interface of TriSpeed MAC
-          TSM_HADDR_OUT       => tsm_haddr( (i + 1) * 8 - 1 downto i * 8),
-          TSM_HDATA_OUT       => tsm_hdata( (i + 1) * 8 - 1 downto i * 8),
-          TSM_HCS_N_OUT       => tsm_hcs_n(i),
-          TSM_HWRITE_N_OUT    => tsm_hwrite_n(i),
-          TSM_HREAD_N_OUT     => tsm_hread_n(i),
-          TSM_HREADY_N_IN     => tsm_hready_n(i),
-          TSM_HDATA_EN_N_IN => tsm_hdataout_en_n(i),
-        -- Debug
-          DEBUG_OUT           => open
-        );
-                
-      end generate pcs_active_gen;
-      
-    end generate pcs_gen;
-    
-  end generate impl_gen;
-
-  sim_gen : if DO_SIMULATION =  1 generate
-    
-    process
-    begin
-      
-      MAC_AN_READY_OUT <= (others => '0');
-      wait for 2 us;
-      MAC_AN_READY_OUT <= (others => '1');
-      
-      wait;
-    end process;
-    
-    process(CLK_125_IN)
-    begin
-      if rising_edge(CLK_125_IN) then
-        MAC_TX_READ_OUT <= MAC_FIFOAVAIL_IN;
-        
-        fifo_eof_q <= MAC_FIFOEOF_IN;
-        fifo_eof_qq <= fifo_eof_q;
-        fifo_eof_qqq <= fifo_eof_qq;
-        fifo_eof_qqqq <= fifo_eof_qqq;
-        
-        MAC_TX_DONE_OUT <= fifo_eof_qqqq; -- MAC_FIFOEOF_IN;
-      end if;
-    end process;
-    
-    
-  end generate sim_gen;
-  
-
-end architecture RTL;
diff --git a/gbe_trb/base/gbe_med_interface_single_5G.vhd b/gbe_trb/base/gbe_med_interface_single_5G.vhd
index 513968c..8587614 100644
--- a/gbe_trb/base/gbe_med_interface_single_5G.vhd
+++ b/gbe_trb/base/gbe_med_interface_single_5G.vhd
@@ -113,39 +113,6 @@ architecture RTL of gbe_med_interface_single_5G is
   );
   end component;
 
-  component rate_resolution 
-  port (
-    gbe_mode               : in  std_logic;
-    sgmii_mode             : in  std_logic;
-    an_enable              : in  std_logic; 
-    advertised_rate        : in  std_logic_vector(1 downto 0);
-    link_partner_rate      : in  std_logic_vector(1 downto 0);
-    non_an_rate            : in  std_logic_vector(1 downto 0);
-    operational_rate       : out std_logic_vector(1 downto 0)  
-  );
-  end component;
-
-  component register_interface_hb port (
-    rst_n                  : in  std_logic;
-    hclk                   : in  std_logic;
-    gbe_mode               : in  std_logic;
-    sgmii_mode             : in  std_logic;
-    hcs_n                  : in  std_logic;
-    hwrite_n               : in  std_logic;
-    haddr                  : in  std_logic_vector(3 downto 0);
-    hdatain                : in  std_logic_vector(7 downto 0);
-    hdataout               : out std_logic_vector(7 downto 0);   
-    hready_n               : out std_logic;
-    mr_an_complete         : in  std_logic; 
-    mr_page_rx             : in  std_logic; 
-    mr_lp_adv_ability      : in  std_logic_vector(15 downto 0); 
-    mr_main_reset          : out std_logic; 
-    mr_an_enable           : out std_logic; 
-    mr_restart_an          : out std_logic; 
-    mr_adv_ability         : out std_logic_vector(15 downto 0) 
-  );
-  end component;
-
   component tsmac_gbe -- checked for ECP5-5G core
   port(
     --------------- clock and reset port declarations ------------------
@@ -381,14 +348,14 @@ begin
   );
 
   -- Status signals
-  STATUS_OUT(0) <= link_tx_ready; -- SerDes TX channel operational
-  STATUS_OUT(1) <= link_rx_ready; -- SerDes Rx channel operational
-  STATUS_OUT(2) <= an_complete;   -- GbE Autonegotiation completed
-  STATUS_OUT(3) <= pcs_tx_en;     -- SerDes TX activity
-  STATUS_OUT(4) <= pcs_rx_en;     -- SerDes RX activity
-  STATUS_OUT(5) <= '0';
-  STATUS_OUT(6) <= '0';
   STATUS_OUT(7) <= '0';
+  STATUS_OUT(6) <= '0';
+  STATUS_OUT(5) <= '0';
+  STATUS_OUT(4) <= pcs_rx_en;     -- SerDes RX activity
+  STATUS_OUT(3) <= pcs_tx_en;     -- SerDes TX activity
+  STATUS_OUT(2) <= an_complete;   -- GbE Autonegotiation completed
+  STATUS_OUT(1) <= link_rx_ready; -- SerDes Rx channel operational
+  STATUS_OUT(0) <= link_tx_ready; -- SerDes TX channel operational
   
 --  -- "Good" debugging pins
 --  debug(7 downto 0)  <= sd_tx_data;
@@ -474,17 +441,6 @@ begin
   operational_rate <= b"10";
 --- /SIMPLE ---
 
---  -- basically, not needed in GbE!
---  u0_rate_resolution : rate_resolution port map(
---    gbe_mode          => '1',
---    sgmii_mode        => '0',
---    an_enable         => '1', -- not used inside if gbe_mode is active
---    advertised_rate   => mr_adv_ability(11 downto 10),
---    link_partner_rate => mr_lp_adv_ability(11 downto 10),
---    non_an_rate       => "10", -- 1Gbps is rate when auto-negotiation disabled
---    operational_rate  => operational_rate
---  );
-
 --- SIMPLE ---
   mr_main_reset <= rst_dual;
   mr_restart_an <= pulse;
@@ -501,30 +457,6 @@ begin
   pulse  <= not delay_q(7) and delay_q(6);
 --- /SIMPLE ---
 
---  u0_ri : register_interface_hb port map(
---    -- Control Signals
---    rst_n             => synced_rst,
---    hclk              => CLK_125_IN,
---    gbe_mode          => '1',
---    sgmii_mode        => '0',
---    -- Host Bus
---    hcs_n             => '1',
---    hwrite_n          => '1',
---    haddr             => (others => '0'),
---    hdatain           => (others => '0'),
---    hdataout          => open,
---    hready_n          => open,
---    -- Register Outputs
---    mr_an_enable      => mr_an_enable,
---    mr_restart_an     => mr_restart_an,
---    mr_main_reset     => mr_main_reset,
---    mr_adv_ability    => mr_adv_ability,
---    -- Register Inputs
---    mr_an_complete    => an_complete,
---    mr_page_rx        => mr_page_rx,
---    mr_lp_adv_ability => mr_lp_adv_ability
---  );
-
   -- "Good" debugging pins
   debug(7 downto 0)  <= pcs_txd;
   debug(15 downto 8) <= pcs_rxd;
diff --git a/gbe_trb/base/gbe_wrapper_single_5G.vhd b/gbe_trb/base/gbe_wrapper_single_5G.vhd
index 4ed9791..29608f5 100644
--- a/gbe_trb/base/gbe_wrapper_single_5G.vhd
+++ b/gbe_trb/base/gbe_wrapper_single_5G.vhd
@@ -51,8 +51,7 @@ entity gbe_wrapper_single_5G is
     CTS_NUMBER_IN            : in  std_logic_vector(15 downto 0);
     CTS_CODE_IN              : in  std_logic_vector(7 downto 0);
     CTS_INFORMATION_IN       : in  std_logic_vector(7 downto 0);
-    CTS_READOUT_TYPE_IN      : in  std_logic_vector(3 down: in  std_logic_vector(7 downto 0) := (others => '0');
-      to 0);
+    CTS_READOUT_TYPE_IN      : in  std_logic_vector(3 downto 0);
     CTS_START_READOUT_IN     : in  std_logic;
     CTS_DATA_OUT             : out std_logic_vector(31 downto 0);
     CTS_DATAREADY_OUT        : out std_logic;
@@ -126,9 +125,6 @@ architecture RTL of gbe_wrapper_single_5G is
   signal mac_rx_eof                 : std_logic;
   signal mac_rx_err                 : std_logic;
 
---  signal clk_125_from_pcs           : std_logic; -- not needed
---  signal clk_125_rx_from_pcs        : std_logic; -- not needed
-
   signal cfg_gbe_enable             : std_logic;
   signal cfg_ipu_enable             : std_logic;
   signal cfg_mult_enable            : std_logic;
@@ -255,9 +251,9 @@ begin
     RESET               => RESET,
     GSR_N               => GSR_N,
     CLK_SYS_IN          => CLK_SYS_IN,
-    CLK_125_OUT         => open, --clk_125_from_pcs, -- not needed
+    CLK_125_OUT         => open, -- not needed
     CLK_125_IN          => CLK_125_IN,
-    CLK_125_RX_OUT      => open, --clk_125_rx_from_pcs, -- not needed
+    CLK_125_RX_OUT      => open, -- not needed
     MAC_READY_CONF_OUT  => mac_ready_conf,
     MAC_RECONF_IN       => mac_reconf,
     MAC_AN_READY_OUT    => mac_an_ready,
@@ -289,7 +285,8 @@ begin
     DEBUG_OUT           => debug(63 downto 0) --open
   );
 
-  STATUS_OUT(15 downto 8) <= (others => '0');
+  STATUS_OUT(8)           <= dhcp_done; -- DHCP has completed
+  STATUS_OUT(15 downto 9) <= (others => '0');
   
   gbe_inst : entity work.gbe_logic_wrapper
   generic map(DO_SIMULATION           => DO_SIMULATION,
@@ -315,7 +312,7 @@ begin
   port map(
     CLK_SYS_IN               => CLK_SYS_IN,
     CLK_125_IN               => CLK_125_IN,
-    CLK_RX_125_IN            => CLK_125_IN, --clk_125_rx_from_pcs,
+    CLK_RX_125_IN            => CLK_125_IN,
     RESET                    => RESET,
     GSR_N                    => GSR_N,
     MY_MAC_IN                => mac_0,
@@ -643,18 +640,18 @@ begin
     MONITOR_TX_FRAMES_IN         => sum_tx_frames,
     MONITOR_TX_PACKETS_IN        => sum_tx_packets,
     MONITOR_DROPPED_IN           => sum_dropped,
-    MONITOR_SELECT_REC_IN        => (others => '0'), --dbg_select_rec,
-    MONITOR_SELECT_REC_BYTES_IN  => (others => '0'), --dbg_select_rec_bytes,
-    MONITOR_SELECT_SENT_BYTES_IN => (others => '0'), --dbg_select_sent_bytes,
-    MONITOR_SELECT_SENT_IN       => (others => '0'), --dbg_select_sent,
-    MONITOR_SELECT_DROP_IN_IN    => (others => '0'), --dbg_select_drop_in,
-    MONITOR_SELECT_DROP_OUT_IN   => (others => '0'), --dbg_select_drop_out,
-    MONITOR_SELECT_GEN_DBG_IN    => monitor_gen_dbg, --dbg_select_gen,
+    MONITOR_SELECT_REC_IN        => (others => '0'),
+    MONITOR_SELECT_REC_BYTES_IN  => (others => '0'),
+    MONITOR_SELECT_SENT_BYTES_IN => (others => '0'),
+    MONITOR_SELECT_SENT_IN       => (others => '0'),
+    MONITOR_SELECT_DROP_IN_IN    => (others => '0'),
+    MONITOR_SELECT_DROP_OUT_IN   => (others => '0'),
+    MONITOR_SELECT_GEN_DBG_IN    => monitor_gen_dbg,
     MONITOR_IP_IN                => my_ip,
     DUMMY_EVENT_SIZE_OUT         => dummy_event,
     DUMMY_TRIGGERED_MODE_OUT     => dummy_mode,
-    DATA_HIST_IN                 => (others => (others => '0')), --dbg_hist,
-    SCTRL_HIST_IN                => (others => (others => '0')) --dbg_hist2
+    DATA_HIST_IN                 => (others => (others => '0')),
+    SCTRL_HIST_IN                => (others => (others => '0'))
   );
 
   NOSCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL = "0000") generate
diff --git a/gbe_trb_ecp5/base/gbe_med_interface_single.vhd b/gbe_trb_ecp5/base/gbe_med_interface_single.vhd
new file mode 100644
index 0000000..22c579e
--- /dev/null
+++ b/gbe_trb_ecp5/base/gbe_med_interface_single.vhd
@@ -0,0 +1,559 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net_gbe_components.all;
+use work.med_sync_define_RS.all;
+
+entity gbe_med_interface_single is
+  port (
+    RESET                 : in  std_logic;
+    GSR_N                 : in  std_logic;
+    CLK_SYS_IN            : in  std_logic;
+    CLK_125_OUT           : out std_logic;
+    CLK_125_IN            : in  std_logic;
+    CLK_125_RX_OUT        : out std_logic;
+    -- MAC status and config
+    MAC_READY_CONF_OUT    : out std_logic;
+    MAC_RECONF_IN         : in  std_logic;
+    MAC_AN_READY_OUT      : out std_logic;
+    -- MAC data interface
+    MAC_FIFOAVAIL_IN      : in  std_logic;
+    MAC_FIFOEOF_IN        : in  std_logic;
+    MAC_FIFOEMPTY_IN      : in  std_logic;
+    MAC_RX_FIFOFULL_IN    : in  std_logic;
+    -- MAC TX interface
+    MAC_TX_DATA_IN        : in  std_logic_vector(7 downto 0);
+    MAC_TX_READ_OUT       : out std_logic;
+    MAC_TX_DISCRFRM_OUT   : out std_logic;
+    MAC_TX_STAT_EN_OUT    : out std_logic;
+    MAC_TX_STATS_OUT      : out std_logic_vector(30 downto 0);
+    MAC_TX_DONE_OUT       : out std_logic;
+    -- MAC RX interface
+    MAC_RX_FIFO_ERR_OUT   : out std_logic;
+    MAC_RX_STATS_OUT      : out std_logic_vector(31 downto 0);
+    MAC_RX_DATA_OUT       : out std_logic_vector(7 downto 0);
+    MAC_RX_WRITE_OUT      : out std_logic;
+    MAC_RX_STAT_EN_OUT    : out std_logic;
+    MAC_RX_EOF_OUT        : out std_logic;
+    MAC_RX_ERROR_OUT      : out std_logic;
+    --SFP Connection
+    SD_RXD_P_IN           : in  std_logic;
+    SD_RXD_N_IN           : in  std_logic;
+    SD_TXD_P_OUT          : out std_logic;
+    SD_TXD_N_OUT          : out std_logic;
+    SD_PRSNT_N_IN         : in  std_logic;
+    SD_LOS_IN             : in  std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SD_TXDIS_OUT          : out std_logic; -- SFP disable
+    STATUS_OUT            : out std_logic_vector(7 downto 0);
+    -- Debug
+    DEBUG_OUT             : out std_logic_vector(63 downto 0)		
+  );
+end entity gbe_med_interface_single;
+
+architecture RTL of gbe_med_interface_single is
+  
+  component sgmii_gbe_core -- checked for ECP5-5G core 
+  port( 
+    rst_n                  : in  std_logic;
+    signal_detect          : in  std_logic;
+    gbe_mode               : in  std_logic;
+    sgmii_mode             : in  std_logic;
+    operational_rate       : in  std_logic_vector(1 downto 0);
+    debug_link_timer_short : in  std_logic;
+
+    force_isolate          : in  std_logic;
+    force_loopback         : in  std_logic;
+    force_unidir           : in  std_logic;
+
+    rx_compensation_err    : out std_logic;
+
+    ctc_drop_flag          : out std_logic;
+    ctc_add_flag           : out std_logic;
+    an_link_ok             : out std_logic;
+
+    tx_clk_125             : in  std_logic;                    
+    tx_clock_enable_source : out std_logic;
+    tx_clock_enable_sink   : in  std_logic;          
+    tx_d                   : in  std_logic_vector(7 downto 0); 
+    tx_en                  : in  std_logic;       
+    tx_er                  : in  std_logic;       
+    rx_clk_125             : in  std_logic; 
+    rx_clock_enable_source : out std_logic;
+    rx_clock_enable_sink   : in  std_logic;          
+    rx_d                   : out std_logic_vector(7 downto 0);       
+    rx_dv                  : out std_logic;  
+    rx_er                  : out std_logic; 
+    col                    : out std_logic;  
+    crs                    : out std_logic;  
+    tx_data                : out std_logic_vector(7 downto 0);  
+    tx_kcntl               : out std_logic; 
+    tx_disparity_cntl      : out std_logic; 
+
+    xmit_autoneg           : out std_logic;
+
+    serdes_recovered_clk   : in  std_logic; 
+    rx_data                : in  std_logic_vector(7 downto 0);  
+    rx_even                : in  std_logic;  
+    rx_kcntl               : in  std_logic; 
+    rx_disp_err            : in  std_logic; 
+    rx_cv_err              : in  std_logic; 
+    rx_err_decode_mode     : in  std_logic; 
+    mr_an_complete         : out std_logic; 
+    mr_page_rx             : out std_logic; 
+    mr_lp_adv_ability      : out std_logic_vector(15 downto 0); 
+    mr_main_reset          : in  std_logic; 
+    mr_an_enable           : in  std_logic; 
+    mr_restart_an          : in  std_logic; 
+    mr_adv_ability         : in  std_logic_vector(15 downto 0)  
+  );
+  end component;
+
+  component tsmac_gbe -- checked for ECP5-5G core
+  port(
+    --------------- clock and reset port declarations ------------------
+    hclk            : in  std_logic;
+    txmac_clk       : in  std_logic;
+    rxmac_clk       : in  std_logic;
+    reset_n         : in  std_logic;
+    ------------------- Input signals to the GMII ----------------
+    rxd             : in  std_logic_vector(7 downto 0);
+    rx_dv           : in  std_logic;
+    rx_er           : in  std_logic;
+    -------------------- Input signals to the CPU I/F -------------------
+    haddr           : in  std_logic_vector(7 downto 0);
+    hdatain         : in  std_logic_vector(7 downto 0);
+    hcs_n           : in  std_logic;
+    hwrite_n        : in  std_logic;
+    hread_n         : in  std_logic;
+    ---------------- Input signals to the Tx MAC FIFO I/F ---------------
+    tx_fifodata     : in  std_logic_vector(7 downto 0);
+    tx_fifoavail    : in  std_logic;
+    tx_fifoeof      : in  std_logic;
+    tx_fifoempty    : in  std_logic;
+    tx_sndpaustim   : in  std_logic_vector(15 downto 0);
+    tx_sndpausreq   : in  std_logic;
+    tx_fifoctrl     : in  std_logic;
+    ---------------- Input signals to the Rx MAC FIFO I/F --------------- 
+    rx_fifo_full    : in  std_logic;
+    ignore_pkt      : in  std_logic;
+    -------------------- Output signals from the GMII -----------------------
+    txd             : out std_logic_vector(7 downto 0);  
+    tx_en           : out std_logic;
+    tx_er           : out std_logic;
+    -------------------- Output signals from the CPU I/F -------------------
+    hdataout        : out std_logic_vector(7 downto 0);
+    hdataout_en_n   : out std_logic;
+    hready_n        : out std_logic;
+    cpu_if_gbit_en  : out std_logic;
+    ---------------- Output signals from the Tx MAC FIFO I/F --------------- 
+    tx_macread      : out std_logic;
+    tx_discfrm      : out std_logic;
+    tx_staten       : out std_logic;
+    tx_done         : out std_logic;
+    tx_statvec      : out std_logic_vector(30 downto 0);
+    ---------------- Output signals from the Rx MAC FIFO I/F ---------------   
+    rx_fifo_error   : out std_logic;
+    rx_stat_vector  : out std_logic_vector(31 downto 0);
+    rx_dbout        : out std_logic_vector(7 downto 0);
+    rx_write        : out std_logic;
+    rx_stat_en      : out std_logic;
+    rx_eof          : out std_logic;
+    rx_error        : out std_logic
+  );
+  end component; 
+
+  signal sd_rx_clk                                : std_logic;
+  signal sd_tx_kcntl                              : std_logic_vector(0 downto 0);
+  signal sd_tx_data                               : std_logic_vector(7 downto 0);
+  signal xmit                                     : std_logic_vector(0 downto 0);
+  signal sd_tx_correct_disp                       : std_logic_vector(0 downto 0);
+  signal sd_rx_data                               : std_logic_vector(7 downto 0);
+  signal sd_rx_kcntl                              : std_logic_vector(0 downto 0);
+  signal sd_rx_disp_error                         : std_logic_vector(0 downto 0);
+  signal sd_rx_cv_error                           : std_logic_vector(0 downto 0); 
+  signal lsm_status                               : std_logic;
+  signal rx_clk_en                                : std_logic;
+  signal tx_clk_en                                : std_logic;
+  signal operational_rate                         : std_logic_vector(1 downto 0);
+  signal an_complete                              : std_logic;
+  signal mr_page_rx                               : std_logic;
+  signal mr_lp_adv_ability                        : std_logic_vector(15 downto 0);
+  signal mr_main_reset                            : std_logic;
+  signal mr_restart_an                            : std_logic;
+  signal mr_adv_ability                           : std_logic_vector(15 downto 0);
+  signal mr_an_enable                             : std_logic;
+  signal an_link_ok                               : std_logic;
+  signal pcs_rxd                                  : std_logic_vector(7 downto 0);
+  signal pcs_rx_en                                : std_logic;
+  signal pcs_rx_er                                : std_logic;
+  signal pcs_txd                                  : std_logic_vector(7 downto 0);
+  signal pcs_tx_en                                : std_logic;
+  signal pcs_tx_er                                : std_logic;
+  signal tsm_hdataout_en_n                        : std_logic;
+  signal tsm_hready_n                             : std_logic;
+  signal tsm_hread_n                              : std_logic;
+  signal tsm_hwrite_n                             : std_logic;
+  signal tsm_hcs_n                                : std_logic;
+  signal tsm_hdata                                : std_logic_vector(7 downto 0);
+  signal tsm_haddr                                : std_logic_vector(7 downto 0);
+  
+  signal synced_rst                               : std_logic;
+  
+  signal fifo_eof_q, fifo_eof_qq, fifo_eof_qqq, fifo_eof_qqqq : std_logic;
+
+  signal link_rx_ready                            : std_logic;
+  signal rx_los_low                               : std_logic;
+  signal rx_cdr_lol                               : std_logic;
+  signal rst_dual                                 : std_logic;
+  signal rx_pcs_rst                               : std_logic;
+  signal rx_pcs_rst_q                             : std_logic;
+  signal rx_serdes_rst                            : std_logic;
+  signal rx_serdes_rst_q                          : std_logic;
+  signal tx_pcs_rst                               : std_logic;
+  signal link_tx_ready                            : std_logic;
+  signal pll_lol                                  : std_logic;
+  
+  signal debug                                    : std_logic_vector(63 downto 0);
+
+  -- for replacing register interface
+  signal delay_q                                  : std_logic_vector(7 downto 0);
+  signal pulse                                    : std_logic;
+
+begin
+
+  -- We allow only one GbE in ECP5 for now
+  assert not (LINKS_ACTIVE = b"0000") report "Error: no GbE interface selected" severity error;
+  
+  --------------------------------------------------------------------
+  --------------------------------------------------------------------
+  DEBUG_OUT <= debug;  
+  -- debug(19..0) are on INTCOM
+  -- debug(33..20) are on GPIO
+  -- 33 = CLK2 (white/green)
+  -- 32 = CLK1 (white/blue)
+  --------------------------------------------------------------------
+  --------------------------------------------------------------------
+  
+--  reset_sync: process( CLK_125_IN )
+--  begin
+--  if( rising_edge(CLK_125_IN) ) then
+    synced_rst <= GSR_N;
+--  end if;
+--  end process reset_sync;
+  rst_dual <= not GSR_N;
+  
+  SD_TXDIS_OUT <= '0';
+  
+  CLK_125_OUT    <= CLK_125_IN;
+  CLK_125_RX_OUT <= sd_rx_clk;
+
+  -- Some notes on clocks: the SerDes uses TX and RX bridge FIFO, with RX FIFO being clocked on
+  -- both read and write side by rx_pclk, and TX FIFO being clocked on write side by txi_clk.
+  -- For TX, we can use local 125MHz clock.
+  -- For RX, the SGMII core implements the CTC FIFO, and by clocking SGMII also by local 125MHz 
+  -- (except serdes_recovered_clk, which goes to rx_pclk) we have *everthing* behind the SGMII
+  -- on local 125MHz clock.
+  
+  gbe_serdes: entity serdes_gbe
+  port map(
+  -- external I/Os
+    hdinp             => SD_RXD_P_IN, 
+    hdinn             => SD_RXD_N_IN,
+    hdoutp            => SD_TXD_P_OUT,
+    hdoutn            => SD_TXD_N_OUT,
+  -- clocks
+    pll_refclki       => CLK_125_IN, -- TX reference clock for PLL
+    rxrefclk          => CLK_125_IN, -- RX reference clock for CDR
+    txi_clk           => CLK_125_IN, -- feeds the TX FIFO
+    tx_pclk           => open, -- not really needed
+    rx_pclk           => sd_rx_clk, -- recovered RX clock, also used on FIFO!
+  -- TX channel
+    txdata            => sd_tx_data,
+    tx_k              => sd_tx_kcntl,
+    tx_disp_correct   => sd_tx_correct_disp,
+    xmit              => xmit, -- not used, should not harm
+  -- RX channel
+    rxdata            => sd_rx_data,
+    rx_k              => sd_rx_kcntl,
+    rx_disp_err       => sd_rx_disp_error,
+    rx_cv_err         => sd_rx_cv_error,
+    lsm_status_s      => lsm_status,
+    signal_detect_c   => '1', -- enable internal LSM
+  -- Status signals
+    pll_lol           => pll_lol,
+    rx_cdr_lol_s      => rx_cdr_lol,
+    rx_los_low_s      => rx_los_low,
+  -- Power control
+    rx_pwrup_c        => '1',
+    tx_pwrup_c        => '1',
+    serdes_pdb        => '1', -- DUAL is powered up 
+  -- Resets
+    sli_rst           => '0', -- soft logic reset (?)
+    rst_dual_c        => rst_dual,
+    rx_pcs_rst_c      => rx_pcs_rst_q,
+    rx_serdes_rst_c   => rx_serdes_rst_q,
+    tx_pcs_rst_c      => tx_pcs_rst,
+    serdes_rst_dual_c => '0',
+    tx_serdes_rst_c   => '0'
+  );
+    
+  -- RSL for TX of SerDes, based on extRSL logic
+  THE_MAIN_TX_RST: main_tx_reset_RS
+  port map (
+    CLEAR                => rst_dual,
+    CLK_REF              => CLK_125_IN,
+    TX_PLL_LOL_IN        => pll_lol,
+    TX_CLOCK_AVAIL_IN    => '1', -- not needed here
+    TX_PCS_RST_CH_C_OUT  => tx_pcs_rst,
+    SYNC_TX_QUAD_OUT     => open, --not needed here
+    LINK_TX_READY_OUT    => link_tx_ready,
+    STATE_OUT            => open
+  );
+
+  -- RSL for RX of SerDes, based on extRSL logic
+  -- CAVEAT: reset signals MUST BE sync'ed to recovered RX clock!
+  THE_MAIN_RX_RST: main_rx_reset_RS 
+  port map(
+    CLEAR             => rst_dual,
+    CLK_REF           => CLK_125_IN,
+    CDR_LOL_IN        => rx_cdr_lol,
+    CV_IN             => sd_rx_cv_error(0),
+    LSM_IN            => lsm_status,
+    LOS_IN            => rx_los_low,
+    WAP_ZERO_IN       => '1', -- not needed here
+    -- outputs
+    WAP_REQ_OUT       => open, -- not needed here
+    RX_SERDES_RST_OUT => rx_serdes_rst, -- CLK_REF based
+    RX_PCS_RST_OUT    => rx_pcs_rst, -- CLK_REF based
+    LINK_RX_READY_OUT => link_rx_ready, -- CLK_REF based
+    STATE_OUT         => open
+  );
+
+  -- reset signals for RX SerDes need to be sync'ed to real RX clock for ECP5
+  SYNC_RST_SIGS: entity work.signal_sync 
+  generic map( WIDTH => 2 )
+  port map(
+    RESET    => '0',
+    CLK0     => sd_rx_clk, 
+    CLK1     => sd_rx_clk,
+    D_IN(0)  => rx_pcs_rst,
+    D_IN(1)  => rx_serdes_rst,
+    D_OUT(0) => rx_pcs_rst_q,
+    D_OUT(1) => rx_serdes_rst_q
+  );
+
+  -- Status signals
+  STATUS_OUT(7) <= '0';
+  STATUS_OUT(6) <= '0';
+  STATUS_OUT(5) <= '0';
+  STATUS_OUT(4) <= pcs_rx_en;     -- SerDes RX activity
+  STATUS_OUT(3) <= pcs_tx_en;     -- SerDes TX activity
+  STATUS_OUT(2) <= an_complete;   -- GbE Autonegotiation completed
+  STATUS_OUT(1) <= link_rx_ready; -- SerDes Rx channel operational
+  STATUS_OUT(0) <= link_tx_ready; -- SerDes TX channel operational
+  
+--  -- "Good" debugging pins
+--  debug(7 downto 0)  <= sd_tx_data;
+--  debug(15 downto 8) <= sd_rx_data;
+--  debug(16)          <= sd_tx_kcntl(0);
+--  debug(17)          <= sd_rx_kcntl(0);
+--  debug(18)          <= '0';
+--  debug(19)          <= '0';
+--  -- "Bad" debugging pins
+--  debug(20) <= pll_lol;
+--  debug(21) <= rx_cdr_lol;
+--  debug(22) <= rx_los_low;
+--  debug(23) <= sd_rx_cv_error(0);
+--  debug(24) <= lsm_status;
+--  debug(25) <= mr_main_reset;
+--  debug(26) <= mr_an_enable;
+--  debug(27) <= mr_restart_an;
+--  debug(28) <= mr_page_rx;
+--  debug(29) <= an_complete;
+--  debug(30) <= an_link_ok;
+--  debug(31) <= '0';
+--  debug(32) <= link_rx_ready;
+--  debug(33) <= link_tx_ready;
+  debug(62) <= link_rx_ready;
+  debug(63) <= link_tx_ready;
+
+  -- SGMII core
+  SGMII_GBE_PCS : sgmii_gbe_core
+  port map(
+    rst_n                   => synced_rst,
+    signal_detect           => link_rx_ready,
+    gbe_mode                => '1',
+    sgmii_mode              => '0',
+    operational_rate        => operational_rate,
+    debug_link_timer_short  => '0',
+    force_isolate           => '0',
+    force_loopback          => '0',
+    force_unidir            => '0',
+    rx_compensation_err     => open,
+    ctc_drop_flag           => open,
+    ctc_add_flag            => open,
+    an_link_ok              => an_link_ok, --open,
+  -- MAC interface
+    tx_clk_125              => CLK_125_IN,
+    tx_clock_enable_source  => tx_clk_en,
+    tx_clock_enable_sink    => tx_clk_en,
+    tx_d                    => pcs_txd, -- TX data from MAC
+    tx_en                   => pcs_tx_en, -- TX data enable from MAC
+    tx_er                   => pcs_tx_er, -- TX error from MAC
+    rx_clk_125              => CLK_125_IN,
+    rx_clock_enable_source  => rx_clk_en,
+    rx_clock_enable_sink    => rx_clk_en,
+    rx_d                    => pcs_rxd, -- RX data to MAC
+    rx_dv                   => pcs_rx_en, -- RX data enable to MAC
+    rx_er                   => pcs_rx_er, -- RX error to MAC
+    col                     => open,
+    crs                     => open,
+    -- SerDes interface
+    tx_data                 => sd_tx_data, -- TX data to SerDes
+    tx_kcntl                => sd_tx_kcntl(0), -- TX komma control to SerDes
+    tx_disparity_cntl       => sd_tx_correct_disp(0), -- idle parity state control in IPG (to SerDes)
+    xmit_autoneg            => xmit(0),
+    serdes_recovered_clk    => sd_rx_clk, -- 125MHz recovered from receive bit stream
+    rx_data                 => sd_rx_data, -- RX data from SerDes
+    rx_kcntl                => sd_rx_kcntl(0), -- RX komma control from SerDes
+    rx_err_decode_mode      => '0', -- receive error control mode fixed to normal
+    rx_even                 => '0', -- unused (receive error control mode = normal, tie to GND)
+    rx_disp_err             => sd_rx_disp_error(0), -- RX disparity error from SerDes
+    rx_cv_err               => sd_rx_cv_error(0), -- RX code violation error from SerDes
+    -- Autonegotiation stuff
+    mr_an_complete          => an_complete,
+    mr_page_rx              => mr_page_rx,
+    mr_lp_adv_ability       => mr_lp_adv_ability,
+    mr_main_reset           => mr_main_reset,
+    mr_an_enable            => mr_an_enable,
+    mr_restart_an           => mr_restart_an,
+    mr_adv_ability          => mr_adv_ability
+  );
+          
+  MAC_AN_READY_OUT <= an_complete;
+
+--- SIMPLE ---
+  operational_rate <= b"10";
+--- /SIMPLE ---
+
+--- SIMPLE ---
+  mr_main_reset <= rst_dual;
+  mr_restart_an <= pulse;
+  mr_an_enable  <= link_rx_ready;
+  mr_adv_ability <= x"0020";
+
+  SYNC_PROC: process( CLK_125_IN ) 
+  begin
+    if( rising_edge(CLK_125_IN) ) then
+      delay_q <= delay_q(6 downto 0) & link_rx_ready;
+    end if;
+  end process SYNC_PROC;
+  
+  pulse  <= not delay_q(7) and delay_q(6);
+--- /SIMPLE ---
+
+  -- "Good" debugging pins
+  debug(7 downto 0)  <= pcs_txd;
+  debug(15 downto 8) <= pcs_rxd;
+  debug(16)          <= pcs_tx_en;
+  debug(17)          <= pcs_tx_er;
+  debug(18)          <= pcs_rx_en;
+  debug(19)          <= pcs_rx_er;
+  -- "Bad" debugging pins
+  debug(20) <= pll_lol;
+  debug(21) <= rx_cdr_lol;
+  debug(22) <= rx_los_low;
+  debug(23) <= sd_rx_cv_error(0);
+  debug(24) <= lsm_status;
+  debug(25) <= mr_main_reset;
+  debug(26) <= mr_an_enable;
+  debug(27) <= mr_restart_an;
+  debug(28) <= mr_page_rx;
+  debug(29) <= an_complete;
+  debug(30) <= an_link_ok;
+  debug(31) <= '0';
+  debug(32) <= link_rx_ready;
+  debug(33) <= link_tx_ready;
+        
+  MAC: tsmac_gbe
+  port map(
+  ----------------- clock and reset port declarations ------------------
+    hclk            => CLK_SYS_IN,
+    txmac_clk       => CLK_125_IN,
+    rxmac_clk       => CLK_125_IN,
+    reset_n         => synced_rst, -- was GSR_N
+  ------------------- Input signals to the GMII ----------------
+    rxd             => pcs_rxd,
+    rx_dv           => pcs_rx_en,
+    rx_er           => pcs_rx_er,
+  -------------------- Input signals to the CPU I/F -------------------
+    haddr           => tsm_haddr,
+    hdatain         => tsm_hdata,
+    hcs_n           => tsm_hcs_n,
+    hwrite_n        => tsm_hwrite_n,
+    hread_n         => tsm_hread_n,
+  ---------------- Input signals to the Tx MAC FIFO I/F ---------------
+    tx_fifodata     => MAC_TX_DATA_IN,
+    tx_fifoavail    => MAC_FIFOAVAIL_IN,
+    tx_fifoeof      => MAC_FIFOEOF_IN,
+    tx_fifoempty    => MAC_FIFOEMPTY_IN,
+    tx_sndpaustim   => x"0000",
+    tx_sndpausreq   => '0',
+    tx_fifoctrl     => '0',  -- always data frame
+  ---------------- Input signals to the Rx MAC FIFO I/F --------------- 
+    rx_fifo_full    => MAC_RX_FIFOFULL_IN,
+    ignore_pkt      => '0',
+  ---------------- Output signals from the GMII -----------------------
+    txd             => pcs_txd,
+    tx_en           => pcs_tx_en,
+    tx_er           => pcs_tx_er,
+  ----------------- Output signals from the CPU I/F -------------------
+    hdataout        => open,
+    hdataout_en_n   => tsm_hdataout_en_n,
+    hready_n        => tsm_hready_n,
+    cpu_if_gbit_en  => open,
+  ------------- Output signals from the Tx MAC FIFO I/F --------------- 
+    tx_macread      => MAC_TX_READ_OUT,
+    tx_discfrm      => MAC_TX_DISCRFRM_OUT,
+    tx_staten       => MAC_TX_STAT_EN_OUT,
+    tx_statvec      => MAC_TX_STATS_OUT,
+    tx_done         => MAC_TX_DONE_OUT,
+  ------------- Output signals from the Rx MAC FIFO I/F ---------------   
+    rx_fifo_error   => MAC_RX_FIFO_ERR_OUT,
+    rx_stat_vector  => MAC_RX_STATS_OUT,
+    rx_dbout        => MAC_RX_DATA_OUT,
+    rx_write        => MAC_RX_WRITE_OUT,
+    rx_stat_en      => MAC_RX_STAT_EN_OUT,
+    rx_eof          => MAC_RX_EOF_OUT,
+    rx_error        => MAC_RX_ERROR_OUT
+  );
+  
+  TSMAC_CONTROLLER : trb_net16_gbe_mac_control
+  port map(
+    CLK                 => CLK_SYS_IN,
+    RESET               => RESET, 
+  -- signals to/from main controller
+    MC_TSMAC_READY_OUT  => MAC_READY_CONF_OUT,
+    MC_RECONF_IN        => MAC_RECONF_IN,
+    MC_GBE_EN_IN        => '1',
+    MC_RX_DISCARD_FCS   => '0',
+    MC_PROMISC_IN       => '1',
+    MC_MAC_ADDR_IN      => (others => '0'),
+  -- signal to/from Host interface of TriSpeed MAC
+    TSM_HADDR_OUT       => tsm_haddr,
+    TSM_HDATA_OUT       => tsm_hdata,
+    TSM_HCS_N_OUT       => tsm_hcs_n,
+    TSM_HWRITE_N_OUT    => tsm_hwrite_n,
+    TSM_HREAD_N_OUT     => tsm_hread_n,
+    TSM_HREADY_N_IN     => tsm_hready_n,
+    TSM_HDATA_EN_N_IN   => tsm_hdataout_en_n,
+  -- Debug
+    DEBUG_OUT           => open
+  );
+                
+end architecture RTL;
diff --git a/gbe_trb_ecp5/base/gbe_wrapper_single.vhd b/gbe_trb_ecp5/base/gbe_wrapper_single.vhd
new file mode 100644
index 0000000..c41d25d
--- /dev/null
+++ b/gbe_trb_ecp5/base/gbe_wrapper_single.vhd
@@ -0,0 +1,701 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_ARITH.all;
+use IEEE.std_logic_UNSIGNED.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+use work.trb_net_gbe_components.all;
+use work.trb_net_gbe_protocols.all;
+
+
+entity gbe_wrapper_single is
+  generic(
+    DO_SIMULATION             : integer range 0 to 1         := 0;
+    INCLUDE_DEBUG             : integer range 0 to 1         := 0;
+    USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1         := 0; -- only for debugging
+    USE_EXTERNAL_TRBNET_DUMMY : integer range 0 to 1         := 0; -- only for debugging
+    RX_PATH_ENABLE            : integer range 0 to 1         := 1; -- 
+    FIXED_SIZE_MODE           : integer range 0 to 1         := 1; -- only for debugging
+    INCREMENTAL_MODE          : integer range 0 to 1         := 0; -- only for debugging
+    FIXED_SIZE                : integer range 0 to 65535     := 10; -- only for debugging
+    FIXED_DELAY_MODE          : integer range 0 to 1         := 1; -- only for debugging
+    UP_DOWN_MODE              : integer range 0 to 1         := 0; -- only for debugging
+    UP_DOWN_LIMIT             : integer range 0 to 16777215  := 0; -- only for debugging
+    FIXED_DELAY               : integer range 0 to 16777215  := 16777215; -- only for debugging
+    NUMBER_OF_GBE_LINKS       : integer range 1 to 4         := 4; --
+    LINKS_ACTIVE              : std_logic_vector(3 downto 0) := "1111";
+    LINK_HAS_PING             : std_logic_vector(3 downto 0) := "1111";
+    LINK_HAS_ARP              : std_logic_vector(3 downto 0) := "1111";
+    LINK_HAS_DHCP             : std_logic_vector(3 downto 0) := "1111";
+    LINK_HAS_READOUT          : std_logic_vector(3 downto 0) := "1111";
+    LINK_HAS_SLOWCTRL         : std_logic_vector(3 downto 0) := "1111";
+    LINK_HAS_FWD              : std_logic_vector(3 downto 0) := "1111"
+  );
+  port(
+    CLK_SYS_IN               : in  std_logic;
+    CLK_125_IN               : in  std_logic;
+    RESET                    : in  std_logic;
+    GSR_N                    : in  std_logic;
+    SD_PRSNT_N_IN            : in  std_logic;
+    SD_LOS_IN                : in  std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SD_TXDIS_OUT             : out std_logic; -- SFP disable
+    SD_LED_GREEN_OUT         : out std_logic;
+    SD_LED_YELLOW_OUT        : out std_logic;
+    SD_LED_RED_OUT           : out std_logic;
+    --
+    TRIGGER_IN               : in  std_logic; -- for debug purpose only
+    -- CTS interface
+    CTS_NUMBER_IN            : in  std_logic_vector(15 downto 0);
+    CTS_CODE_IN              : in  std_logic_vector(7 downto 0);
+    CTS_INFORMATION_IN       : in  std_logic_vector(7 downto 0);
+    CTS_READOUT_TYPE_IN      : in  std_logic_vector(3 downto 0);
+    CTS_START_READOUT_IN     : in  std_logic;
+    CTS_DATA_OUT             : out std_logic_vector(31 downto 0);
+    CTS_DATAREADY_OUT        : out std_logic;
+    CTS_READOUT_FINISHED_OUT : out std_logic;
+    CTS_READ_IN              : in  std_logic;
+    CTS_LENGTH_OUT           : out std_logic_vector(15 downto 0);
+    CTS_ERROR_PATTERN_OUT    : out std_logic_vector(31 downto 0);
+    -- Data payload interface
+    FEE_DATA_IN              : in  std_logic_vector(15 downto 0);
+    FEE_DATAREADY_IN         : in  std_logic;
+    FEE_READ_OUT             : out std_logic;
+    FEE_STATUS_BITS_IN       : in  std_logic_vector(31 downto 0);
+    FEE_BUSY_IN              : in  std_logic;
+    -- SlowControl
+    MY_TRBNET_ADDRESS_IN     : in std_logic_vector(15 downto 0);
+    ISSUE_REBOOT_OUT         : out std_logic;
+    MC_UNIQUE_ID_IN          : in  std_logic_vector(63 downto 0);
+    GSC_CLK_IN               : in  std_logic;
+    GSC_INIT_DATAREADY_OUT   : out std_logic;
+    GSC_INIT_DATA_OUT        : out std_logic_vector(15 downto 0);
+    GSC_INIT_PACKET_NUM_OUT  : out std_logic_vector(2 downto 0);
+    GSC_INIT_READ_IN         : in  std_logic;
+    GSC_REPLY_DATAREADY_IN   : in  std_logic;
+    GSC_REPLY_DATA_IN        : in  std_logic_vector(15 downto 0);
+    GSC_REPLY_PACKET_NUM_IN  : in  std_logic_vector(2 downto 0);
+    GSC_REPLY_READ_OUT       : out std_logic;
+    GSC_BUSY_IN              : in  std_logic;
+    -- IP configuration
+    BUS_IP_RX                : in  CTRLBUS_RX;
+    BUS_IP_TX                : out CTRLBUS_TX;
+    -- Registers config
+    BUS_REG_RX               : in  CTRLBUS_RX;
+    BUS_REG_TX               : out CTRLBUS_TX;
+    -- Forwarder
+    FWD_DST_MAC_IN           : in  std_logic_vector(47 downto 0) := (others => '0');
+    FWD_DST_IP_IN            : in  std_logic_vector(31 downto 0) := (others => '0');
+    FWD_DST_UDP_IN           : in  std_logic_vector(15 downto 0) := (others => '0');
+    FWD_DATA_IN              : in  std_logic_vector(7 downto 0) := (others => '0');
+    FWD_DATA_VALID_IN        : in  std_logic := '0';
+    FWD_SOP_IN               : in  std_logic := '0';
+    FWD_EOP_IN               : in  std_logic := '0';
+    FWD_READY_OUT            : out std_logic;
+    FWD_FULL_OUT             : out std_logic;
+    --
+    MAKE_RESET_OUT           : out std_logic;
+    -- 
+    STATUS_OUT               : out std_logic_vector(15 downto 0);
+    DEBUG_OUT                : out std_logic_vector(127 downto 0)
+  );
+end entity gbe_wrapper_single;
+
+architecture RTL of gbe_wrapper_single is
+  signal mac_ready_conf             : std_logic;
+  signal mac_reconf                 : std_logic;
+  signal mac_an_ready               : std_logic;
+  signal mac_fifoavail              : std_logic;
+  signal mac_fifoeof                : std_logic;
+  signal mac_fifoempty              : std_logic;
+  signal mac_rx_fifofull            : std_logic;
+  signal mac_tx_data                : std_logic_vector(7 downto 0);
+  signal mac_tx_read                : std_logic;
+  signal mac_tx_discrfrm            : std_logic;
+  signal mac_tx_stat_en             : std_logic;
+  signal mac_tx_stats               : std_logic_vector(30 downto 0);
+  signal mac_tx_done                : std_logic;
+  signal mac_rx_fifo_err            : std_logic;
+  signal mac_rx_stats               : std_logic_vector(31 downto 0);
+  signal mac_rx_data                : std_logic_vector(7 downto 0);
+  signal mac_rx_write               : std_logic;
+  signal mac_rx_stat_en             : std_logic;
+  signal mac_rx_eof                 : std_logic;
+  signal mac_rx_err                 : std_logic;
+
+  signal cfg_gbe_enable             : std_logic;
+  signal cfg_ipu_enable             : std_logic;
+  signal cfg_mult_enable            : std_logic;
+  signal cfg_subevent_id            : std_logic_vector(31 downto 0);
+  signal cfg_subevent_dec           : std_logic_vector(31 downto 0);
+  signal cfg_queue_dec              : std_logic_vector(31 downto 0);
+  signal cfg_readout_ctr            : std_logic_vector(23 downto 0);
+  signal cfg_readout_ctr_valid      : std_logic;
+  signal cfg_insert_ttype           : std_logic;
+  signal cfg_max_sub                : std_logic_vector(15 downto 0);
+  signal cfg_max_queue              : std_logic_vector(15 downto 0);
+  signal cfg_max_subs_in_queue      : std_logic_vector(15 downto 0);
+  signal cfg_max_single_sub         : std_logic_vector(15 downto 0);
+  signal cfg_additional_hdr         : std_logic;
+  signal cfg_soft_rst               : std_logic;
+  signal cfg_allow_rx               : std_logic;
+  signal cfg_max_frame              : std_logic_vector(15 downto 0);
+
+  signal dbg_hist, dbg_hist2        : hist_array;
+
+  signal mac_0                      : std_logic_vector(47 downto 0);
+  signal cfg_max_reply              : std_logic_vector(31 downto 0);
+
+  signal mlt_cts_number             : std_logic_vector(15 downto 0);
+  signal mlt_cts_code               : std_logic_vector(7 downto 0);
+  signal mlt_cts_information        : std_logic_vector(7 downto 0);
+  signal mlt_cts_readout_type       : std_logic_vector(3 downto 0);
+  signal mlt_cts_start_readout      : std_logic_vector(0 downto 0);
+  signal mlt_cts_data               : std_logic_vector(31 downto 0);
+  signal mlt_cts_dataready          : std_logic_vector(0 downto 0);
+  signal mlt_cts_readout_finished   : std_logic_vector(0 downto 0);
+  signal mlt_cts_read               : std_logic_vector(0 downto 0);
+  signal mlt_cts_length             : std_logic_vector(15 downto 0);
+  signal mlt_cts_error_pattern      : std_logic_vector(31 downto 0);
+  signal mlt_fee_data               : std_logic_vector(15 downto 0);
+  signal mlt_fee_dataready          : std_logic_vector(0 downto 0);
+  signal mlt_fee_read               : std_logic_vector(0 downto 0);
+  signal mlt_fee_status             : std_logic_vector(31 downto 0);
+  signal mlt_fee_busy               : std_logic_vector(0 downto 0);
+
+  signal mlt_gsc_clk                : std_logic;
+  signal mlt_gsc_init_dataready     : std_logic;
+  signal mlt_gsc_init_data          : std_logic_vector(15 downto 0);
+  signal mlt_gsc_init_packet        : std_logic_vector(2 downto 0);
+  signal mlt_gsc_init_read          : std_logic;
+  signal mlt_gsc_reply_dataready    : std_logic;
+  signal mlt_gsc_reply_data         : std_logic_vector(15 downto 0);
+  signal mlt_gsc_reply_packet       : std_logic_vector(2 downto 0);
+  signal mlt_gsc_reply_read         : std_logic;
+  signal mlt_gsc_busy               : std_logic;
+
+  signal local_cts_number           : std_logic_vector(15 downto 0);
+  signal local_cts_code             : std_logic_vector(7 downto 0);
+  signal local_cts_information      : std_logic_vector(7 downto 0);
+  signal local_cts_readout_type     : std_logic_vector(3 downto 0);
+  signal local_cts_start_readout    : std_logic;
+  signal local_cts_readout_finished : std_logic;
+  signal local_cts_status_bits      : std_logic_vector(31 downto 0);
+  signal local_fee_data             : std_logic_vector(15 downto 0);
+  signal local_fee_dataready        : std_logic;
+  signal local_fee_read             : std_logic;
+  signal local_fee_status_bits      : std_logic_vector(31 downto 0);
+  signal local_fee_busy             : std_logic;
+  signal dhcp_done                  : std_logic;
+  signal all_links_ready            : std_logic;
+  signal monitor_rx_frames          : std_logic_vector(31 downto 0);
+  signal monitor_rx_bytes           : std_logic_vector(31 downto 0);
+  signal monitor_tx_frames          : std_logic_vector(31 downto 0);
+  signal monitor_tx_bytes           : std_logic_vector(31 downto 0);
+  signal monitor_tx_packets         : std_logic_vector(31 downto 0);
+  signal monitor_dropped            : std_logic_vector(31 downto 0);
+  signal sum_rx_frames              : std_logic_vector(31 downto 0);
+  signal sum_rx_bytes               : std_logic_vector(31 downto 0);
+  signal sum_tx_frames              : std_logic_vector(31 downto 0);
+  signal sum_tx_bytes               : std_logic_vector(31 downto 0);
+  signal sum_tx_packets             : std_logic_vector(31 downto 0);
+  signal sum_dropped                : std_logic_vector(31 downto 0);
+
+  signal busip0                                               : CTRLBUS_TX;
+  signal SD_RXD_P_IN, SD_RXD_N_IN, SD_TXD_P_OUT, SD_TXD_N_OUT : std_logic;
+  --attribute nopad : string;
+  --attribute nopad of SD_RXD_P_IN, SD_RXD_N_IN, SD_TXD_P_OUT, SD_TXD_N_OUT : signal is "true";
+
+  signal dummy_event                                        : std_logic_vector(15 downto 0);
+  signal dummy_mode                                         : std_logic;
+  signal make_reset0                                        : std_logic := '0';
+  signal monitor_gen_dbg                                    : std_logic_vector(c_MAX_PROTOCOLS * 64 - 1 downto 0);
+
+  signal cfg_autothrottle   : std_logic;
+  signal cfg_throttle_pause : std_logic_vector(15 downto 0);
+  
+  signal issue_reboot : std_logic;
+  signal my_ip        : std_logic_vector(127 downto 0);
+  signal debug        : std_logic_vector(127 downto 0);
+  
+begin
+
+--  assert hits if condition in brackets is true, or overall condition is false
+--  assert not (dual_mode = 8)                           report "Note: DUAL with one slave port detected" severity note;
+
+  assert not (NUMBER_OF_GBE_LINKS /= 1)                report "Error: only one GbE link allowed" severity error;
+  assert not (LINKS_ACTIVE /= b"0001")                 report "Error: no / wrong GbE interface selected" severity error;
+  assert not (LINK_HAS_PING(3 downto 1) /= b"000")     report "Error: only interface 0 supported" severity error;
+  assert not (LINK_HAS_ARP(3 downto 1) /= b"000")      report "Error: only interface 0 supported" severity error;
+  assert not (LINK_HAS_DHCP(3 downto 1) /= b"000")     report "Error: only interface 0 supported" severity error;
+  assert not (LINK_HAS_READOUT(3 downto 1) /= b"000")  report "Error: only interface 0 supported" severity error;
+  assert not (LINK_HAS_SLOWCTRL(3 downto 1) /= b"000") report "Error: only interface 0 supported" severity error;
+  assert not (LINK_HAS_FWD(3 downto 1) /= b"000")      report "Error: only interface 0 supported" severity error;
+  
+  -- debug(127 downto 64) are local
+  -- debug(63 downto 0) are media interface
+  DEBUG_OUT <= debug;
+
+  mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
+
+  all_links_ready <= '1' when dhcp_done = '1' else '0';
+
+  MAKE_RESET_OUT <= '1' when  make_reset0 = '1' else '0';
+  
+  ISSUE_REBOOT_OUT <= '0' when issue_reboot = '0' else '1';
+
+  physical : entity work.gbe_med_interface_single
+  port map(
+    RESET               => RESET,
+    GSR_N               => GSR_N,
+    CLK_SYS_IN          => CLK_SYS_IN,
+    CLK_125_OUT         => open, -- not needed
+    CLK_125_IN          => CLK_125_IN,
+    CLK_125_RX_OUT      => open, -- not needed
+    MAC_READY_CONF_OUT  => mac_ready_conf,
+    MAC_RECONF_IN       => mac_reconf,
+    MAC_AN_READY_OUT    => mac_an_ready,
+    MAC_FIFOAVAIL_IN    => mac_fifoavail,
+    MAC_FIFOEOF_IN      => mac_fifoeof,
+    MAC_FIFOEMPTY_IN    => mac_fifoempty,
+    MAC_RX_FIFOFULL_IN  => mac_rx_fifofull,
+    MAC_TX_DATA_IN      => mac_tx_data,
+    MAC_TX_READ_OUT     => mac_tx_read,
+    MAC_TX_DISCRFRM_OUT => mac_tx_discrfrm,
+    MAC_TX_STAT_EN_OUT  => mac_tx_stat_en,
+    MAC_TX_STATS_OUT    => mac_tx_stats,
+    MAC_TX_DONE_OUT     => mac_tx_done,
+    MAC_RX_FIFO_ERR_OUT => mac_rx_fifo_err,
+    MAC_RX_STATS_OUT    => mac_rx_stats,
+    MAC_RX_DATA_OUT     => mac_rx_data,
+    MAC_RX_WRITE_OUT    => mac_rx_write,
+    MAC_RX_STAT_EN_OUT  => mac_rx_stat_en,
+    MAC_RX_EOF_OUT      => mac_rx_eof,
+    MAC_RX_ERROR_OUT    => mac_rx_err,
+    SD_RXD_P_IN         => SD_RXD_P_IN,
+    SD_RXD_N_IN         => SD_RXD_N_IN,
+    SD_TXD_P_OUT        => SD_TXD_P_OUT,
+    SD_TXD_N_OUT        => SD_TXD_N_OUT,
+    SD_PRSNT_N_IN       => SD_PRSNT_N_IN,
+    SD_LOS_IN           => SD_LOS_IN,
+    SD_TXDIS_OUT        => SD_TXDIS_OUT,
+    STATUS_OUT          => STATUS_OUT(7 downto 0),
+    DEBUG_OUT           => debug(63 downto 0) --open
+  );
+
+  STATUS_OUT(8)           <= dhcp_done; -- DHCP has completed
+  STATUS_OUT(15 downto 9) <= (others => '0');
+  
+  gbe_inst : entity work.gbe_logic_wrapper
+  generic map(DO_SIMULATION           => DO_SIMULATION,
+            INCLUDE_DEBUG             => INCLUDE_DEBUG,
+            USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY,
+            RX_PATH_ENABLE            => RX_PATH_ENABLE,
+            INCLUDE_READOUT           => LINK_HAS_READOUT(0),
+            INCLUDE_SLOWCTRL          => LINK_HAS_SLOWCTRL(0),
+            INCLUDE_DHCP              => LINK_HAS_DHCP(0),
+            INCLUDE_ARP               => LINK_HAS_ARP(0),
+            INCLUDE_PING              => LINK_HAS_PING(0),
+            INCLUDE_FWD               => LINK_HAS_FWD(0),
+            FRAME_BUFFER_SIZE         => 1,
+            READOUT_BUFFER_SIZE       => 4,
+            SLOWCTRL_BUFFER_SIZE      => 2,
+            FIXED_SIZE_MODE           => FIXED_SIZE_MODE,
+            INCREMENTAL_MODE          => INCREMENTAL_MODE,
+            FIXED_SIZE                => FIXED_SIZE,
+            FIXED_DELAY_MODE          => FIXED_DELAY_MODE,
+            UP_DOWN_MODE              => UP_DOWN_MODE,
+            UP_DOWN_LIMIT             => UP_DOWN_LIMIT,
+            FIXED_DELAY               => FIXED_DELAY)
+  port map(
+    CLK_SYS_IN               => CLK_SYS_IN,
+    CLK_125_IN               => CLK_125_IN,
+    CLK_RX_125_IN            => CLK_125_IN,
+    RESET                    => RESET,
+    GSR_N                    => GSR_N,
+    MY_MAC_IN                => mac_0,
+    DHCP_DONE_OUT            => dhcp_done,
+    MY_IP_OUT                => my_ip(31 downto 0),
+    MY_TRBNET_ADDRESS_IN     => MY_TRBNET_ADDRESS_IN,
+    ISSUE_REBOOT_OUT         => issue_reboot,
+    MAC_READY_CONF_IN        => mac_ready_conf,
+    MAC_RECONF_OUT           => mac_reconf,
+    MAC_AN_READY_IN          => mac_an_ready,
+    MAC_FIFOAVAIL_OUT        => mac_fifoavail,
+    MAC_FIFOEOF_OUT          => mac_fifoeof,
+    MAC_FIFOEMPTY_OUT        => mac_fifoempty,
+    MAC_RX_FIFOFULL_OUT      => mac_rx_fifofull,
+    MAC_TX_DATA_OUT          => mac_tx_data,
+    MAC_TX_READ_IN           => mac_tx_read,
+    MAC_TX_DISCRFRM_IN       => mac_tx_discrfrm,
+    MAC_TX_STAT_EN_IN        => mac_tx_stat_en,
+    MAC_TX_STATS_IN          => mac_tx_stats,
+    MAC_TX_DONE_IN           => mac_tx_done,
+    MAC_RX_FIFO_ERR_IN       => mac_rx_fifo_err,
+    MAC_RX_STATS_IN          => mac_rx_stats,
+    MAC_RX_DATA_IN           => mac_rx_data,
+    MAC_RX_WRITE_IN          => mac_rx_write,
+    MAC_RX_STAT_EN_IN        => mac_rx_stat_en,
+    MAC_RX_EOF_IN            => mac_rx_eof,
+    MAC_RX_ERROR_IN          => mac_rx_err,
+    CTS_NUMBER_IN            => mlt_cts_number,
+    CTS_CODE_IN              => mlt_cts_code,
+    CTS_INFORMATION_IN       => mlt_cts_information,
+    CTS_READOUT_TYPE_IN      => mlt_cts_readout_type,
+    CTS_START_READOUT_IN     => mlt_cts_start_readout(0),
+    CTS_DATA_OUT             => mlt_cts_data,
+    CTS_DATAREADY_OUT        => mlt_cts_dataready(0),
+    CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(0),
+    CTS_READ_IN              => mlt_cts_read(0),
+    CTS_LENGTH_OUT           => mlt_cts_length,
+    CTS_ERROR_PATTERN_OUT    => mlt_cts_error_pattern,
+    FEE_DATA_IN              => mlt_fee_data,
+    FEE_DATAREADY_IN         => mlt_fee_dataready(0),
+    FEE_READ_OUT             => mlt_fee_read(0),
+    FEE_STATUS_BITS_IN       => mlt_fee_status,
+    FEE_BUSY_IN              => mlt_fee_busy(0),
+    GSC_CLK_IN               => mlt_gsc_clk,
+    GSC_INIT_DATAREADY_OUT   => mlt_gsc_init_dataready,
+    GSC_INIT_DATA_OUT        => mlt_gsc_init_data,
+    GSC_INIT_PACKET_NUM_OUT  => mlt_gsc_init_packet,
+    GSC_INIT_READ_IN         => mlt_gsc_init_read,
+    GSC_REPLY_DATAREADY_IN   => mlt_gsc_reply_dataready,
+    GSC_REPLY_DATA_IN        => mlt_gsc_reply_data,
+    GSC_REPLY_PACKET_NUM_IN  => mlt_gsc_reply_packet,
+    GSC_REPLY_READ_OUT       => mlt_gsc_reply_read,
+    GSC_BUSY_IN              => mlt_gsc_busy,
+    SLV_ADDR_IN              => BUS_IP_RX.addr(7 downto 0),
+    SLV_READ_IN              => BUS_IP_RX.read,
+    SLV_WRITE_IN             => BUS_IP_RX.write,
+    SLV_BUSY_OUT             => busip0.nack,
+    SLV_ACK_OUT              => busip0.ack,
+    SLV_DATA_IN              => BUS_IP_RX.data,
+    SLV_DATA_OUT             => busip0.data,
+    CFG_GBE_ENABLE_IN        => cfg_gbe_enable,
+    CFG_IPU_ENABLE_IN        => cfg_ipu_enable,
+    CFG_MULT_ENABLE_IN       => cfg_mult_enable,
+    CFG_MAX_FRAME_IN         => cfg_max_frame,
+    CFG_ALLOW_RX_IN          => cfg_allow_rx,
+    CFG_SOFT_RESET_IN        => cfg_soft_rst,
+    CFG_SUBEVENT_ID_IN       => cfg_subevent_id,
+    CFG_SUBEVENT_DEC_IN      => cfg_subevent_dec,
+    CFG_QUEUE_DEC_IN         => cfg_queue_dec,
+    CFG_READOUT_CTR_IN       => cfg_readout_ctr,
+    CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
+    CFG_INSERT_TTYPE_IN      => cfg_insert_ttype,
+    CFG_MAX_SUB_IN           => cfg_max_sub,
+    CFG_MAX_QUEUE_IN         => cfg_max_queue,
+    CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
+    CFG_MAX_SINGLE_SUB_IN    => cfg_max_single_sub,
+    CFG_ADDITIONAL_HDR_IN    => cfg_additional_hdr,
+    CFG_MAX_REPLY_SIZE_IN    => cfg_max_reply,
+    CFG_AUTO_THROTTLE_IN     => cfg_autothrottle,
+    CFG_THROTTLE_PAUSE_IN    => cfg_throttle_pause,
+    FWD_DST_MAC_IN           => FWD_DST_MAC_IN,
+    FWD_DST_IP_IN            => FWD_DST_IP_IN,
+    FWD_DST_UDP_IN           => FWD_DST_UDP_IN,
+    FWD_DATA_IN              => FWD_DATA_IN,
+    FWD_DATA_VALID_IN        => FWD_DATA_VALID_IN,
+    FWD_SOP_IN               => FWD_SOP_IN,
+    FWD_EOP_IN               => FWD_EOP_IN,
+    FWD_READY_OUT            => FWD_READY_OUT,
+    FWD_FULL_OUT             => FWD_FULL_OUT,
+    MONITOR_RX_FRAMES_OUT    => monitor_rx_frames,
+    MONITOR_RX_BYTES_OUT     => monitor_rx_bytes,
+    MONITOR_TX_FRAMES_OUT    => monitor_tx_frames,
+    MONITOR_TX_BYTES_OUT     => monitor_tx_bytes,
+    MONITOR_TX_PACKETS_OUT   => monitor_tx_packets,
+    MONITOR_DROPPED_OUT      => monitor_dropped,
+    MONITOR_GEN_DBG_OUT      => monitor_gen_dbg,
+    MAKE_RESET_OUT           => make_reset0
+  );
+                                       
+  BUS_IP_TX.ack  <= busip0.ack  when rising_edge(CLK_SYS_IN);
+  BUS_IP_TX.nack <= busip0.nack when rising_edge(CLK_SYS_IN);
+  BUS_IP_TX.data <= busip0.data when rising_edge(CLK_SYS_IN);
+
+  real_ipu_gen : if USE_EXTERNAL_TRBNET_DUMMY = 0 generate
+    ipu_mult : entity work.gbe_ipu_multiplexer
+      generic map(
+        DO_SIMULATION       => DO_SIMULATION,
+        INCLUDE_DEBUG       => INCLUDE_DEBUG,
+        LINK_HAS_READOUT    => LINK_HAS_READOUT,
+        NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS
+      )
+      port map(
+        CLK_SYS_IN                  => CLK_SYS_IN,
+        RESET                       => RESET,
+        CTS_NUMBER_IN               => CTS_NUMBER_IN,
+        CTS_CODE_IN                 => CTS_CODE_IN,
+        CTS_INFORMATION_IN          => CTS_INFORMATION_IN,
+        CTS_READOUT_TYPE_IN         => CTS_READOUT_TYPE_IN,
+        CTS_START_READOUT_IN        => CTS_START_READOUT_IN,
+        CTS_DATA_OUT                => CTS_DATA_OUT,
+        CTS_DATAREADY_OUT           => CTS_DATAREADY_OUT,
+        CTS_READOUT_FINISHED_OUT    => CTS_READOUT_FINISHED_OUT,
+        CTS_READ_IN                 => CTS_READ_IN,
+        CTS_LENGTH_OUT              => CTS_LENGTH_OUT,
+        CTS_ERROR_PATTERN_OUT       => CTS_ERROR_PATTERN_OUT,
+        FEE_DATA_IN                 => FEE_DATA_IN,
+        FEE_DATAREADY_IN            => FEE_DATAREADY_IN,
+        FEE_READ_OUT                => FEE_READ_OUT,
+        FEE_STATUS_BITS_IN          => FEE_STATUS_BITS_IN,
+        FEE_BUSY_IN                 => FEE_BUSY_IN,
+        MLT_CTS_NUMBER_OUT          => mlt_cts_number,
+        MLT_CTS_CODE_OUT            => mlt_cts_code,
+        MLT_CTS_INFORMATION_OUT     => mlt_cts_information,
+        MLT_CTS_READOUT_TYPE_OUT    => mlt_cts_readout_type,
+        MLT_CTS_START_READOUT_OUT   => mlt_cts_start_readout,
+        MLT_CTS_DATA_IN             => mlt_cts_data,
+        MLT_CTS_DATAREADY_IN        => mlt_cts_dataready,
+        MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished,
+        MLT_CTS_READ_OUT            => mlt_cts_read,
+        MLT_CTS_LENGTH_IN           => mlt_cts_length,
+        MLT_CTS_ERROR_PATTERN_IN    => mlt_cts_error_pattern,
+        MLT_FEE_DATA_OUT            => mlt_fee_data,
+        MLT_FEE_DATAREADY_OUT       => mlt_fee_dataready,
+        MLT_FEE_READ_IN             => mlt_fee_read,
+        MLT_FEE_STATUS_BITS_OUT     => mlt_fee_status,
+        MLT_FEE_BUSY_OUT            => mlt_fee_busy,
+        DEBUG_OUT                   => open
+      );
+  end generate real_ipu_gen;
+
+  dummy_ipu_gen : if (USE_EXTERNAL_TRBNET_DUMMY = 1) generate
+    ipu_mult : entity work.gbe_ipu_multiplexer
+    generic map(
+      DO_SIMULATION       => DO_SIMULATION,
+      INCLUDE_DEBUG       => INCLUDE_DEBUG,
+      LINK_HAS_READOUT    => LINK_HAS_READOUT,
+      NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS
+    )
+    port map(
+      CLK_SYS_IN                  => CLK_SYS_IN,
+      RESET                       => RESET,
+      CTS_NUMBER_IN               => local_cts_number,
+      CTS_CODE_IN                 => local_cts_code,
+      CTS_INFORMATION_IN          => local_cts_information,
+      CTS_READOUT_TYPE_IN         => local_cts_readout_type,
+      CTS_START_READOUT_IN        => local_cts_start_readout,
+      CTS_DATA_OUT                => open,
+      CTS_DATAREADY_OUT           => open,
+      CTS_READOUT_FINISHED_OUT    => local_cts_readout_finished,
+      CTS_READ_IN                 => '1',
+      CTS_LENGTH_OUT              => open,
+      CTS_ERROR_PATTERN_OUT       => local_cts_status_bits,
+      FEE_DATA_IN                 => local_fee_data,
+      FEE_DATAREADY_IN            => local_fee_dataready,
+      FEE_READ_OUT                => local_fee_read,
+      FEE_STATUS_BITS_IN          => local_fee_status_bits,
+      FEE_BUSY_IN                 => local_fee_busy,
+      MLT_CTS_NUMBER_OUT          => mlt_cts_number,
+      MLT_CTS_CODE_OUT            => mlt_cts_code,
+      MLT_CTS_INFORMATION_OUT     => mlt_cts_information,
+      MLT_CTS_READOUT_TYPE_OUT    => mlt_cts_readout_type,
+      MLT_CTS_START_READOUT_OUT   => mlt_cts_start_readout,
+      MLT_CTS_DATA_IN             => mlt_cts_data,
+      MLT_CTS_DATAREADY_IN        => mlt_cts_dataready,
+      MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished,
+      MLT_CTS_READ_OUT            => mlt_cts_read,
+      MLT_CTS_LENGTH_IN           => mlt_cts_length,
+      MLT_CTS_ERROR_PATTERN_IN    => mlt_cts_error_pattern,
+      MLT_FEE_DATA_OUT            => mlt_fee_data,
+      MLT_FEE_DATAREADY_OUT       => mlt_fee_dataready,
+      MLT_FEE_READ_IN             => mlt_fee_read,
+      MLT_FEE_STATUS_BITS_OUT     => mlt_fee_status,
+      MLT_FEE_BUSY_OUT            => mlt_fee_busy,
+      DEBUG_OUT                   => open
+    );
+
+    dummy : entity work.gbe_ipu_dummy
+    generic map(
+      DO_SIMULATION    => DO_SIMULATION,
+      FIXED_SIZE_MODE  => FIXED_SIZE_MODE,
+      INCREMENTAL_MODE => INCREMENTAL_MODE,
+      FIXED_SIZE       => FIXED_SIZE,
+      UP_DOWN_MODE     => UP_DOWN_MODE,
+      UP_DOWN_LIMIT    => UP_DOWN_LIMIT,
+      FIXED_DELAY_MODE => FIXED_DELAY_MODE,
+      FIXED_DELAY      => FIXED_DELAY
+    )
+    port map(
+      clk                     => CLK_SYS_IN,
+      rst                     => RESET,
+      GBE_READY_IN            => all_links_ready,
+      CFG_EVENT_SIZE_IN       => dummy_event,
+      CFG_TRIGGERED_MODE_IN   => '0',
+      TRIGGER_IN              => TRIGGER_IN,
+      CTS_NUMBER_OUT          => local_cts_number,
+      CTS_CODE_OUT            => local_cts_code,
+      CTS_INFORMATION_OUT     => local_cts_information,
+      CTS_READOUT_TYPE_OUT    => local_cts_readout_type,
+      CTS_START_READOUT_OUT   => local_cts_start_readout,
+      CTS_DATA_IN             => (others => '0'),
+      CTS_DATAREADY_IN        => '0',
+      CTS_READOUT_FINISHED_IN => local_cts_readout_finished,
+      CTS_READ_OUT            => open,
+      CTS_LENGTH_IN           => (others => '0'),
+      CTS_ERROR_PATTERN_IN    => local_cts_status_bits,
+      -- Data payload interface
+      FEE_DATA_OUT            => local_fee_data,
+      FEE_DATAREADY_OUT       => local_fee_dataready,
+      FEE_READ_IN             => local_fee_read,
+      FEE_STATUS_BITS_OUT     => local_fee_status_bits,
+      FEE_BUSY_OUT            => local_fee_busy
+    );
+
+    -- handler for triggers
+    DUMMY_HANDLER : entity work.trb_net16_gbe_ipu_interface
+    port map(
+      CLK_IPU                  => CLK_SYS_IN,
+      CLK_GBE                  => CLK_125_IN,
+      RESET                    => RESET,
+      --Event information coming from CTS
+      CTS_NUMBER_IN            => CTS_NUMBER_IN,
+      CTS_CODE_IN              => CTS_CODE_IN,
+      CTS_INFORMATION_IN       => CTS_INFORMATION_IN,
+      CTS_READOUT_TYPE_IN      => CTS_READOUT_TYPE_IN,
+      CTS_START_READOUT_IN     => CTS_START_READOUT_IN,
+      --Information sent to CTS
+      --status data, equipped with DHDR
+      CTS_DATA_OUT             => CTS_DATA_OUT,
+      CTS_DATAREADY_OUT        => CTS_DATAREADY_OUT,
+      CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
+      CTS_READ_IN              => CTS_READ_IN,
+      CTS_LENGTH_OUT           => CTS_LENGTH_OUT,
+      CTS_ERROR_PATTERN_OUT    => CTS_ERROR_PATTERN_OUT,
+      -- Data from Frontends
+      FEE_DATA_IN              => FEE_DATA_IN,
+      FEE_DATAREADY_IN         => FEE_DATAREADY_IN,
+      FEE_READ_OUT             => FEE_READ_OUT,
+      FEE_STATUS_BITS_IN       => FEE_STATUS_BITS_IN,
+      FEE_BUSY_IN              => FEE_BUSY_IN,
+      -- slow control interface
+      START_CONFIG_OUT         => open,
+      BANK_SELECT_OUT          => open,
+      CONFIG_DONE_IN           => '1',
+      DATA_GBE_ENABLE_IN       => '1',
+      DATA_IPU_ENABLE_IN       => '1',
+      MULT_EVT_ENABLE_IN       => '1',
+      MAX_SUBEVENT_SIZE_IN     => (others => '0'),
+      MAX_QUEUE_SIZE_IN        => (others => '0'),
+      MAX_SUBS_IN_QUEUE_IN     => (others => '0'),
+      MAX_SINGLE_SUB_SIZE_IN   => (others => '0'),
+      READOUT_CTR_IN           => (others => '0'),
+      READOUT_CTR_VALID_IN     => '0',
+      CFG_AUTO_THROTTLE_IN     => '0',
+      CFG_THROTTLE_PAUSE_IN    => (others => '0'),
+      -- PacketConstructor interface
+      PC_WR_EN_OUT             => open,
+      PC_DATA_OUT              => open,
+      PC_READY_IN              => '1',
+      PC_SOS_OUT               => open,
+      PC_EOS_OUT               => open,
+      PC_EOQ_OUT               => open,
+      PC_SUB_SIZE_OUT          => open,
+      PC_TRIG_NR_OUT           => open,
+      PC_TRIGGER_TYPE_OUT      => open,
+      MONITOR_OUT              => open,
+      DEBUG_OUT                => open
+    );
+  end generate dummy_ipu_gen;
+
+  SETUP : gbe_setup
+  port map(
+    CLK                          => CLK_SYS_IN,
+    RESET                        => RESET,
+    -- interface to regio bus
+    BUS_ADDR_IN                  => BUS_REG_RX.addr(7 downto 0),
+    BUS_DATA_IN                  => BUS_REG_RX.data,
+    BUS_DATA_OUT                 => BUS_REG_TX.data,
+    BUS_WRITE_EN_IN              => BUS_REG_RX.write,
+    BUS_READ_EN_IN               => BUS_REG_RX.read,
+    BUS_ACK_OUT                  => BUS_REG_TX.ack,
+    -- output to gbe_buf
+    GBE_SUBEVENT_ID_OUT          => cfg_subevent_id,
+    GBE_SUBEVENT_DEC_OUT         => cfg_subevent_dec,
+    GBE_QUEUE_DEC_OUT            => cfg_queue_dec,
+    GBE_MAX_FRAME_OUT            => cfg_max_frame,
+    GBE_USE_GBE_OUT              => cfg_gbe_enable,
+    GBE_USE_TRBNET_OUT           => cfg_ipu_enable,
+    GBE_USE_MULTIEVENTS_OUT      => cfg_mult_enable,
+    GBE_READOUT_CTR_OUT          => cfg_readout_ctr,
+    GBE_READOUT_CTR_VALID_OUT    => cfg_readout_ctr_valid,
+    GBE_ALLOW_RX_OUT             => cfg_allow_rx,
+    GBE_ADDITIONAL_HDR_OUT       => cfg_additional_hdr,
+    GBE_INSERT_TTYPE_OUT         => cfg_insert_ttype,
+    GBE_SOFT_RESET_OUT           => cfg_soft_rst,
+    GBE_MAX_REPLY_OUT            => cfg_max_reply,
+    GBE_MAX_SUB_OUT              => cfg_max_sub,
+    GBE_MAX_QUEUE_OUT            => cfg_max_queue,
+    GBE_MAX_SUBS_IN_QUEUE_OUT    => cfg_max_subs_in_queue,
+    GBE_MAX_SINGLE_SUB_OUT       => cfg_max_single_sub,
+    GBE_AUTOTHROTTLE_OUT         => cfg_autothrottle,
+    GBE_THROTTLE_PAUSE_OUT       => cfg_throttle_pause,
+    MONITOR_RX_BYTES_IN          => sum_rx_bytes,
+    MONITOR_RX_FRAMES_IN         => sum_rx_frames,
+    MONITOR_TX_BYTES_IN          => sum_tx_bytes,
+    MONITOR_TX_FRAMES_IN         => sum_tx_frames,
+    MONITOR_TX_PACKETS_IN        => sum_tx_packets,
+    MONITOR_DROPPED_IN           => sum_dropped,
+    MONITOR_SELECT_REC_IN        => (others => '0'),
+    MONITOR_SELECT_REC_BYTES_IN  => (others => '0'),
+    MONITOR_SELECT_SENT_BYTES_IN => (others => '0'),
+    MONITOR_SELECT_SENT_IN       => (others => '0'),
+    MONITOR_SELECT_DROP_IN_IN    => (others => '0'),
+    MONITOR_SELECT_DROP_OUT_IN   => (others => '0'),
+    MONITOR_SELECT_GEN_DBG_IN    => monitor_gen_dbg,
+    MONITOR_IP_IN                => my_ip,
+    DUMMY_EVENT_SIZE_OUT         => dummy_event,
+    DUMMY_TRIGGERED_MODE_OUT     => dummy_mode,
+    DATA_HIST_IN                 => (others => (others => '0')),
+    SCTRL_HIST_IN                => (others => (others => '0'))
+  );
+
+  NOSCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL = "0000") generate
+    GSC_INIT_DATAREADY_OUT  <= '0';
+    GSC_INIT_DATA_OUT       <= (others => '0');
+    GSC_INIT_PACKET_NUM_OUT <= (others => '0');
+    GSC_REPLY_READ_OUT      <= '1';
+    mlt_gsc_clk             <= (others => '0');
+    mlt_gsc_init_read       <= (others => '0');
+    mlt_gsc_reply_dataready <= (others => '0');
+    mlt_gsc_reply_data      <= (others => '0');
+    mlt_gsc_reply_packet    <= (others => '0');
+    mlt_gsc_busy            <= (others => '0');
+  end generate NOSCTRL_MAP_GEN;
+
+  SCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL /= "0000") generate
+    ACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL(0) = '1') generate
+      mlt_gsc_clk              <= GSC_CLK_IN;
+      GSC_INIT_DATAREADY_OUT   <= mlt_gsc_init_dataready;
+      GSC_INIT_DATA_OUT        <= mlt_gsc_init_data;
+      GSC_INIT_PACKET_NUM_OUT  <= mlt_gsc_init_packet;
+      mlt_gsc_init_read        <= GSC_INIT_READ_IN;
+      mlt_gsc_reply_dataready  <= GSC_REPLY_DATAREADY_IN;
+      mlt_gsc_reply_data       <= GSC_REPLY_DATA_IN;
+      mlt_gsc_reply_packet     <= GSC_REPLY_PACKET_NUM_IN;
+      GSC_REPLY_READ_OUT       <= mlt_gsc_reply_read;
+      mlt_gsc_busy             <= GSC_BUSY_IN;
+    end generate ACTIVE_MAP_GEN;
+
+    INACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL(0) = '0') generate
+      mlt_gsc_clk              <= '0';
+      mlt_gsc_init_read        <= '0';
+      mlt_gsc_reply_dataready  <= '0';
+      mlt_gsc_reply_data       <= (others => '0');
+      mlt_gsc_reply_packet     <= (others => '0');
+      mlt_gsc_busy             <= '0';
+    end generate INACTIVE_MAP_GEN;
+  end generate SCTRL_MAP_GEN;
+
+  sum_rx_bytes   <= monitor_rx_bytes;
+  sum_rx_frames  <= monitor_rx_frames;
+  sum_tx_bytes   <= monitor_tx_bytes;
+  sum_tx_frames  <= monitor_tx_frames;
+  sum_tx_packets <= monitor_tx_packets;
+  sum_dropped    <= monitor_dropped;
+
+end architecture RTL;
diff --git a/gbe_trb_ecp5/media/ecp5-5g/pmi_ram_dpEbnonessdn208256208256p138702ef.ngo b/gbe_trb_ecp5/media/ecp5-5g/pmi_ram_dpEbnonessdn208256208256p138702ef.ngo
new file mode 100644
index 0000000..43684e4
Binary files /dev/null and b/gbe_trb_ecp5/media/ecp5-5g/pmi_ram_dpEbnonessdn208256208256p138702ef.ngo differ
diff --git a/gbe_trb_ecp5/media/ecp5-5g/serdes_gbe.lpc b/gbe_trb_ecp5/media/ecp5-5g/serdes_gbe.lpc
new file mode 100644
index 0000000..5aac97f
--- /dev/null
+++ b/gbe_trb_ecp5/media/ecp5-5g/serdes_gbe.lpc
@@ -0,0 +1,97 @@
+[Device]
+Family=ecp5um5g
+OperatingCondition=COM
+Package=CABGA381
+PartName=LFE5UM5G-85F-8BG381C
+PartType=LFE5UM5G-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=PCS
+CoreRevision=8.2
+CoreStatus=Demo
+CoreType=LPM
+Date=06/27/2022
+ModuleName=serdes_gbe
+ParameterFileVersion=1.0
+SourceFormat=vhdl
+Time=13:46:14
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+;ACHARA=0 00H
+;ACHARB=0 00H
+;ACHARM=0 00H
+;RXMCAENABLE=Disabled
+CDRLOLACTION=Full Recalibration
+CDRLOLRANGE=3
+CDR_MAX_RATE=1.25
+CDR_MULT=10X
+CDR_REF_RATE=125.0000
+CH_MODE=Rx and Tx
+Destination=Synplicity
+EDIF=1
+Expression=BusA(0 to 7)
+IO=0
+IO_TYPE=SGMII
+LEQ=0
+LOOPBACK=Disabled
+LOSPORT=Enabled
+NUM_CHS=1
+Order=Big Endian [MSB:LSB]
+PPORT_RX_RDY=Disabled
+PPORT_TX_RDY=Disabled
+PROTOCOL=SGMII
+PWAIT_RX_RDY=3000
+PWAIT_TX_RDY=3000
+RCSRC=Disabled
+REFCLK_RATE=125.0000
+RSTSEQSEL=Disabled
+RX8B10B=Enabled
+RXCOMMAA=1010000011
+RXCOMMAB=0101111100
+RXCOMMAM=1111111111
+RXCOUPLING=AC
+RXCTC=Disabled
+RXCTCBYTEN=0 00H
+RXCTCBYTEN1=0 00H
+RXCTCBYTEN2=0 00H
+RXCTCBYTEN3=0 00H
+RXCTCMATCHPATTERN=M1-S1
+RXDIFFTERM=50 ohms
+RXFIFO_ENABLE=Enabled
+RXINVPOL=Non-invert
+RXLDR=Off
+RXLOSTHRESHOLD=4
+RXLSM=Enabled
+RXSC=K28P5
+RXWA=Barrel Shift
+RX_DATA_WIDTH=8/10-Bit
+RX_FICLK_RATE=125.0000
+RX_LINE_RATE=1.2500
+RX_RATE_DIV=Full Rate
+SCIPORT=Disabled
+SOFTLOL=Enabled
+TX8B10B=Enabled
+TXAMPLITUDE=1000
+TXDEPOST=Disabled
+TXDEPRE=Disabled
+TXDIFFTERM=50 ohms
+TXFIFO_ENABLE=Enabled
+TXINVPOL=Non-invert
+TXLDR=Off
+TXPLLLOLTHRESHOLD=1
+TXPLLMULT=10X
+TX_DATA_WIDTH=8/10-Bit
+TX_FICLK_RATE=125.0000
+TX_LINE_RATE=1.2500
+TX_MAX_RATE=1.25
+TX_RATE_DIV=Full Rate
+VHDL=1
+Verilog=0
+[FilesGenerated]
+serdes_gbe.pp=pp
+serdes_gbe.sym=sym
+serdes_gbe.tft=tft
+serdes_gbe.txt=pcs_module
+[SYSTEMPNR]
+LN0=DCU0_CH0
diff --git a/gbe_trb_ecp5/media/ecp5-5g/serdes_gbe.vhd b/gbe_trb_ecp5/media/ecp5-5g/serdes_gbe.vhd
new file mode 100644
index 0000000..4947ba9
--- /dev/null
+++ b/gbe_trb_ecp5/media/ecp5-5g/serdes_gbe.vhd
@@ -0,0 +1,352 @@
+
+--
+-- Verific VHDL Description of module DCUA
+--
+
+-- DCUA is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module serdes_gbesll_core
+--
+
+-- serdes_gbesll_core is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module serdes_gbe
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+library ecp5um ;
+use ecp5um.components.all ;
+
+entity serdes_gbe is
+    port (hdoutp: out std_logic;
+        hdoutn: out std_logic;
+        hdinp: in std_logic;
+        hdinn: in std_logic;
+        rxrefclk: in std_logic;
+        rx_pclk: out std_logic;
+        txi_clk: in std_logic;
+        tx_pclk: out std_logic;
+        txdata: in std_logic_vector(7 downto 0);
+        tx_k: in std_logic_vector(0 downto 0);
+        xmit: in std_logic_vector(0 downto 0);
+        tx_disp_correct: in std_logic_vector(0 downto 0);
+        rxdata: out std_logic_vector(7 downto 0);
+        rx_k: out std_logic_vector(0 downto 0);
+        rx_disp_err: out std_logic_vector(0 downto 0);
+        rx_cv_err: out std_logic_vector(0 downto 0);
+        signal_detect_c: in std_logic;
+        rx_los_low_s: out std_logic;
+        lsm_status_s: out std_logic;
+        rx_cdr_lol_s: out std_logic;
+        tx_pcs_rst_c: in std_logic;
+        rx_pcs_rst_c: in std_logic;
+        rx_serdes_rst_c: in std_logic;
+        tx_pwrup_c: in std_logic;
+        rx_pwrup_c: in std_logic;
+        rst_dual_c: in std_logic;
+        serdes_rst_dual_c: in std_logic;
+        serdes_pdb: in std_logic;
+        tx_serdes_rst_c: in std_logic;
+        pll_refclki: in std_logic;
+        sli_rst: in std_logic;
+        pll_lol: out std_logic
+    );
+    
+end entity serdes_gbe;
+
+architecture v1 of serdes_gbe is 
+    component serdes_gbesll_core is
+        generic (PPROTOCOL: string := "SGMII";
+            PLOL_SETTING: integer := 1;
+            PDYN_RATE_CTRL: string := "DISABLED";
+            PPCIE_MAX_RATE: string := "1.25";
+            PDIFF_VAL_LOCK: integer := 20;
+            PDIFF_VAL_UNLOCK: integer := 131;
+            PPCLK_TC: integer := 65536;
+            PDIFF_DIV11_VAL_LOCK: integer := 0;
+            PDIFF_DIV11_VAL_UNLOCK: integer := 0;
+            PPCLK_DIV11_TC: integer := 0);
+        port (sli_rst: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00g/data/sll_core_template.v(125)
+            sli_refclk: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00g/data/sll_core_template.v(126)
+            sli_pclk: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00g/data/sll_core_template.v(127)
+            sli_div2_rate: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00g/data/sll_core_template.v(128)
+            sli_div11_rate: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00g/data/sll_core_template.v(129)
+            sli_gear_mode: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00g/data/sll_core_template.v(130)
+            sli_cpri_mode: in std_logic_vector(2 downto 0);   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00g/data/sll_core_template.v(131)
+            sli_pcie_mode: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00g/data/sll_core_template.v(132)
+            slo_plol: out std_logic   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00g/data/sll_core_template.v(135)
+        );
+        
+    end component serdes_gbesll_core; -- syn_black_box=1    -- /opt/lattice/diamond/3.12/ispfpga/sa5p00g/data/sll_core_template.v(107)
+    signal n48,n47,n1,n2,n3,n4,rx_pclk_c,n5,n6,n7,n8,tx_pclk_c,n9,
+        n10,n11,n12,n13,n14,n15,n16,n17,n18,n19,n20,n21,n22,n23,
+        n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,
+        n38,n39,n40,n41,n42,n43,n44,n45,n46,n49,n115,n114,n50,n51,
+        n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,
+        n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,
+        n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,
+        n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n105,n106,
+        n107,n108,n109,n110,n111,n112,n113,\_Z\,n117,n116,gnd,pwr : std_logic; 
+    attribute LOC : string;
+    attribute LOC of DCU0_inst : label is "DCU0";
+    attribute CHAN : string;
+    attribute CHAN of DCU0_inst : label is "CH0";
+begin
+    rx_pclk <= rx_pclk_c;
+    tx_pclk <= tx_pclk_c;
+    DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
+        D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
+        D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+        D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
+        D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b0",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0",
+        CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b1",CH0_PRBS_SELECTION=>"0b0",
+        CH0_GE_AN_ENABLE=>"0b1",CH0_PRBS_LOCK=>"0b0",CH0_PRBS_ENABLE=>"0b0",
+        CH0_ENABLE_CG_ALIGN=>"0b1",CH0_TX_GEAR_MODE=>"0b0",CH0_RX_GEAR_MODE=>"0b0",
+        CH0_PCS_DET_TIME_SEL=>"0b00",CH0_PCIE_EI_EN=>"0b0",CH0_TX_GEAR_BYPASS=>"0b0",
+        CH0_ENC_BYPASS=>"0b0",CH0_SB_BYPASS=>"0b0",CH0_RX_SB_BYPASS=>"0b0",
+        CH0_WA_BYPASS=>"0b0",CH0_DEC_BYPASS=>"0b0",CH0_CTC_BYPASS=>"0b1",
+        CH0_RX_GEAR_BYPASS=>"0b0",CH0_LSM_DISABLE=>"0b0",CH0_MATCH_2_ENABLE=>"0b0",
+        CH0_MATCH_4_ENABLE=>"0b0",CH0_MIN_IPG_CNT=>"0b11",CH0_CC_MATCH_1=>"0x000",
+        CH0_CC_MATCH_2=>"0x000",CH0_CC_MATCH_3=>"0x000",CH0_CC_MATCH_4=>"0x000",
+        CH0_UDF_COMMA_MASK=>"0x3ff",CH0_UDF_COMMA_A=>"0x283",CH0_UDF_COMMA_B=>"0x17C",
+        CH0_RX_DCO_CK_DIV=>"0b010",CH0_RCV_DCC_EN=>"0b0",CH0_TPWDNB=>"0b1",
+        CH0_RATE_MODE_TX=>"0b0",CH0_RTERM_TX=>"0d19",CH0_TX_CM_SEL=>"0b00",
+        CH0_TDRV_PRE_EN=>"0b0",CH0_TDRV_SLICE0_SEL=>"0b01",CH0_TDRV_SLICE1_SEL=>"0b00",
+        CH0_TDRV_SLICE2_SEL=>"0b01",CH0_TDRV_SLICE3_SEL=>"0b01",CH0_TDRV_SLICE4_SEL=>"0b01",
+        CH0_TDRV_SLICE5_SEL=>"0b00",CH0_TDRV_SLICE0_CUR=>"0b011",CH0_TDRV_SLICE1_CUR=>"0b000",
+        CH0_TDRV_SLICE2_CUR=>"0b11",CH0_TDRV_SLICE3_CUR=>"0b11",CH0_TDRV_SLICE4_CUR=>"0b11",
+        CH0_TDRV_SLICE5_CUR=>"0b00",CH0_TDRV_DAT_SEL=>"0b00",CH0_TX_DIV11_SEL=>"0b0",
+        CH0_RPWDNB=>"0b1",CH0_RATE_MODE_RX=>"0b0",CH0_RX_DIV11_SEL=>"0b0",
+        CH0_SEL_SD_RX_CLK=>"0b1",CH0_FF_RX_H_CLK_EN=>"0b0",CH0_FF_RX_F_CLK_DIS=>"0b0",
+        CH0_FF_TX_H_CLK_EN=>"0b0",CH0_FF_TX_F_CLK_DIS=>"0b0",CH0_TDRV_POST_EN=>"0b0",
+        CH0_TX_POST_SIGN=>"0b0",CH0_TX_PRE_SIGN=>"0b0",CH0_REQ_LVL_SET=>"0b00",
+        CH0_REQ_EN=>"0b1",CH0_RTERM_RX=>"0d22",CH0_RXTERM_CM=>"0b11",CH0_PDEN_SEL=>"0b1",
+        CH0_RXIN_CM=>"0b11",CH0_LEQ_OFFSET_SEL=>"0b0",CH0_LEQ_OFFSET_TRIM=>"0b000",
+        CH0_RLOS_SEL=>"0b1",CH0_RX_LOS_LVL=>"0b100",CH0_RX_LOS_CEQ=>"0b11",
+        CH0_RX_LOS_HYST_EN=>"0b0",CH0_RX_LOS_EN=>"0b1",CH0_LDR_RX2CORE_SEL=>"0b0",
+        CH0_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"1.25",CH0_CDR_MAX_RATE=>"1.25",
+        CH0_TXAMPLITUDE=>"0d1000",CH0_TXDEPRE=>"DISABLED",CH0_TXDEPOST=>"DISABLED",
+        CH0_PROTOCOL=>"SGMII",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00",
+        D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000",
+        D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH0_CDR_CNT4SEL=>"0b00",
+        CH0_CDR_CNT8SEL=>"0b00",CH0_DCOATDCFG=>"0b00",CH0_DCOATDDLY=>"0b00",
+        CH0_DCOBYPSATD=>"0b1",CH0_DCOCALDIV=>"0b001",CH0_DCOCTLGI=>"0b010",
+        CH0_DCODISBDAVOID=>"0b0",CH0_DCOFLTDAC=>"0b01",CH0_DCOFTNRG=>"0b110",
+        CH0_DCOIOSTUNE=>"0b000",CH0_DCOITUNE=>"0b00",CH0_DCOITUNE4LSB=>"0b111",
+        CH0_DCOIUPDNX2=>"0b1",CH0_DCONUOFLSB=>"0b101",CH0_DCOSCALEI=>"0b00",
+        CH0_DCOSTARTVAL=>"0b000",CH0_DCOSTEP=>"0b00",CH0_BAND_THRESHOLD=>"0d0",
+        CH0_AUTO_FACQ_EN=>"0b1",CH0_AUTO_CALIB_EN=>"0b1",CH0_CALIB_CK_MODE=>"0b0",
+        CH0_REG_BAND_OFFSET=>"0d0",CH0_REG_BAND_SEL=>"0d0",CH0_REG_IDAC_SEL=>"0d0",
+        CH0_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00",
+        D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000",
+        D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101",
+        D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH0_RX_RATE_SEL=>"0d8",
+        D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b010",D_PLL_LOL_SET=>"0b01",
+        D_RG_EN=>"0b0",D_RG_SET=>"0b00")
+     port map (CH0_HDINP=>hdinp,CH1_HDINP=>n115,CH0_HDINN=>hdinn,CH1_HDINN=>n115,
+    D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47,
+    CH0_RX_REFCLK=>rxrefclk,CH1_RX_REFCLK=>n115,CH0_FF_RXI_CLK=>rx_pclk_c,
+    CH1_FF_RXI_CLK=>n114,CH0_FF_TXI_CLK=>txi_clk,CH1_FF_TXI_CLK=>n114,CH0_FF_EBRD_CLK=>n48,
+    CH1_FF_EBRD_CLK=>n114,CH0_FF_TX_D_0=>txdata(0),CH1_FF_TX_D_0=>n115,CH0_FF_TX_D_1=>txdata(1),
+    CH1_FF_TX_D_1=>n115,CH0_FF_TX_D_2=>txdata(2),CH1_FF_TX_D_2=>n115,CH0_FF_TX_D_3=>txdata(3),
+    CH1_FF_TX_D_3=>n115,CH0_FF_TX_D_4=>txdata(4),CH1_FF_TX_D_4=>n115,CH0_FF_TX_D_5=>txdata(5),
+    CH1_FF_TX_D_5=>n115,CH0_FF_TX_D_6=>txdata(6),CH1_FF_TX_D_6=>n115,CH0_FF_TX_D_7=>txdata(7),
+    CH1_FF_TX_D_7=>n115,CH0_FF_TX_D_8=>tx_k(0),CH1_FF_TX_D_8=>n115,CH0_FF_TX_D_9=>n47,
+    CH1_FF_TX_D_9=>n115,CH0_FF_TX_D_10=>xmit(0),CH1_FF_TX_D_10=>n115,CH0_FF_TX_D_11=>tx_disp_correct(0),
+    CH1_FF_TX_D_11=>n115,CH0_FF_TX_D_12=>n115,CH1_FF_TX_D_12=>n115,CH0_FF_TX_D_13=>n115,
+    CH1_FF_TX_D_13=>n115,CH0_FF_TX_D_14=>n115,CH1_FF_TX_D_14=>n115,CH0_FF_TX_D_15=>n115,
+    CH1_FF_TX_D_15=>n115,CH0_FF_TX_D_16=>n115,CH1_FF_TX_D_16=>n115,CH0_FF_TX_D_17=>n115,
+    CH1_FF_TX_D_17=>n115,CH0_FF_TX_D_18=>n115,CH1_FF_TX_D_18=>n115,CH0_FF_TX_D_19=>n115,
+    CH1_FF_TX_D_19=>n115,CH0_FF_TX_D_20=>n115,CH1_FF_TX_D_20=>n115,CH0_FF_TX_D_21=>n47,
+    CH1_FF_TX_D_21=>n115,CH0_FF_TX_D_22=>n115,CH1_FF_TX_D_22=>n115,CH0_FF_TX_D_23=>n115,
+    CH1_FF_TX_D_23=>n115,CH0_FFC_EI_EN=>n47,CH1_FFC_EI_EN=>n115,CH0_FFC_PCIE_DET_EN=>n47,
+    CH1_FFC_PCIE_DET_EN=>n115,CH0_FFC_PCIE_CT=>n47,CH1_FFC_PCIE_CT=>n115,
+    CH0_FFC_SB_INV_RX=>n115,CH1_FFC_SB_INV_RX=>n115,CH0_FFC_ENABLE_CGALIGN=>n115,
+    CH1_FFC_ENABLE_CGALIGN=>n115,CH0_FFC_SIGNAL_DETECT=>signal_detect_c,CH1_FFC_SIGNAL_DETECT=>n115,
+    CH0_FFC_FB_LOOPBACK=>n47,CH1_FFC_FB_LOOPBACK=>n115,CH0_FFC_SB_PFIFO_LP=>n47,
+    CH1_FFC_SB_PFIFO_LP=>n115,CH0_FFC_PFIFO_CLR=>n47,CH1_FFC_PFIFO_CLR=>n115,
+    CH0_FFC_RATE_MODE_RX=>n47,CH1_FFC_RATE_MODE_RX=>n115,CH0_FFC_RATE_MODE_TX=>n47,
+    CH1_FFC_RATE_MODE_TX=>n115,CH0_FFC_DIV11_MODE_RX=>n47,CH1_FFC_DIV11_MODE_RX=>n115,
+    CH0_FFC_DIV11_MODE_TX=>n47,CH1_FFC_DIV11_MODE_TX=>n115,CH0_FFC_RX_GEAR_MODE=>n47,
+    CH1_FFC_RX_GEAR_MODE=>n115,CH0_FFC_TX_GEAR_MODE=>n47,CH1_FFC_TX_GEAR_MODE=>n115,
+    CH0_FFC_LDR_CORE2TX_EN=>n115,CH1_FFC_LDR_CORE2TX_EN=>n115,CH0_FFC_LANE_TX_RST=>tx_pcs_rst_c,
+    CH1_FFC_LANE_TX_RST=>n115,CH0_FFC_LANE_RX_RST=>rx_pcs_rst_c,CH1_FFC_LANE_RX_RST=>n115,
+    CH0_FFC_RRST=>rx_serdes_rst_c,CH1_FFC_RRST=>n115,CH0_FFC_TXPWDNB=>tx_pwrup_c,
+    CH1_FFC_TXPWDNB=>n115,CH0_FFC_RXPWDNB=>rx_pwrup_c,CH1_FFC_RXPWDNB=>n115,
+    CH0_LDR_CORE2TX=>n115,CH1_LDR_CORE2TX=>n115,D_SCIWDATA0=>n115,D_SCIWDATA1=>n115,
+    D_SCIWDATA2=>n115,D_SCIWDATA3=>n115,D_SCIWDATA4=>n115,D_SCIWDATA5=>n115,
+    D_SCIWDATA6=>n115,D_SCIWDATA7=>n115,D_SCIADDR0=>n115,D_SCIADDR1=>n115,
+    D_SCIADDR2=>n115,D_SCIADDR3=>n115,D_SCIADDR4=>n115,D_SCIADDR5=>n115,
+    D_SCIENAUX=>n115,D_SCISELAUX=>n115,CH0_SCIEN=>n115,CH1_SCIEN=>n115,CH0_SCISEL=>n115,
+    CH1_SCISEL=>n115,D_SCIRD=>n115,D_SCIWSTN=>n115,D_CYAWSTN=>n115,D_FFC_SYNC_TOGGLE=>n115,
+    D_FFC_DUAL_RST=>rst_dual_c,D_FFC_MACRO_RST=>serdes_rst_dual_c,D_FFC_MACROPDB=>serdes_pdb,
+    D_FFC_TRST=>tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n47,CH1_FFC_CDR_EN_BITSLIP=>n115,
+    D_SCAN_ENABLE=>n47,D_SCAN_IN_0=>n47,D_SCAN_IN_1=>n47,D_SCAN_IN_2=>n47,
+    D_SCAN_IN_3=>n47,D_SCAN_IN_4=>n47,D_SCAN_IN_5=>n47,D_SCAN_IN_6=>n47,
+    D_SCAN_IN_7=>n47,D_SCAN_MODE=>n47,D_SCAN_RESET=>n47,D_CIN0=>n47,D_CIN1=>n47,
+    D_CIN2=>n47,D_CIN3=>n47,D_CIN4=>n47,D_CIN5=>n47,D_CIN6=>n47,D_CIN7=>n47,
+    D_CIN8=>n47,D_CIN9=>n47,D_CIN10=>n47,D_CIN11=>n47,CH0_HDOUTP=>hdoutp,
+    CH1_HDOUTP=>n50,CH0_HDOUTN=>hdoutn,CH1_HDOUTN=>n51,D_TXBIT_CLKP_TO_ND=>n1,
+    D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,CH0_FF_RX_F_CLK=>n5,
+    CH1_FF_RX_F_CLK=>n52,CH0_FF_RX_H_CLK=>n6,CH1_FF_RX_H_CLK=>n53,CH0_FF_TX_F_CLK=>n7,
+    CH1_FF_TX_F_CLK=>n54,CH0_FF_TX_H_CLK=>n8,CH1_FF_TX_H_CLK=>n55,CH0_FF_RX_PCLK=>rx_pclk_c,
+    CH1_FF_RX_PCLK=>n56,CH0_FF_TX_PCLK=>tx_pclk_c,CH1_FF_TX_PCLK=>n57,CH0_FF_RX_D_0=>rxdata(0),
+    CH1_FF_RX_D_0=>n58,CH0_FF_RX_D_1=>rxdata(1),CH1_FF_RX_D_1=>n59,CH0_FF_RX_D_2=>rxdata(2),
+    CH1_FF_RX_D_2=>n60,CH0_FF_RX_D_3=>rxdata(3),CH1_FF_RX_D_3=>n61,CH0_FF_RX_D_4=>rxdata(4),
+    CH1_FF_RX_D_4=>n62,CH0_FF_RX_D_5=>rxdata(5),CH1_FF_RX_D_5=>n63,CH0_FF_RX_D_6=>rxdata(6),
+    CH1_FF_RX_D_6=>n64,CH0_FF_RX_D_7=>rxdata(7),CH1_FF_RX_D_7=>n65,CH0_FF_RX_D_8=>rx_k(0),
+    CH1_FF_RX_D_8=>n66,CH0_FF_RX_D_9=>rx_disp_err(0),CH1_FF_RX_D_9=>n67,CH0_FF_RX_D_10=>rx_cv_err(0),
+    CH1_FF_RX_D_10=>n68,CH0_FF_RX_D_11=>n9,CH1_FF_RX_D_11=>n69,CH0_FF_RX_D_12=>n70,
+    CH1_FF_RX_D_12=>n71,CH0_FF_RX_D_13=>n72,CH1_FF_RX_D_13=>n73,CH0_FF_RX_D_14=>n74,
+    CH1_FF_RX_D_14=>n75,CH0_FF_RX_D_15=>n76,CH1_FF_RX_D_15=>n77,CH0_FF_RX_D_16=>n78,
+    CH1_FF_RX_D_16=>n79,CH0_FF_RX_D_17=>n80,CH1_FF_RX_D_17=>n81,CH0_FF_RX_D_18=>n82,
+    CH1_FF_RX_D_18=>n83,CH0_FF_RX_D_19=>n84,CH1_FF_RX_D_19=>n85,CH0_FF_RX_D_20=>n86,
+    CH1_FF_RX_D_20=>n87,CH0_FF_RX_D_21=>n88,CH1_FF_RX_D_21=>n89,CH0_FF_RX_D_22=>n90,
+    CH1_FF_RX_D_22=>n91,CH0_FF_RX_D_23=>n10,CH1_FF_RX_D_23=>n92,CH0_FFS_PCIE_DONE=>n11,
+    CH1_FFS_PCIE_DONE=>n93,CH0_FFS_PCIE_CON=>n12,CH1_FFS_PCIE_CON=>n94,CH0_FFS_RLOS=>rx_los_low_s,
+    CH1_FFS_RLOS=>n95,CH0_FFS_LS_SYNC_STATUS=>lsm_status_s,CH1_FFS_LS_SYNC_STATUS=>n96,
+    CH0_FFS_CC_UNDERRUN=>n13,CH1_FFS_CC_UNDERRUN=>n97,CH0_FFS_CC_OVERRUN=>n14,
+    CH1_FFS_CC_OVERRUN=>n98,CH0_FFS_RXFBFIFO_ERROR=>n15,CH1_FFS_RXFBFIFO_ERROR=>n99,
+    CH0_FFS_TXFBFIFO_ERROR=>n16,CH1_FFS_TXFBFIFO_ERROR=>n100,CH0_FFS_RLOL=>rx_cdr_lol_s,
+    CH1_FFS_RLOL=>n101,CH0_FFS_SKP_ADDED=>n17,CH1_FFS_SKP_ADDED=>n102,CH0_FFS_SKP_DELETED=>n18,
+    CH1_FFS_SKP_DELETED=>n103,CH0_LDR_RX2CORE=>n104,CH1_LDR_RX2CORE=>n105,
+    D_SCIRDATA0=>n106,D_SCIRDATA1=>n107,D_SCIRDATA2=>n108,D_SCIRDATA3=>n109,
+    D_SCIRDATA4=>n110,D_SCIRDATA5=>n111,D_SCIRDATA6=>n112,D_SCIRDATA7=>n113,
+    D_SCIINT=>\_Z\,D_SCAN_OUT_0=>n19,D_SCAN_OUT_1=>n20,D_SCAN_OUT_2=>n21,
+    D_SCAN_OUT_3=>n22,D_SCAN_OUT_4=>n23,D_SCAN_OUT_5=>n24,D_SCAN_OUT_6=>n25,
+    D_SCAN_OUT_7=>n26,D_COUT0=>n27,D_COUT1=>n28,D_COUT2=>n29,D_COUT3=>n30,
+    D_COUT4=>n31,D_COUT5=>n32,D_COUT6=>n33,D_COUT7=>n34,D_COUT8=>n35,D_COUT9=>n36,
+    D_COUT10=>n37,D_COUT11=>n38,D_COUT12=>n39,D_COUT13=>n40,D_COUT14=>n41,
+    D_COUT15=>n42,D_COUT16=>n43,D_COUT17=>n44,D_COUT18=>n45,D_COUT19=>n46,
+    D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n49);
+    n48 <= '1' ;
+    n47 <= '0' ;
+    n1 <= 'Z' ;
+    n2 <= 'Z' ;
+    n3 <= 'Z' ;
+    n4 <= 'Z' ;
+    n5 <= 'Z' ;
+    n6 <= 'Z' ;
+    n7 <= 'Z' ;
+    n8 <= 'Z' ;
+    n9 <= 'Z' ;
+    n10 <= 'Z' ;
+    n11 <= 'Z' ;
+    n12 <= 'Z' ;
+    n13 <= 'Z' ;
+    n14 <= 'Z' ;
+    n15 <= 'Z' ;
+    n16 <= 'Z' ;
+    n17 <= 'Z' ;
+    n18 <= 'Z' ;
+    n19 <= 'Z' ;
+    n20 <= 'Z' ;
+    n21 <= 'Z' ;
+    n22 <= 'Z' ;
+    n23 <= 'Z' ;
+    n24 <= 'Z' ;
+    n25 <= 'Z' ;
+    n26 <= 'Z' ;
+    n27 <= 'Z' ;
+    n28 <= 'Z' ;
+    n29 <= 'Z' ;
+    n30 <= 'Z' ;
+    n31 <= 'Z' ;
+    n32 <= 'Z' ;
+    n33 <= 'Z' ;
+    n34 <= 'Z' ;
+    n35 <= 'Z' ;
+    n36 <= 'Z' ;
+    n37 <= 'Z' ;
+    n38 <= 'Z' ;
+    n39 <= 'Z' ;
+    n40 <= 'Z' ;
+    n41 <= 'Z' ;
+    n42 <= 'Z' ;
+    n43 <= 'Z' ;
+    n44 <= 'Z' ;
+    n45 <= 'Z' ;
+    n46 <= 'Z' ;
+    n49 <= 'Z' ;
+    n115 <= '0' ;
+    n114 <= '1' ;
+    n50 <= 'Z' ;
+    n51 <= 'Z' ;
+    n52 <= 'Z' ;
+    n53 <= 'Z' ;
+    n54 <= 'Z' ;
+    n55 <= 'Z' ;
+    n56 <= 'Z' ;
+    n57 <= 'Z' ;
+    n58 <= 'Z' ;
+    n59 <= 'Z' ;
+    n60 <= 'Z' ;
+    n61 <= 'Z' ;
+    n62 <= 'Z' ;
+    n63 <= 'Z' ;
+    n64 <= 'Z' ;
+    n65 <= 'Z' ;
+    n66 <= 'Z' ;
+    n67 <= 'Z' ;
+    n68 <= 'Z' ;
+    n69 <= 'Z' ;
+    n70 <= 'Z' ;
+    n71 <= 'Z' ;
+    n72 <= 'Z' ;
+    n73 <= 'Z' ;
+    n74 <= 'Z' ;
+    n75 <= 'Z' ;
+    n76 <= 'Z' ;
+    n77 <= 'Z' ;
+    n78 <= 'Z' ;
+    n79 <= 'Z' ;
+    n80 <= 'Z' ;
+    n81 <= 'Z' ;
+    n82 <= 'Z' ;
+    n83 <= 'Z' ;
+    n84 <= 'Z' ;
+    n85 <= 'Z' ;
+    n86 <= 'Z' ;
+    n87 <= 'Z' ;
+    n88 <= 'Z' ;
+    n89 <= 'Z' ;
+    n90 <= 'Z' ;
+    n91 <= 'Z' ;
+    n92 <= 'Z' ;
+    n93 <= 'Z' ;
+    n94 <= 'Z' ;
+    n95 <= 'Z' ;
+    n96 <= 'Z' ;
+    n97 <= 'Z' ;
+    n98 <= 'Z' ;
+    n99 <= 'Z' ;
+    n100 <= 'Z' ;
+    n101 <= 'Z' ;
+    n102 <= 'Z' ;
+    n103 <= 'Z' ;
+    n104 <= 'Z' ;
+    n105 <= 'Z' ;
+    n106 <= 'Z' ;
+    n107 <= 'Z' ;
+    n108 <= 'Z' ;
+    n109 <= 'Z' ;
+    n110 <= 'Z' ;
+    n111 <= 'Z' ;
+    n112 <= 'Z' ;
+    n113 <= 'Z' ;
+    \_Z\ <= 'Z' ;
+    sll_inst: component serdes_gbesll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki,
+            sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd,
+            sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd,
+            sli_pcie_mode=>gnd,slo_plol=>pll_lol);
+    n117 <= '1' ;
+    n116 <= '0' ;
+    gnd <= '0' ;
+    pwr <= '1' ;
+    
+end architecture v1;
+
diff --git a/gbe_trb_ecp5/media/ecp5-5g/serdes_gbe_softlogic.v b/gbe_trb_ecp5/media/ecp5-5g/serdes_gbe_softlogic.v
new file mode 100644
index 0000000..fc7464d
--- /dev/null
+++ b/gbe_trb_ecp5/media/ecp5-5g/serdes_gbe_softlogic.v
@@ -0,0 +1,1060 @@
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2015 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED 
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement. 
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02 
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS         
+// Project               : SLL - Soft Loss Of Lock(LOL) Logic
+// File                  : sll_core.v
+// Title                 : Top-level file for SLL 
+// Dependencies          : 1.
+//                       : 2.
+// Description           : 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : AV
+// Mod. Date             : March 2, 2015
+// Changes Made          : Initial Creation
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.1
+// Author(s)             : AV
+// Mod. Date             : June 8, 2015
+// Changes Made          : Following updates were made 
+//                       : 1. Changed all the PLOL status logic and FSM to run
+//                       :    on sli_refclk. 
+//                       : 2. Added the HB logic for presence of tx_pclk 
+//                       : 3. Changed the lparam assignment scheme for 
+//                       :    simulation purposes. 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.2
+// Author(s)             : AV
+// Mod. Date             : June 24, 2015
+// Changes Made          : Updated the gearing logic for SDI dynamic rate change
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.3
+// Author(s)             : AV
+// Mod. Date             : July 14, 2015
+// Changes Made          : Added the logic for dynamic rate change in CPRI
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.4
+// Author(s)             : AV
+// Mod. Date             : August 21, 2015
+// Changes Made          : Added the logic for dynamic rate change of 5G CPRI & 
+//                         PCIe.
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.5
+// Author(s)             : ES/EB
+// Mod. Date             : March 21, 2017
+// Changes Made          : 1. Added pdiff_sync signal to syncrhonize pcount_diff 
+//                       :    to sli_refclk.
+//                       : 2. Updated terminal count logic for PCIe 5G
+//                       : 3. Modified checking of pcount_diff in SLL state
+//                       :    machine to cover actual count
+//                       :    (from 16-bits to 22-bits)
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.6
+// Author(s)             : ES
+// Mod. Date             : April 19, 2017
+// Changes Made          : 1. Added registered lock and unlock signal from
+//                            pdiff_sync to totally decouple pcount_diff from
+//                            SLL state machine.
+//                       : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI
+//                            is operating @ 4.9125Gbps data rate.
+// =============================================================================
+`timescale 1ns/10ps
+
+module serdes_gbesll_core ( 
+  //Reset and Clock inputs
+  sli_rst,         //Active high asynchronous reset input
+  sli_refclk,      //Refclk input to the Tx PLL
+  sli_pclk,        //Tx pclk output from the PCS
+  
+  //Control inputs
+  sli_div2_rate,   //Divide by 2 control; 0 - Full rate; 1 - Half rate
+  sli_div11_rate,  //Divide by 11 control; 0 - Full rate; 1 - Div by 11
+  sli_gear_mode,   //Gear mode control for PCS; 0 - 8/10; 1- 16/20
+  sli_cpri_mode,   //Mode of operation specific to CPRI protocol
+  sli_pcie_mode,   //Mode of operation specific to PCIe mode (2.5G or 5G)
+  
+  //LOL Output
+  slo_plol         //Tx PLL Loss of Lock output to the user logic
+  );
+  
+// Inputs
+input       sli_rst;
+input       sli_refclk;
+input       sli_pclk;
+input       sli_div2_rate;
+input       sli_div11_rate;
+input       sli_gear_mode;
+input [2:0] sli_cpri_mode;
+input       sli_pcie_mode;
+
+// Outputs
+output      slo_plol;
+
+
+// Parameters
+parameter PPROTOCOL              = "PCIE";     //Protocol selected by the User
+parameter PLOL_SETTING           = 0;          //PLL LOL setting. Possible values are 0,1,2,3
+parameter PDYN_RATE_CTRL         = "DISABLED"; //PCS Dynamic Rate control
+parameter PPCIE_MAX_RATE         = "2.5";      //PCIe max data rate
+parameter PDIFF_VAL_LOCK         = 20;         //Differential count value for Lock
+parameter PDIFF_VAL_UNLOCK       = 39;         //Differential count value for Unlock
+parameter PPCLK_TC               = 65535;      //Terminal count value for counter running on sli_pclk
+parameter PDIFF_DIV11_VAL_LOCK   = 3;          //Differential count value for Lock for SDI Div11
+parameter PDIFF_DIV11_VAL_UNLOCK = 3;          //Differential count value for Unlock for SDI Div11
+parameter PPCLK_DIV11_TC         = 2383;       //Terminal count value (SDI Div11) for counter running on sli_pclk
+
+
+// Local Parameters
+localparam [1:0]  LPLL_LOSS_ST         = 2'b00;       //PLL Loss state
+localparam [1:0]  LPLL_PRELOSS_ST      = 2'b01;       //PLL Pre-Loss state
+localparam [1:0]  LPLL_PRELOCK_ST      = 2'b10;       //PLL Pre-Lock state
+localparam [1:0]  LPLL_LOCK_ST         = 2'b11;       //PLL Lock state
+`ifdef RSL_SIM_MODE
+localparam [15:0] LRCLK_TC             = 16'd63;   //Terminal count value for counter running on sli_refclk
+`else
+localparam [15:0] LRCLK_TC             = 16'd65535;   //Terminal count value for counter running on sli_refclk
+`endif
+localparam [15:0] LRCLK_TC_PUL_WIDTH   = 16'd50;      //Pulse width for the Refclk terminal count pulse
+localparam [7:0]  LHB_WAIT_CNT         = 8'd255;      //Wait count for the Heartbeat signal
+
+// Local Parameters related to the CPRI dynamic modes
+// Terminal count values for the four CPRI modes
+localparam LPCLK_TC_0 = 32768;
+localparam LPCLK_TC_1 = 65536;
+localparam LPCLK_TC_2 = 131072;
+localparam LPCLK_TC_3 = 163840;
+localparam LPCLK_TC_4 = 65536;
+
+// Lock values count values for the four CPRI modes and four PLOL settings (4x5)
+// CPRI rate mode 0                CPRI rate mode 1                   CPRI rate mode 2                    CPRI rate mode 3                     CPRI rate mode 4
+localparam LPDIFF_LOCK_00 = 9;     localparam LPDIFF_LOCK_10 = 19;    localparam LPDIFF_LOCK_20 = 39;     localparam LPDIFF_LOCK_30 = 49;      localparam LPDIFF_LOCK_40 = 19;
+localparam LPDIFF_LOCK_01 = 9;     localparam LPDIFF_LOCK_11 = 19;    localparam LPDIFF_LOCK_21 = 39;     localparam LPDIFF_LOCK_31 = 49;      localparam LPDIFF_LOCK_41 = 19;
+localparam LPDIFF_LOCK_02 = 49;    localparam LPDIFF_LOCK_12 = 98;    localparam LPDIFF_LOCK_22 = 196;    localparam LPDIFF_LOCK_32 = 245;     localparam LPDIFF_LOCK_42 = 98;
+localparam LPDIFF_LOCK_03 = 131;   localparam LPDIFF_LOCK_13 = 262;   localparam LPDIFF_LOCK_23 = 524;    localparam LPDIFF_LOCK_33 = 655;     localparam LPDIFF_LOCK_43 = 262;
+
+// Unlock values count values for the four CPRI modes and four PLOL settings (4x5)
+// CPRI rate mode 0                  CPRI rate mode 1                      CPRI rate mode 2                       CPRI rate mode 3                         CPRI rate mode 4
+localparam LPDIFF_UNLOCK_00 = 19;    localparam LPDIFF_UNLOCK_10 = 39;     localparam LPDIFF_UNLOCK_20 = 78;      localparam LPDIFF_UNLOCK_30 = 98;        localparam LPDIFF_UNLOCK_40 = 39;
+localparam LPDIFF_UNLOCK_01 = 65;    localparam LPDIFF_UNLOCK_11 = 131;    localparam LPDIFF_UNLOCK_21 = 262;     localparam LPDIFF_UNLOCK_31 = 327;       localparam LPDIFF_UNLOCK_41 = 131;
+localparam LPDIFF_UNLOCK_02 = 72;    localparam LPDIFF_UNLOCK_12 = 144;    localparam LPDIFF_UNLOCK_22 = 288;     localparam LPDIFF_UNLOCK_32 = 360;       localparam LPDIFF_UNLOCK_42 = 144;
+localparam LPDIFF_UNLOCK_03 = 196;   localparam LPDIFF_UNLOCK_13 = 393;    localparam LPDIFF_UNLOCK_23 = 786;     localparam LPDIFF_UNLOCK_33 = 983;       localparam LPDIFF_UNLOCK_43 = 393;
+
+// Input and Output reg and wire declarations
+wire       sli_rst;
+wire       sli_refclk;
+wire       sli_pclk;
+wire       sli_div2_rate;
+wire       sli_div11_rate;
+wire       sli_gear_mode;
+wire [2:0] sli_cpri_mode;
+wire       sli_pcie_mode;
+wire       slo_plol;
+
+//-------------- Internal signals reg and wire declarations --------------------
+
+//Signals running on sli_refclk
+reg  [15:0] rcount;           //16-bit Counter
+reg         rtc_pul;          //Terminal count pulse
+reg         rtc_pul_p1;       //Terminal count pulse pipeline
+reg         rtc_ctrl;         //Terminal count pulse control
+
+reg  [7:0]  rhb_wait_cnt;     //Heartbeat wait counter
+
+//Heatbeat synchronization and pipeline registers
+wire        rhb_sync;
+reg         rhb_sync_p2;
+reg         rhb_sync_p1;
+
+//Pipeling registers for dynamic control mode
+wire        rgear;
+wire        rdiv2;
+wire        rdiv11;
+reg         rgear_p1;
+reg         rdiv2_p1;
+reg         rdiv11_p1;
+
+reg         rstat_pclk;        //Pclk presence/absence status
+
+reg  [21:0] rcount_tc;         //Tx_pclk terminal count register
+reg  [15:0] rdiff_comp_lock;   //Differential comparison value for Lock
+reg  [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock
+
+wire        rpcie_mode;        //PCIe mode signal synchronized to refclk
+reg         rpcie_mode_p1;     //PCIe mode pipeline register
+
+wire        rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk
+reg         rcpri_mod_ch_p1;   //CPRI mode change pipeline register
+reg         rcpri_mod_ch_p2;   //CPRI mode change pipeline register
+reg         rcpri_mod_ch_st;   //CPRI mode change status
+
+reg  [1:0]  sll_state;         //Current-state register for LOL FSM
+
+reg         pll_lock;          //PLL Lock signal
+
+//Signals running on sli_pclk
+//Synchronization and pipeline registers
+wire        ppul_sync;
+reg         ppul_sync_p1;
+reg         ppul_sync_p2;
+reg         ppul_sync_p3;
+
+wire        pdiff_sync;
+reg         pdiff_sync_p1;
+   
+reg  [21:0] pcount;            //22-bit counter
+reg  [21:0] pcount_diff;       //Differential value between Tx_pclk counter and theoritical value
+
+//Heartbeat counter and heartbeat signal running on pclk
+reg  [2:0]  phb_cnt;
+reg         phb;
+
+//CPRI dynamic mode releated signals
+reg  [2:0]  pcpri_mode;
+reg         pcpri_mod_ch;
+
+//Assignment scheme changed mainly for simulation purpose
+wire [15:0] LRCLK_TC_w;
+assign LRCLK_TC_w = LRCLK_TC;
+
+reg         unlock;
+reg         lock;
+
+//Heartbeat synchronization
+sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (phb),
+  .data_out(rhb_sync)
+  );
+  
+  
+//Terminal count pulse synchronization
+sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( 
+  .clk     (sli_pclk),
+  .rst     (sli_rst),
+  .data_in (rtc_pul),
+  .data_out(ppul_sync)
+  );
+
+//Differential value logic update synchronization
+sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (ppul_sync),
+  .data_out(pdiff_sync)
+  );
+
+//Gear mode synchronization
+sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_gear_mode),
+  .data_out(rgear)
+  );
+  
+//Div2 synchronization
+sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_div2_rate),
+  .data_out(rdiv2)
+  );
+  
+//Div11 synchronization
+sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_div11_rate),
+  .data_out(rdiv11)
+  );
+  
+//CPRI mode change synchronization
+sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (pcpri_mod_ch),
+  .data_out(rcpri_mod_ch_sync)
+  );
+  
+//PCIe mode change synchronization
+sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_pcie_mode),
+  .data_out(rpcie_mode)
+  );  
+
+// =============================================================================
+// Synchronized Lock/Unlock signals
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    unlock        <= 1'b0;
+    lock          <= 1'b0;
+    pdiff_sync_p1 <= 1'b0;
+  end
+  else begin
+    pdiff_sync_p1 <= pdiff_sync;
+    if (unlock) begin
+      unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock;
+    end
+    else begin
+      unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0;
+    end
+    if (lock) begin
+      lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock;
+    end
+    else begin
+      lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0;
+    end
+  end
+end
+
+// =============================================================================
+// Refclk Counter, pulse generation logic and Heartbeat monitor logic
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount     <= 16'd0;
+    rtc_pul    <= 1'b0;
+    rtc_ctrl   <= 1'b0;
+    rtc_pul_p1 <= 1'b0;
+  end
+  else begin
+    //Counter logic
+    if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
+      if (rtc_ctrl == 1'b1) begin
+        rcount <= LRCLK_TC_PUL_WIDTH;
+      end  
+    end
+    else begin
+      if (rcount != LRCLK_TC_w) begin
+        rcount <= rcount + 1;
+      end
+      else begin
+        rcount <= 16'd0;   
+      end
+    end
+    
+    //Pulse control logic
+    if (rcount == LRCLK_TC_w - 1) begin
+      rtc_ctrl <= 1'b1;
+    end
+    
+    //Pulse Generation logic
+    if (rtc_ctrl == 1'b1) begin
+      if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin
+        rtc_pul <= 1'b1;
+    end  
+      else begin
+        rtc_pul <= 1'b0;  
+      end
+    end
+    
+    rtc_pul_p1 <= rtc_pul;  
+  end  
+end
+
+
+// =============================================================================
+// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic 
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rhb_sync_p1     <= 1'b0;
+    rhb_sync_p2     <= 1'b0;
+    rhb_wait_cnt    <= 8'd0;
+    rstat_pclk      <= 1'b0;
+    rgear_p1        <= 1'b0;
+    rdiv2_p1        <= 1'b0;
+    rdiv11_p1       <= 1'b0;
+    rcpri_mod_ch_p1 <= 1'b0;
+    rcpri_mod_ch_p2 <= 1'b0;
+    rcpri_mod_ch_st <= 1'b0;
+    rpcie_mode_p1   <= 1'b0;
+    
+  end
+  else begin
+    //Pipeline stages for the Heartbeat
+    rhb_sync_p1 <= rhb_sync;
+    rhb_sync_p2 <= rhb_sync_p1;
+    
+    //Pipeline stages of the Dynamic rate control signals
+    rgear_p1  <= rgear;
+    rdiv2_p1  <= rdiv2;
+    rdiv11_p1 <= rdiv11;
+    
+    //Pipeline stage for PCIe mode
+    rpcie_mode_p1 <= rpcie_mode;
+    
+    //Pipeline stage for CPRI mode change
+    rcpri_mod_ch_p1 <= rcpri_mod_ch_sync;
+    rcpri_mod_ch_p2 <= rcpri_mod_ch_p1;
+    
+    //CPRI mode change status logic
+    if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin
+      rcpri_mod_ch_st <= 1'b1;
+    end 
+    
+    //Heartbeat wait counter and monitor logic
+    if (rtc_ctrl == 1'b1) begin
+      if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin
+        rhb_wait_cnt <= 8'd0;
+        rstat_pclk   <= 1'b1;
+      end
+      else if (rhb_wait_cnt == LHB_WAIT_CNT) begin
+        rhb_wait_cnt <= 8'd0;
+        rstat_pclk   <= 1'b0;
+      end
+      else begin
+        rhb_wait_cnt <= rhb_wait_cnt + 1;
+      end
+    end
+  end  
+end
+
+
+// =============================================================================
+// Pipleline registers for the TC pulse and CPRI mode change logic
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    ppul_sync_p1 <= 1'b0;
+    ppul_sync_p2 <= 1'b0;
+    ppul_sync_p3 <= 1'b0;
+    pcpri_mode   <= 3'b0;
+    pcpri_mod_ch <= 1'b0;
+  end
+  else begin
+    ppul_sync_p1 <= ppul_sync;
+    ppul_sync_p2 <= ppul_sync_p1;
+    ppul_sync_p3 <= ppul_sync_p2;
+    
+    //CPRI mode change logic
+    pcpri_mode <= sli_cpri_mode;
+    
+    if (pcpri_mode != sli_cpri_mode) begin
+      pcpri_mod_ch <= ~pcpri_mod_ch;
+    end 
+  end  
+end
+   
+
+// =============================================================================
+// Terminal count logic
+// =============================================================================
+
+//For SDI protocol with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    //Div by 11 is enabled
+    if (rdiv11 == 1'b1) begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= PPCLK_DIV11_TC;
+        rdiff_comp_lock   <= PDIFF_DIV11_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK;
+      end
+      else begin
+        rcount_tc         <= {PPCLK_DIV11_TC[20:0], 1'b0};
+        rdiff_comp_lock   <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0};
+        rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0};
+      end
+    end
+    //Div by 2 is enabled
+    else if (rdiv2 == 1'b1) begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+        rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+        rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+      end
+      else begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+    end
+    //Both div by 11 and div by 2 are disabled
+    else begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+      else begin
+        rcount_tc         <= {PPCLK_TC[20:0],1'b0};
+        rdiff_comp_lock   <= {PDIFF_VAL_LOCK[14:0],1'b0};
+        rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0};
+      end
+    end
+  end  
+end
+end
+endgenerate
+
+//For G8B10B protocol with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    //Div by 2 is enabled
+    if (rdiv2 == 1'b1) begin
+      rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+      rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+      rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+    end
+    else begin
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end
+  end  
+end
+end
+endgenerate
+
+
+//For CPRI protocol with Dynamic rate control is disabled
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic for CPRI protocol
+    //Only if there is a change in the rate mode from the default
+    if (rcpri_mod_ch_st == 1'b1) begin
+      if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin
+        case(sli_cpri_mode)
+          3'd0 : begin //For 0.6Gbps
+            rcount_tc         <= LPCLK_TC_0;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_00;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_01;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_01;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_02;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_02;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_03;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_03;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_00;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+              end
+            endcase
+          end
+          
+          3'd1 : begin //For 1.2Gbps
+            rcount_tc         <= LPCLK_TC_1;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_10;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_11;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_11;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_12;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_12;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_13;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_13;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_10;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
+              end
+            endcase
+          end
+          
+          3'd2 : begin //For 2.4Gbps
+            rcount_tc         <= LPCLK_TC_2;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_20;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_21;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_21;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_22;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_22;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_23;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_23;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_20;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
+              end
+            endcase
+          end
+          
+          3'd3 : begin //For 3.07Gbps
+            rcount_tc         <= LPCLK_TC_3;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_30;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_30;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_31;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_31;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_32;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_32;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_33;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_33;
+              end
+            endcase
+          end    
+              
+          3'd4 : begin //For 4.9125bps
+            rcount_tc         <= LPCLK_TC_4;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_40;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_41;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_41;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_42;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_42;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_43;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_43;
+              end  
+            
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_40;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
+              end
+            endcase
+          end
+        
+          default : begin
+            rcount_tc         <= LPCLK_TC_0;
+            rdiff_comp_lock   <= LPDIFF_LOCK_00;
+            rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+          end
+        endcase
+      end
+    end
+    else begin
+      //If there is no change in the CPRI rate mode from default
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end  
+  end  
+end
+end
+endgenerate
+
+//For PCIe protocol with Dynamic rate control disabled
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    if (PPCIE_MAX_RATE == "2.5") begin
+      //2.5G mode is enabled
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end
+    else begin
+      //5G mode is enabled
+      if (rpcie_mode == 1'b1) begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+      else begin
+        //2.5G mode is enabled
+        rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+        rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+        rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+      end 
+    end 	  
+  end  
+end
+end
+endgenerate
+
+//For all protocols other than CPRI & PCIe
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic for all protocols other than CPRI & PCIe
+    rcount_tc         <= PPCLK_TC;
+    rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+    rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+  end  
+end
+end
+endgenerate
+
+
+// =============================================================================
+// Tx_pclk counter, Heartbeat and Differential value logic
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    pcount      <= 22'd0;
+    pcount_diff <= 22'd65535;
+    phb_cnt     <= 3'd0;
+    phb         <= 1'b0;
+  end
+  else begin
+    //Counter logic
+    if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+      pcount <= 22'd0;
+    end
+    else begin
+      pcount <= pcount + 1;
+    end
+    
+    //Heartbeat logic
+    phb_cnt <= phb_cnt + 1;
+    
+    if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin
+      phb <= 1'b1;
+    end  
+    else begin
+      phb <= 1'b0;  
+    end 
+    
+    //Differential value logic
+    if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+      pcount_diff <= rcount_tc + ~(pcount) + 1;
+    end  
+    else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin
+      if (pcount_diff[21] == 1'b1) begin
+        pcount_diff <= ~(pcount_diff) + 1;
+      end
+    end
+  end  
+end
+
+
+// =============================================================================
+// State transition logic for SLL FSM
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    sll_state <= LPLL_LOSS_ST; 
+  end
+  else begin
+    //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI
+    if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || 
+    (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
+      sll_state <= LPLL_LOSS_ST;
+    end
+    else begin  
+      case(sll_state)
+        LPLL_LOSS_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (unlock) begin
+              sll_state <= LPLL_LOSS_ST;
+            end
+            else if (lock) begin
+              if (PLOL_SETTING == 2'd0) begin
+                sll_state <= LPLL_PRELOCK_ST;
+              end
+              else begin
+                sll_state <= LPLL_LOCK_ST;
+              end
+            end
+          end
+        end
+        
+        LPLL_LOCK_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+            else begin
+              if (PLOL_SETTING == 2'd0) begin
+                sll_state <= LPLL_LOSS_ST;
+              end
+              else begin
+                sll_state <= LPLL_PRELOSS_ST;
+              end
+            end
+          end
+        end
+        
+        LPLL_PRELOCK_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+            else begin
+              sll_state <= LPLL_PRELOSS_ST;
+            end
+          end
+        end
+        
+        LPLL_PRELOSS_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (unlock) begin
+              sll_state <= LPLL_PRELOSS_ST;
+            end
+            else if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+          end
+        end
+        
+        default: begin
+          sll_state <= LPLL_LOSS_ST;
+        end
+      endcase
+    end  
+  end  
+end
+
+
+// =============================================================================
+// Logic for Tx PLL Lock
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    pll_lock <= 1'b0; 
+  end
+  else begin
+    case(sll_state)
+      LPLL_LOSS_ST : begin
+        pll_lock <= 1'b0;
+      end
+      
+      LPLL_LOCK_ST : begin
+        pll_lock <= 1'b1;
+      end
+      
+      LPLL_PRELOSS_ST : begin
+        pll_lock <= 1'b0;
+      end
+      
+      default: begin
+        pll_lock <= 1'b0;
+      end
+    endcase
+  end  
+end
+
+assign slo_plol = ~(pll_lock);
+
+endmodule  
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2015 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED 
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement. 
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02 
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS
+// Project               : Synchronizer Logic
+// File                  : sync.v
+// Title                 : Synchronizer module
+// Description           : 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : AV
+// Mod. Date             : July 7, 2015
+// Changes Made          : Initial Creation
+// -----------------------------------------------------------------------------
+// Version               : 1.1
+// Author(s)             : EB
+// Mod. Date             : March 21, 2017
+// Changes Made          : 
+// =============================================================================
+
+`ifndef PCS_SYNC_MODULE
+`define PCS_SYNC_MODULE
+module sync ( 
+  clk,
+  rst,
+  data_in,
+  data_out
+  );
+  
+input  clk;                  //Clock in which the async data needs to be synchronized to
+input  rst;                  //Active high reset
+input  data_in;              //Asynchronous data
+output data_out;             //Synchronized data
+
+parameter PDATA_RST_VAL = 0; //Reset value for the registers
+
+reg data_p1;
+reg data_p2;
+
+// =============================================================================
+// Synchronization logic
+// =============================================================================
+always @(posedge clk or posedge rst) begin
+  if (rst == 1'b1) begin
+    data_p1 <= PDATA_RST_VAL;
+    data_p2 <= PDATA_RST_VAL; 
+  end
+  else begin
+    data_p1 <= data_in;
+    data_p2 <= data_p1;
+  end  
+end
+
+assign data_out = data_p2; 
+
+endmodule    
+`endif
+
diff --git a/gbe_trb_ecp5/media/ecp5-5g/sgmii_gbe.lpc b/gbe_trb_ecp5/media/ecp5-5g/sgmii_gbe.lpc
new file mode 100644
index 0000000..d37f4c5
--- /dev/null
+++ b/gbe_trb_ecp5/media/ecp5-5g/sgmii_gbe.lpc
@@ -0,0 +1,37 @@
+[Device]
+Family=sa5p00g
+OperatingCondition=COM
+Package=CABGA381
+PartName=LFE5UM5G-85F-8BG381C
+PartType=LFE5UM5G-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=SGMII/Gb Ethernet PCS
+CoreRevision=4.2
+CoreStatus=Demo
+CoreType=IPCFG
+Date=06/27/2022
+ModuleName=sgmii_gbe
+ParameterFileVersion=1.0
+SourceFormat=vhdl
+Time=13:46:42
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+CH_MODE=Rx and Tx
+CORE_SYNP=1
+Channel=CH0
+DCUA=DCU0
+EasyConnect=1
+MAX_RATE=1.250
+NUM_CHS=1
+PROTOCOL=SGMII
+REFCLK_RATE=125.0000
+RX_CTC=2
+RX_CTC_HIGH=32
+RX_CTC_LOW=16
+SBP=1
+SOFTLOL=Enabled
+TX_MAX_RATE=2.5
+[SYSTEMPNR]
+LN0=DCU0_CH0
diff --git a/gbe_trb_ecp5/media/ecp5-5g/sgmii_gbe_core.ngo b/gbe_trb_ecp5/media/ecp5-5g/sgmii_gbe_core.ngo
new file mode 100644
index 0000000..7ad45c6
Binary files /dev/null and b/gbe_trb_ecp5/media/ecp5-5g/sgmii_gbe_core.ngo differ
diff --git a/gbe_trb_ecp5/media/ecp5-5g/tsmac_gbe.lpc b/gbe_trb_ecp5/media/ecp5-5g/tsmac_gbe.lpc
new file mode 100644
index 0000000..43794b8
--- /dev/null
+++ b/gbe_trb_ecp5/media/ecp5-5g/tsmac_gbe.lpc
@@ -0,0 +1,37 @@
+[Device]
+Family=sa5p00g
+PartType=LFE5UM5G-85F
+PartName=LFE5UM5G-85F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=IPCFG
+CoreStatus=Demo
+CoreName=Tri-Speed Ethernet MAC
+CoreRevision=4.1
+ModuleName=tsmac_gbe
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=06/27/2022
+Time=13:47:01
+
+[Parameters]
+MIIM=No
+MODE=Gbit MAC
+MODS_TOOL=0
+ALDC_TOOL=0
+MULT_WB=NO
+LOOPBACK=NO
+STAT_REGS=NO
+CORE_SYNP=1
+
+[Files]
+Synthesis=
+Simulation=
+Logical=
+Physical=
+Misc=
diff --git a/gbe_trb_ecp5/media/ecp5-5g/tsmac_gbe.ngo b/gbe_trb_ecp5/media/ecp5-5g/tsmac_gbe.ngo
new file mode 100644
index 0000000..33bffa8
Binary files /dev/null and b/gbe_trb_ecp5/media/ecp5-5g/tsmac_gbe.ngo differ