From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Fri, 8 Apr 2022 07:59:33 +0000 (+0200)
Subject: fixed typos
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5353bb47db9639602f6e263fa967fe52b558a193;p=trb3sc.git

fixed typos
---

diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd
index 9f8b39d..617dc29 100644
--- a/code/clock_reset_handler.vhd
+++ b/code/clock_reset_handler.vhd
@@ -233,5 +233,7 @@ BUS_TX.data    <= (others => '0');
 BUS_TX.unknown <= '1';
 BUS_TX.ack     <= '0';
 BUS_TX.nack    <= '0';
+BUS_TX.rack    <= '0';
+BUS_TX.wack    <= '0';
 
 end architecture;
diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd
index d946f74..f215111 100644
--- a/tdctemplate/trb3sc_tdctemplate.vhd
+++ b/tdctemplate/trb3sc_tdctemplate.vhd
@@ -107,7 +107,7 @@ architecture trb3sc_arch of trb3sc_tdctemplate is
   --Media Interface
   signal med2int           : med2int_array_t(0 to 0);
   signal int2med           : int2med_array_t(0 to 0);
-  signal med_stat_debug    : std_logic_vector (1*64-1 downto 0);
+--  signal med_stat_debug    : std_logic_vector (1*64-1 downto 0);
 
   --READOUT
   signal readout_rx        : READOUT_RX;
@@ -235,7 +235,7 @@ end generate;
       MEDIA_INT2MED(0 to 2)           => open,
       MEDIA_INT2MED(3)                => int2med(0),
       -- Sync operation
-      RX_DLM_OUT(2 downto 2)          => open,
+      RX_DLM_OUT(2 downto 0)          => open,
       RX_DLM_OUT(3)                   => rx_dlm_i,
       RX_DLM_WORD_OUT(23 downto 0)    => open,
       RX_DLM_WORD_OUT(31 downto 24)   => send_dlm_word_i,
@@ -349,7 +349,7 @@ end generate;
   THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
     generic map(
       PORT_NUMBER      => 5,
-      PORT_ADDRESSES   => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", 4 => x"b000", others => x"0000"),
+      PORT_ADDRESSES   => (0 => x"d000", 1 => x"b200", 2 => x"d300", 3 => x"c000", 4 => x"e000", others => x"0000"),
       PORT_ADDR_MASK   => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, others => 0),
       PORT_MASK_ENABLE => 1
       )