From: hadeshyp Date: Wed, 18 Feb 2009 14:50:43 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~483 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=537fb3012781c9f637322e33b3ea4544089c0b06;p=trbnet.git *** empty log message *** --- diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index be1d811..ecfa645 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -14,8 +14,8 @@ entity trb_net16_api_base is FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - SECURE_MODE_TO_APL: integer range 0 to 1 := c_NO; - SECURE_MODE_TO_INT: integer range 0 to 1 := c_NO; + SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; + SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF" ); @@ -815,7 +815,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; when RUNNING => fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and not master_counter(2); next_INT_MASTER_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or (master_counter(2) and not fifo_to_int_empty)); - if APL_SEND_IN = '0' then --and fifo_was_not_empty = '1' then -- terminate the transfer + if APL_SEND_IN = '0' and fifo_was_not_empty = '1' then -- terminate the transfer update_registered_trailer <= '1'; if fifo_to_int_empty = '1' and master_counter = c_F3 and sbuf_free = '1' then next_state_to_int <= SEND_TRAILER; -- immediate stop diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index bc8e47e..5b10554 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -91,6 +91,7 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is signal current_demux_READ : STD_LOGIC_VECTOR ((2**c_MUX_WIDTH-1)-1 downto 0); signal next_demux_dr, next_demux_dr_tmp, demux_dr_tmp: STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + signal buf_INT_DATAREADY_OUT : STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); signal current_MED_READ_OUT, next_MED_READ_OUT: STD_LOGIC; signal final_INT_READ_OUT: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); --signal tmp_tmp_INT_READ_OUT: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); @@ -98,7 +99,7 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is signal current_mux_buffer: STD_LOGIC_VECTOR (c_DATA_WIDTH+c_NUM_WIDTH-1 downto 0); signal endpoint_locked, next_endpoint_locked: std_logic; signal current_INT_READ_OUT : STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); - signal current_mux_packet_number : std_logic_vector (c_NUM_WIDTH-1 downto 0); + signal current_mux_packet_number : std_logic_vector (c_NUM_WIDTH-1 downto 0) := c_H0; signal last_mux_enable : std_logic; signal arbiter_CLK_EN : std_logic; signal buf_INT_DATA_OUT: STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); @@ -128,15 +129,16 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is begin if rising_edge(CLK) then if RESET = '1' then - INT_DATAREADY_OUT(i) <= '0'; + buf_INT_DATAREADY_OUT(i) <= '0'; else - INT_DATAREADY_OUT(i) <= next_demux_dr(i) and MED_DATAREADY_IN; + buf_INT_DATAREADY_OUT(i) <= next_demux_dr(i) and MED_DATAREADY_IN; end if; end if; end process; end generate; INT_DATA_OUT <= buf_INT_DATA_OUT; + INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT; --current_demux_READ <= INT_READ_IN; @@ -267,10 +269,15 @@ ARBITER: trb_net_priority_arbiter -- current_INT_READ_OUT <= tmp_INT_READ_OUT when endpoint_locked = '0' -- else final_INT_READ_OUT; - STAT(0) <= sbuf_status; - STAT(15 downto 1) <= (others => '0'); - STAT(18 downto 16) <= current_mux_buffer(c_DATA_WIDTH+c_NUM_WIDTH-1 downto c_DATA_WIDTH) xor current_mux_packet_number; - STAT(31 downto 19) <= (others => '0'); + STAT(7 downto 0) <= INT_DATAREADY_IN(7 downto 0); + STAT(15 downto 8) <= current_INT_READ_OUT(7 downto 0); + STAT(19 downto 16) <= buf_INT_DATAREADY_OUT(3 downto 0); + STAT(20) <= next_endpoint_locked; + STAT(21) <= arbiter_CLK_EN; + STAT(24 downto 22) <= current_mux_packet_number; + STAT(25) <= mux_read; + + STAT(31 downto 26) <= (others => '0'); process(CLK) @@ -338,15 +345,18 @@ ARBITER: trb_net_priority_arbiter k := 0; var_mux_buffer := (others => '0'); for i in 0 to 2**c_MUX_WIDTH-1 loop - for j in 0 to c_DATA_WIDTH-1 loop - var_mux_buffer(j) := var_mux_buffer(j) or (INT_DATA_IN(c_DATA_WIDTH*i+j) and current_INT_READ_OUT(i)); - end loop; - for j in c_DATA_WIDTH to c_DATA_WIDTH + c_NUM_WIDTH-1 loop - var_mux_buffer(j) := var_mux_buffer(j) or (INT_PACKET_NUM_IN(c_NUM_WIDTH*i+j-c_DATA_WIDTH) and current_INT_READ_OUT(i)); + for j in 0 to c_DATA_WIDTH+c_NUM_WIDTH-1 loop + if j < c_DATA_WIDTH then + var_mux_buffer(j) := var_mux_buffer(j) or (INT_DATA_IN(c_DATA_WIDTH*i+j) and current_INT_READ_OUT(i)); + else + var_mux_buffer(j) := var_mux_buffer(j) or (INT_PACKET_NUM_IN(c_NUM_WIDTH*i+j-c_DATA_WIDTH) and current_INT_READ_OUT(i)); + end if; + if current_INT_READ_OUT(i) = '1' and INT_PACKET_NUM_IN(c_NUM_WIDTH*(i+1)-1 downto c_NUM_WIDTH*i) = "100" then + k := i; + else + k := k; + end if; end loop; - if current_INT_READ_OUT(i) = '1' and INT_PACKET_NUM_IN(c_NUM_WIDTH*(i+1)-1 downto c_NUM_WIDTH*i) = "100" then - k := i; - end if; end loop; var_mux_buffer(3+c_MUX_WIDTH-1 downto 3) := var_mux_buffer(3+c_MUX_WIDTH-1 downto 3) or conv_std_logic_vector(k, c_MUX_WIDTH); current_mux_buffer <= var_mux_buffer;