From: Manuel Penschuck Date: Tue, 27 Aug 2013 13:38:09 +0000 (+0200) Subject: CBMNet Work in progress: linking seems to work (not quite stable yet) X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=54186d279337b3eac07f219872abc9db770b5f14;p=trb3.git CBMNet Work in progress: linking seems to work (not quite stable yet) --- diff --git a/cbmnet/code/cbmnet_phy_ecp3.vhd b/cbmnet/code/cbmnet_phy_ecp3.vhd index 1131698..7eaf524 100644 --- a/cbmnet/code/cbmnet_phy_ecp3.vhd +++ b/cbmnet/code/cbmnet_phy_ecp3.vhd @@ -58,7 +58,8 @@ entity cbmnet_phy_ecp3 is STAT_OP : out std_logic_vector (15 downto 0); CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') + CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0'); + DEBUG_OUT : out std_logic_vector (127 downto 0) := (others => '0') ); end entity; @@ -74,27 +75,37 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal clk_125_internal : std_logic; signal clk_rx_full : std_logic; signal clk_rx_half : std_logic; - signal clk_tx_full : std_logic; - signal clk_tx_half : std_logic; signal tx_data_i : std_logic_vector(17 downto 0); + signal tx_data_buf_i : std_logic_vector(17 downto 0); signal rx_data_i : std_logic_vector(17 downto 0); signal rx_error : std_logic_vector(1 downto 0); signal rst_n : std_logic; signal rst : std_logic; - signal rx_serdes_rst : std_logic; signal tx_serdes_rst : std_logic; signal tx_pcs_rst : std_logic; - signal rx_pcs_rst : std_logic; signal rst_qd : std_logic; signal serdes_rst_qd : std_logic; signal sd_los_i : std_logic; + signal rx_pcs_rst : std_logic; + signal rx_fsm_pcs_rst : std_logic:= '0'; + signal rx_init_pcs_rst : std_logic:= '0'; + + signal rx_serdes_rst : std_logic; + signal rx_fsm_serdes_rst : std_logic := '0'; + signal rx_init_serdes_rst : std_logic := '0'; + + + + signal rx_los_low : std_logic; signal rx_cdr_lol : std_logic; signal tx_pll_lol : std_logic; + + signal serdes_ready_i : std_logic; signal sci_ch_i : std_logic_vector(3 downto 0); signal sci_qd_i : std_logic; @@ -109,6 +120,9 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF"; + + signal wa_position_buf : std_logic_vector(3 downto 0); + signal request_retr_i : std_logic; signal start_retr_i : std_logic; signal request_retr_position_i : std_logic_vector(7 downto 0); @@ -133,6 +147,8 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal led_tx, last_led_tx : std_logic; signal led_rx, last_led_rx : std_logic; signal timer : unsigned(20 downto 0); + + signal lsm_status_i : std_logic; -- RX READY MODULE @@ -143,6 +159,8 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal rx_saw_ready1_i : std_logic; signal rx_valid_char_i : std_logic; signal link_init_rx_reset_i : std_logic; + + signal rx_rm_rst_n :std_logic; -- TX READY MODULE @@ -155,12 +173,12 @@ begin SD_TXDIS_OUT <= '0'; - rst_n <= not (CLEAR or sd_los_i); - rst <= (CLEAR or sd_los_i); + rst_n <= not (CLEAR or sd_los_i or CTRL_OP(0)); + rst <= (CLEAR or sd_los_i or CTRL_OP(0)); gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate - clk_125_i <= clk_rx_full; + clk_125_i <= clk_rx_half; end generate; gen_master_clock : if IS_SYNC_SLAVE = c_NO generate @@ -181,17 +199,20 @@ begin -- CLOCKS rxiclk_ch0 => clk_125_i, txiclk_ch0 => clk_125_i, + rx_full_clk_ch0 => clk_rx_full, rx_half_clk_ch0 => clk_rx_half, - tx_full_clk_ch0 => clk_tx_full, - tx_half_clk_ch0 => clk_tx_half, + + tx_full_clk_ch0 => open, + tx_half_clk_ch0 => open, + fpga_rxrefclk_ch0 => clk_125_internal, -- RESETS fpga_txrefclk => clk_125_i, rst_qd_c => rst_qd, - serdes_rst_qd_c => serdes_rst_qd, - tx_serdes_rst_c => tx_serdes_rst, + serdes_rst_qd_c => serdes_rst_qd, -- always 0 + tx_serdes_rst_c => tx_serdes_rst, -- always 0 rx_serdes_rst_ch0_c => rx_serdes_rst, tx_pcs_rst_ch0_c => tx_pcs_rst, rx_pcs_rst_ch0_c => rx_pcs_rst, @@ -200,8 +221,8 @@ begin rx_pwrup_ch0_c => '1', -- TX DATA PORT - txdata_ch0 => tx_data_i(15 downto 0), - tx_k_ch0 => tx_data_i(17 downto 16), + txdata_ch0 => tx_data_buf_i(15 downto 0), + tx_k_ch0 => tx_data_buf_i(17 downto 16), tx_force_disp_ch0 => "00", tx_disp_sel_ch0 => "00", @@ -223,6 +244,7 @@ begin tx_pll_lol_qd_s => tx_pll_lol, rx_los_low_ch0_s => rx_los_low, rx_cdr_lol_ch0_s => rx_cdr_lol, + lsm_status_ch0_s => lsm_status_i, SCI_WRDATA => sci_data_in_i, SCI_RDDATA => sci_data_out_i, @@ -232,9 +254,37 @@ begin SCI_RD => sci_read_i, SCI_WRN => sci_write_i ); - + + wa_position_buf <= x"1" when (rx_init_pcs_rst = '1' and CTRL_OP(2) = '0') or (CTRL_OP(4) = '1') else + wa_position_rx(3 downto 0); + + tx_data_buf_i <= + ("01" & x"009c") when CTRL_OP(9 downto 8) = "01" else + ("01" & x"00bc") when CTRL_OP(9 downto 8) = "11" else + tx_data_i; + + rx_pcs_rst <= rx_fsm_pcs_rst; + rx_serdes_rst <= rx_fsm_serdes_rst; + tx_serdes_rst <= '0'; --no function serdes_rst_qd <= '0'; --included in rst_qd + + DEBUG_OUT(17 downto 0) <= tx_data_i; + DEBUG_OUT(22 downto 20) <= tx_pll_lol & rx_los_low & rx_cdr_lol; + + DEBUG_OUT(17+32 downto 32) <= rx_data_i; + + process is + variable cnt, cntr : unsigned(15 downto 0); + begin + wait until rising_edge(clk_125_i); + cnt := cnt + 1; + cntr := cntr + 1; + if rst_n = '0' then + cntr := x"0000"; + end if; + DEBUG_OUT(31 + 64 downto 64) <= std_logic_vector(cnt) & std_logic_vector(cntr); + end process; ------------------------------------------------- -- Reset FSM & Link states @@ -244,11 +294,11 @@ begin RST_N => rst_n, RX_REFCLK => clk_125_i, TX_PLL_LOL_QD_S => tx_pll_lol, - RX_SERDES_RST_CH_C => rx_serdes_rst, + RX_SERDES_RST_CH_C => rx_fsm_serdes_rst, RX_CDR_LOL_CH_S => rx_cdr_lol, RX_LOS_LOW_CH_S => rx_los_low, - RX_PCS_RST_CH_C => rx_pcs_rst, - WA_POSITION => wa_position_rx(3 downto 0), + RX_PCS_RST_CH_C => rx_fsm_pcs_rst, + WA_POSITION => wa_position_buf, STATE_OUT => rx_fsm_state ); @@ -290,15 +340,20 @@ begin end if; end process; + serdes_ready_i <= not (rx_cdr_lol or tx_pll_lol) when + wa_position_rx = x"0000" and + tx_fsm_state = x"5" and + rx_fsm_state = x"6" else '0'; + ------------------------------------------------- -- CBMNet Link Init ------------------------------------------------- THE_RX_READY: gtp_rx_ready_module - generic map (INCL_8B10B_DEC => 0) + generic map (INCL_8B10B_DEC => c_No) port map ( clk => clk_125_i, - res_n => rst_n, - ready_MGT2RM => '1', + res_n => rx_rm_rst_n, + ready_MGT2RM => serdes_ready_i, rxdata_in(17 downto 0) => rx_data_i, rxdata_in(19 downto 18) => "00", @@ -315,20 +370,22 @@ begin saw_ready1 => rx_saw_ready1_i, valid_char => rx_valid_char_i, - reset_rx => link_init_rx_reset_i + reset_rx => rx_init_pcs_rst ); + + rx_rm_rst_n <= not (rst or CTRL_OP(1)); -- or not serdes_ready_i); THE_TX_READY: gtp_tx_ready_module port map ( clk => clk_125_i, -- : in std_logic; - res_n => rst_n, -- : in std_logic; - restart_link => '0', -- : in std_logic; - ready_MGT2RM => '1', -- : in std_logic; + res_n => rx_rm_rst_n, -- : in std_logic; + restart_link => CTRL_OP(14), -- : in std_logic; + ready_MGT2RM => serdes_ready_i, -- : in std_logic; txdata_in => PHY_TXDATA_IN , -- : in std_logic_vector((DATAWIDTH-1) downto 0); txcharisk_in => PHY_TXDATA_K_IN, -- : in std_logic_vector((WORDS-1) downto 0); see_ready0 => rx_see_ready0_i, -- : in std_logic; - saw_ready1 => rx_see_ready0_i, -- : in std_logic; + saw_ready1 => rx_saw_ready1_i, -- : in std_logic; valid_char => rx_valid_char_i, -- : in std_logic; rx_rm_ready => rx_rm_ready_i, -- : in std_logic; @@ -459,6 +516,7 @@ begin ------------------------------------------------- debug_reg(2 downto 0) <= rx_fsm_state(2 downto 0); debug_reg(3) <= rx_serdes_rst; + debug_reg(4) <= CLEAR; debug_reg(5) <= '1'; debug_reg(6) <= rx_los_low; @@ -468,6 +526,7 @@ begin debug_reg(9) <= tx_pll_lol; debug_reg(10) <= '1'; debug_reg(11) <= CTRL_OP(15); + debug_reg(12) <= '0'; debug_reg(13) <= send_link_reset_i; debug_reg(14) <= sd_los_i; @@ -491,12 +550,34 @@ begin sd_los_i <= SD_LOS_IN when rising_edge(CLK); + + -- STAT_OP REGISTER - STAT_OP(0) <= led_ok; - STAT_OP(1) <= led_tx or last_led_tx; - STAT_OP(2) <= led_rx or last_led_rx; - STAT_OP(3) <= send_link_reset_i when rising_edge(CLK); - STAT_OP( 7 downto 4) <= tx_fsm_state; - STAT_OP(11 downto 8) <= rx_fsm_state; - STAT_OP(15 downto 12) <= (others => '0'); + STAT_OP(0) <= led_tx; + STAT_OP(1) <= led_rx; + STAT_OP(2) <= led_ok; + + STAT_OP(3) <= rx_valid_char_i; + STAT_OP(4) <= rx_see_ready0_i; + STAT_OP(5) <= rx_saw_ready1_i; + STAT_OP(6) <= rx_almost_ready_i; + STAT_OP(7) <= rx_ready_i; + STAT_OP(8) <= rx_init_pcs_rst; + STAT_OP(9) <= tx_almost_ready_i; + STAT_OP(10) <= tx_ready_i; + STAT_OP(11) <= rst_n; + STAT_OP(12) <= serdes_ready_i; + STAT_OP(13) <= lsm_status_i; + + + + + -- STAT_OP(11 downto 8) <= rx_fsm_state; + + -- STAT_OP(15 downto 12) <= wa_position_rx( 3 downto 0); + + --STAT_OP(12) <= rx_los_low; + --STAT_OP(13) <= ; + --STAT_OP(14) <= ; + --STAT_OP(15) <= ; end architecture; diff --git a/cbmnet/code/cbmnet_phy_pkg.vhd b/cbmnet/code/cbmnet_phy_pkg.vhd index 180af9f..c8cb47a 100644 --- a/cbmnet/code/cbmnet_phy_pkg.vhd +++ b/cbmnet/code/cbmnet_phy_pkg.vhd @@ -4,113 +4,117 @@ library ieee; use work.trb_net_std.all; package cbmnet_phy_pkg is -component cbmnet_sfp1 is - GENERIC (USER_CONFIG_FILE : String := "cbmnet_sfp1.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (15 downto 0); - tx_k_ch0 : in std_logic_vector (1 downto 0); - tx_force_disp_ch0 : in std_logic_vector (1 downto 0); - tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); - rxdata_ch0 : out std_logic_vector (15 downto 0); - rx_k_ch0 : out std_logic_vector (1 downto 0); - rx_disp_err_ch0 : out std_logic_vector (1 downto 0); - rx_cv_err_ch0 : out std_logic_vector (1 downto 0); - rx_serdes_rst_ch0_c : in std_logic; - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - --word_align_en_ch0_c : in std_logic; - tx_pcs_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pcs_rst_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - sci_int : out std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_qd_c : in std_logic; - refclk2fpga : out std_logic; - serdes_rst_qd_c : in std_logic); + component cbmnet_phy_ecp3 is + generic( + IS_SYNC_SLAVE : integer := c_NO --select slave mode + ); + port( + CLK : in std_logic; -- *internal* 125 MHz reference clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset -end component; + --Internal Connection TX + PHY_TXDATA_IN : in std_logic_vector(15 downto 0); + PHY_TXDATA_K_IN : in std_logic_vector( 1 downto 0); + --Internal Connection RX + PHY_RXDATA_OUT : out std_logic_vector(15 downto 0) := (others => '0'); + PHY_RXDATA_K_OUT : out std_logic_vector( 1 downto 0) := (others => '0'); + CLK_RX_HALF_OUT : out std_logic := '0'; -- recovered 125 MHz + CLK_RX_FULL_OUT : out std_logic := '0'; -- recovered 250 MHz + CLK_RX_RESET_OUT : out std_logic := '1'; -- set to 0, ~1us after link is assumed to be stable - component cbmnet_phy_ecp3 is - generic( - IS_SYNC_SLAVE : integer := c_NO --select slave mode - ); - port( - CLK : in std_logic; -- *internal* 125 MHz reference clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - - --Internal Connection TX - PHY_TXDATA_IN : in std_logic_vector(15 downto 0); - PHY_TXDATA_K_IN : in std_logic_vector( 1 downto 0); - - --Internal Connection RX - PHY_RXDATA_OUT : out std_logic_vector(15 downto 0) := (others => '0'); - PHY_RXDATA_K_OUT : out std_logic_vector( 1 downto 0) := (others => '0'); - - CLK_RX_HALF_OUT : out std_logic := '0'; -- recovered 125 MHz - CLK_RX_FULL_OUT : out std_logic := '0'; -- recovered 250 MHz - CLK_RX_RESET_OUT : out std_logic := '1'; -- set to 0, ~1us after link is assumed to be stable + LINK_ACTIVE_OUT : out std_logic; -- link is active and can send and receive data + SERDES_ready : out std_logic; - LINK_ACTIVE_OUT : out std_logic; -- link is active and can send and receive data - SERDES_ready : out std_logic; - - --SFP Connection - SD_RXD_P_IN : in std_logic := '0'; - SD_RXD_N_IN : in std_logic := '0'; - SD_TXD_P_OUT : out std_logic := '0'; - SD_TXD_N_OUT : out std_logic := '0'; + --SFP Connection + SD_RXD_P_IN : in std_logic := '0'; + SD_RXD_N_IN : in std_logic := '0'; + SD_TXD_P_OUT : out std_logic := '0'; + SD_TXD_N_OUT : out std_logic := '0'; - SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable - --Control Interface - SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); - SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); - SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); - SCI_READ : in std_logic := '0'; - SCI_WRITE : in std_logic := '0'; - SCI_ACK : out std_logic := '0'; - SCI_NACK : out std_logic := '0'; - - -- Status and control port - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') - ); - end component; + --Control Interface + SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); + SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); + SCI_READ : in std_logic := '0'; + SCI_WRITE : in std_logic := '0'; + SCI_ACK : out std_logic := '0'; + SCI_NACK : out std_logic := '0'; + + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0'); + DEBUG_OUT : out std_logic_vector (127 downto 0) := (others => '0') + ); + end component; + +--------------------------------------------------- INTERNAL + component cbmnet_sfp1 is + generic ( + USER_CONFIG_FILE : String := "cbmnet_sfp1.txt" + ); + port ( + ------------------ + -- CH0 -- + hdinp_ch0, hdinn_ch0 : in std_logic; + hdoutp_ch0, hdoutn_ch0 : out std_logic; + sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + fpga_rxrefclk_ch0 : in std_logic; + txdata_ch0 : in std_logic_vector (15 downto 0); + tx_k_ch0 : in std_logic_vector (1 downto 0); + tx_force_disp_ch0 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); + rxdata_ch0 : out std_logic_vector (15 downto 0); + rx_k_ch0 : out std_logic_vector (1 downto 0); + rx_disp_err_ch0 : out std_logic_vector (1 downto 0); + rx_cv_err_ch0 : out std_logic_vector (1 downto 0); + rx_serdes_rst_ch0_c : in std_logic; + sb_felb_ch0_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + --word_align_en_ch0_c : in std_logic; + tx_pcs_rst_ch0_c : in std_logic; + tx_pwrup_ch0_c : in std_logic; + rx_pcs_rst_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + rx_los_low_ch0_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; + tx_div2_mode_ch0_c : in std_logic; + rx_div2_mode_ch0_c : in std_logic; + lsm_status_ch0_s : OUT std_logic; + + -- CH1 -- + -- CH2 -- + -- CH3 -- + ---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + sci_int : out std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + rst_qd_c : in std_logic; + -- refclk2fpga : out std_logic; + serdes_rst_qd_c : in std_logic + ); + end component; end package cbmnet_phy_pkg; package body cbmnet_phy_pkg is diff --git a/cbmnet/code/cbmnet_pkg.vhd b/cbmnet/code/cbmnet_pkg.vhd index 6cbf624..da8f286 100644 --- a/cbmnet/code/cbmnet_pkg.vhd +++ b/cbmnet/code/cbmnet_pkg.vhd @@ -16,7 +16,6 @@ package cbmnet_interface_pkg is constant K297 : std_logic_vector(7 downto 0) := "11111101"; constant K307 : std_logic_vector(7 downto 0) := "11111110"; - component gtp_rx_ready_module is generic ( READY_CHAR0 : std_logic_vector(7 downto 0) := K284; diff --git a/cbmnet/compile_periph_frankfurt.pl b/cbmnet/compile_periph_frankfurt.pl index f9e0a5e..939fd0d 100755 --- a/cbmnet/compile_periph_frankfurt.pl +++ b/cbmnet/compile_periph_frankfurt.pl @@ -4,6 +4,35 @@ use warnings; use strict; +my $build_master = 1; +my $build_slave = 1; + +my $mode = $ARGV[0]; +$mode = 's' unless defined $mode; + +$build_master = 0 if $mode eq 's'; +$build_slave = 0 if $mode eq 'm' or $mode eq 'w'; + +print "Will build:\n"; +print " -> Slave\n" if $build_slave; +print " -> Master\n" if $build_master; + +print "\n\n"; + local $| = 1; +if ($mode eq 'w') { + print "Wait for slave process\n"; + while(-e 'workdir') { + sleep 3; + print ('.'); + } +} + +if ($build_master and $build_slave) { + system "xterm -e './compile_periph_frankfurt.pl s; read' &"; + sleep 5; + system "xterm -e './compile_periph_frankfurt.pl w; read' &"; + exit; +} ################################################################################### @@ -17,8 +46,21 @@ my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; ################################################################################### +my $workdir = "workdir_" . ($build_slave ? 'slave' : 'master'); + symlink($CbmNetPath, 'cbmnet') unless (-e 'cbmnet'); +unless(-e $workdir) { + mkdir $workdir; + chdir $workdir; + system '../../base/linkdesignfiles.sh'; + symlink '../cores/cbmnet_sfp1.txt', 'cbmnet_sfp1.txt'; + chdir '..'; +} + +unlink 'workdir'; +symlink $workdir, 'workdir'; + use FileHandle; $ENV{'SYNPLIFY'}=$synplify_path; @@ -26,17 +68,14 @@ $ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; - - my $FAMILYNAME="LatticeECP3"; my $DEVICENAME="LFE3-150EA"; my $PACKAGE="FPBGA672"; my $SPEEDGRADE="8"; - #create full lpf file -system("cp $BasePath/$TOPNAME.lpf workdir/$TOPNAME.lpf"); -system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); +system("cp $BasePath/$TOPNAME.lpf $workdir/$TOPNAME.lpf"); +system("cat ".$TOPNAME."_constraints.lpf >> $workdir/$TOPNAME.lpf"); #set -e #set -o errexit @@ -57,6 +96,7 @@ use ieee.numeric_std.all; package version is constant VERSION_NUMBER_TIME : integer := $t; + constant CBM_FEE_MODE_C : integer := $build_slave; end package version; EOF @@ -68,8 +108,9 @@ my $r = ""; my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; $r=execute($c, "do_not_exit" ); +system 'rm -f workdir'; -chdir "workdir"; +chdir $workdir; $fh = new FileHandle("<$TOPNAME".".srr"); my @a = <$fh>; $fh -> close; @@ -109,6 +150,7 @@ execute($c); system("rm $TOPNAME.ncd"); $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +#$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.dir" "$TOPNAME.prf"|; execute($c); #Make Bitfile @@ -132,7 +174,6 @@ execute($c); chdir ".."; -exit; sub execute { my ($c, $op) = @_; @@ -143,10 +184,11 @@ sub execute { if($r) { print "$!"; if($op ne "do_not_exit") { - exit; + wait; } } return $r; } + diff --git a/cbmnet/cores/cbmnet_sfp1.ipx b/cbmnet/cores/cbmnet_sfp1.ipx index 832b8ab..86eeab4 100644 --- a/cbmnet/cores/cbmnet_sfp1.ipx +++ b/cbmnet/cores/cbmnet_sfp1.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/cbmnet/cores/cbmnet_sfp1.lpc b/cbmnet/cores/cbmnet_sfp1.lpc index bbde185..de6f74b 100644 --- a/cbmnet/cores/cbmnet_sfp1.lpc +++ b/cbmnet/cores/cbmnet_sfp1.lpc @@ -16,8 +16,8 @@ CoreRevision=8.1 ModuleName=cbmnet_sfp1 SourceFormat=VHDL ParameterFileVersion=1.0 -Date=08/17/2013 -Time=15:49:18 +Date=08/22/2013 +Time=22:50:46 [Parameters] Verilog=0 @@ -170,15 +170,15 @@ _scomma0=User Defined _scomma1=K28P157 _scomma2=K28P157 _scomma3=K28P157 -_comma_a0=1100000101 +_comma_a0=1100001101 _comma_a1=1100000101 _comma_a2=1100000101 _comma_a3=1100000101 -_comma_b0=0011111010 +_comma_b0=0011110010 _comma_b1=0011111010 _comma_b2=0011111010 _comma_b3=0011111010 -_comma_m0=1111111100 +_comma_m0=1111111111 _comma_m1=1111111100 _comma_m2=1111111100 _comma_m3=1111111100 @@ -243,8 +243,8 @@ _rx_los_port1=Internal _rx_los_port2=Internal _rx_los_port3=Internal _sci_ports=ENABLED -_sci_int_port=ENABLED -_refck2core=ENABLED +_sci_int_port=DISABLED +_refck2core=DISABLED Regen=auto PAR1=0 PARTrace1=0 diff --git a/cbmnet/cores/cbmnet_sfp1.pp b/cbmnet/cores/cbmnet_sfp1.pp index a08464d..27dd1ec 100644 --- a/cbmnet/cores/cbmnet_sfp1.pp +++ b/cbmnet/cores/cbmnet_sfp1.pp @@ -28,9 +28,9 @@ #define _ch0_rxwa "ENABLED" #define _ch0_ilsm "ENABLED" #define _ch0_scomma "User Defined" -#define _ch0_comma_a "1100000101" -#define _ch0_comma_b "0011111010" -#define _ch0_comma_m "1111111100" +#define _ch0_comma_a "1100001101" +#define _ch0_comma_b "0011110010" +#define _ch0_comma_m "1111111111" #define _ch0_ctc "DISABLED" #define _ch0_cc_match_mode "1" #define _ch0_byten "0100011100" @@ -182,10 +182,7 @@ #define _cclmark "7" #define _rst_gen "DISABLED" #define _sci_ports "ENABLED" -#define _sci_int_port "ENABLED" -#define _refck2core "ENABLED" +#define _sci_int_port "DISABLED" +#define _refck2core "DISABLED" #define _circuit_name cbmnet_sfp1 -#define _lang vhdl - -#include #include diff --git a/cbmnet/cores/cbmnet_sfp1.txt b/cbmnet/cores/cbmnet_sfp1.txt index d9a6cc2..02541ce 100644 --- a/cbmnet/cores/cbmnet_sfp1.txt +++ b/cbmnet/cores/cbmnet_sfp1.txt @@ -38,9 +38,9 @@ CH0_TX_SB "DISABLED" CH0_RX_SB "DISABLED" CH0_TX_8B10B "ENABLED" CH0_RX_8B10B "ENABLED" -CH0_COMMA_A "1100000101" -CH0_COMMA_B "0011111010" -CH0_COMMA_M "1111111100" +CH0_COMMA_A "1100001101" +CH0_COMMA_B "0011110010" +CH0_COMMA_M "1111111111" CH0_RXWA "ENABLED" CH0_ILSM "ENABLED" CH0_CTC "DISABLED" @@ -52,7 +52,7 @@ CCLMARK "7" CH0_SSLB "DISABLED" CH0_SPLBPORTS "DISABLED" CH0_PCSLBPORTS "DISABLED" -INT_ALL "ENABLED" -QD_REFCK2CORE "ENABLED" +INT_ALL "DISABLED" +QD_REFCK2CORE "DISABLED" diff --git a/cbmnet/cores/cbmnet_sfp1.vhd b/cbmnet/cores/cbmnet_sfp1.vhd index ddad575..dbfeb6a 100644 --- a/cbmnet/cores/cbmnet_sfp1.vhd +++ b/cbmnet/cores/cbmnet_sfp1.vhd @@ -1580,7 +1580,6 @@ entity cbmnet_sfp1 is tx_serdes_rst_c : in std_logic; tx_pll_lol_qd_s : out std_logic; rst_qd_c : in std_logic; - refclk2fpga : out std_logic; serdes_rst_qd_c : in std_logic); end cbmnet_sfp1; @@ -2138,8 +2137,6 @@ end component; attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "125.000"; attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_REFCK2CORE: string; - attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "125.0"; attribute black_box_pad_pin: string; attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; @@ -2170,7 +2167,6 @@ begin vlo_inst : VLO port map(Z => fpsc_vlo); vhi_inst : VHI port map(Z => fpsc_vhi); - refclk2fpga <= refclk2fpga_sig; rx_los_low_ch0_s <= rx_los_low_ch0_sig; rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig; tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; diff --git a/cbmnet/test/flash b/cbmnet/test/flash new file mode 100755 index 0000000..a48b6cc --- /dev/null +++ b/cbmnet/test/flash @@ -0,0 +1,25 @@ +#!/usr/bin/env perl +my $mode = defined $ARGV[0] ? $ARGV[0] : 'ms'; + +my $flash_master = ($mode =~ m/m/); +my $flash_slave = ($mode =~ m/s/); + +if ($flash_master) { + print "Flash MASTER\n"; + system "trbcmd s 0xa6000002e2e2df28 0x00 0x8000"; + system "trbflash -y program 0x8000 workdir_master/trb3_periph_cbmnet.bit"; + system "rebootfpga.sh 0x8000"; +} else { + print "Skip MASTER\n"; +} + +if ($flash_slave) { + print "Flash SLAVE\n"; + system "trbcmd s 0x72000002e2eb4628 0x02 0x8001"; + system "trbflash -y program 0x8001 workdir_slave/trb3_periph_cbmnet.bit"; + system "rebootfpga.sh 0x8001"; +} else { + print "Skip SLAVE\n"; +} + +system "test/start" diff --git a/cbmnet/test/info b/cbmnet/test/info new file mode 100755 index 0000000..536c945 --- /dev/null +++ b/cbmnet/test/info @@ -0,0 +1,7 @@ +#!/usr/bin/env bash + +echo "MASTER" +trbcmd rm 0x8000 0xa008 8 0 + +echo "SLAVE" +trbcmd rm 0x8001 0xa008 8 0 \ No newline at end of file diff --git a/cbmnet/test/reboot b/cbmnet/test/reboot new file mode 100755 index 0000000..1889888 --- /dev/null +++ b/cbmnet/test/reboot @@ -0,0 +1,4 @@ +#!/bin/bash +rebootfpga.sh 0x8000 +rebootfpga.sh 0x8001 +test/start \ No newline at end of file diff --git a/cbmnet/test/start b/cbmnet/test/start new file mode 100755 index 0000000..befd24b --- /dev/null +++ b/cbmnet/test/start @@ -0,0 +1,14 @@ +#!/usr/bin/env perl +print "Reset ... Takes a few seconds\n"; +system "trbcmd reset"; +print "Init\n"; +system "trbcmd s 0xa6000002e2e2df28 0x00 0x8000"; +system "trbcmd s 0x51000002e2e22828 0x01 0x9000"; +system "trbcmd s 0x72000002e2eb4628 0x02 0x8001"; +system "trbcmd s 0xb0000002e311b928 0x03 0x9001"; +system "trbcmd i 0xffff"; + +print "Checks\n"; +my $ver_reg = "0xa006"; +print "\nWRONG VERSION IN MASTER\n" unless(`trbcmd r 0x8000 $ver_reg` =~ m/0x00000000/); +print "\nWRONG VERSION IN SLAVE\n" unless(`trbcmd r 0x8001 $ver_reg` =~ m/0x00000001/); \ No newline at end of file diff --git a/cbmnet/test/toggle b/cbmnet/test/toggle new file mode 100755 index 0000000..a69aa77 --- /dev/null +++ b/cbmnet/test/toggle @@ -0,0 +1,4 @@ +#!/usr/bin/env bash + +trbcmd setbit $1 0xa001 $2 +trbcmd clearbit $1 0xa001 $2 \ No newline at end of file