From: hadeshyp Date: Mon, 2 Feb 2009 15:34:42 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~490 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5507472487676ad128c3475711c29eccb2a0c5dd;p=trbnet.git *** empty log message *** --- diff --git a/special/trb_net_bridge_etrax_apl.vhd b/special/trb_net_bridge_etrax_apl.vhd index 17938bc..3bae89a 100644 --- a/special/trb_net_bridge_etrax_apl.vhd +++ b/special/trb_net_bridge_etrax_apl.vhd @@ -64,14 +64,14 @@ architecture trb_net_bridge_etrax_apl_arch of trb_net_bridge_etrax_apl is signal fifo_net_to_pci_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); signal fifo_net_to_pci_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); signal fifo_net_to_pci_dout : std_logic_vector(32*2**c_MUX_WIDTH-1 downto 0); - signal fifo_net_to_pci_din : std_logic_vector(32*2**c_MUX_WIDTH-1 downto 0); + signal fifo_net_to_pci_din : std_logic_vector(18*2**c_MUX_WIDTH-1 downto 0); signal fifo_net_to_pci_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); signal fifo_net_to_pci_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); signal fifo_net_to_pci_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); signal fifo_pci_to_net_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); signal fifo_pci_to_net_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); signal fifo_pci_to_net_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); - signal fifo_pci_to_net_dout : std_logic_vector(32*2**c_MUX_WIDTH-1 downto 0); + signal fifo_pci_to_net_dout : std_logic_vector(18*2**c_MUX_WIDTH-1 downto 0); signal fifo_pci_to_net_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); signal fifo_pci_to_net_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); signal next_APL_SEND_OUT : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); @@ -84,8 +84,8 @@ architecture trb_net_bridge_etrax_apl_arch of trb_net_bridge_etrax_apl is signal api_status : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); signal channel_address : integer range 0 to 7; - signal comb_channel_address : integer range 0 to 7; - signal last_CPU_ADDRESS : std_logic_vector(15 downto 0); +-- signal comb_channel_address : integer range 0 to 7; +-- signal last_CPU_ADDRESS : std_logic_vector(15 downto 0); signal reg_CPU_ADDRESS : std_logic_vector(15 downto 0); signal reg_CPU_DATA_IN : std_logic_vector(31 downto 0); @@ -139,12 +139,14 @@ begin STAT(20) <= APL_READ_IN(1); STAT(21) <= fifo_pci_to_net_full(1); STAT(22) <= RESET; + STAT(23) <= '0'; + STAT(31 downto 27) <= (others => '0'); -------------------------------- -- r/w registers -------------------------------- channel_address <= conv_integer(reg_CPU_ADDRESS(6 downto 4)); - comb_channel_address <= conv_integer(CPU_ADDRESS(6 downto 4)); +-- comb_channel_address <= conv_integer(CPU_ADDRESS(6 downto 4)); read_regs : process(sender_control, sender_target, sender_error, sender_status, fifo_net_to_pci_data_count, fifo_pci_to_net_data_count, reg_CPU_ADDRESS, reg_CPU_READ, reg_CPU_WRITE, api_status, @@ -162,12 +164,12 @@ begin when x"12" => next_CPU_DATA_OUT <= sender_error(channel_address*32+31 downto channel_address*32); when x"14" => - next_CPU_DATA_OUT <= x"0000" & fifo_pci_to_net_empty(channel_address) & fifo_pci_to_net_full(channel_address) + next_CPU_DATA_OUT <= x"000" & "00" & fifo_pci_to_net_empty(channel_address) & fifo_pci_to_net_full(channel_address) & "000000" & fifo_pci_to_net_data_count(channel_address*10+9 downto channel_address*10); when x"1F" => next_CPU_DATA_OUT <= sender_status(channel_address*32+31 downto channel_address*32); when x"24" => - next_CPU_DATA_OUT <= x"0000" & fifo_net_to_pci_empty(channel_address) & fifo_net_to_pci_full(channel_address) + next_CPU_DATA_OUT <= x"000" & "00" & fifo_net_to_pci_empty(channel_address) & fifo_net_to_pci_full(channel_address) & "000000" & fifo_net_to_pci_data_count(channel_address*10+9 downto channel_address*10); when x"30" => next_CPU_DATA_OUT <= api_status(channel_address*32+31 downto channel_address*32); @@ -245,9 +247,10 @@ begin fifo_net_to_pci_dout(i*32+31 downto i*32+25) <= (others => '0'); fifo_net_to_pci_dout(i*32+23 downto i*32+18) <= (others => '0'); fifo_net_to_pci_dout(i*32+24) <= fifo_net_to_pci_valid_read(i); - fifo_net_to_pci_din(32*i+c_DATA_WIDTH+1 downto 32*i) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2) & APL_PACKET_NUM_IN(c_NUM_WIDTH*i) & APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i); - APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= fifo_pci_to_net_dout(i*32+c_DATA_WIDTH-1 downto i*32); - APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= fifo_pci_to_net_dout(i*32+c_DATA_WIDTH+1 downto i*32+c_DATA_WIDTH); + fifo_net_to_pci_din(18*i+c_DATA_WIDTH+1 downto 18*i) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2) & APL_PACKET_NUM_IN(c_NUM_WIDTH*i) & APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i); +-- fifo_net_to_pci_din(32*i+31 downto 32*i+c_DATA_WIDTH+18) <= (others => '0'); + APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH-1 downto i*18); + APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH+1 downto i*18+c_DATA_WIDTH); APL_PACKET_NUM_OUT(i*3+2) <= '0'; STAT(24) <= fifo_net_to_pci_empty(1); @@ -266,8 +269,8 @@ begin CLK_EN => '1', READ_ENABLE_IN => fifo_net_to_pci_read(i), WRITE_ENABLE_IN => fifo_net_to_pci_write(i), - DATA_IN => fifo_net_to_pci_din(32*i+15 downto 32*i), - PACKET_NUM_IN => fifo_net_to_pci_din(32*i+17 downto 32*i+16), + DATA_IN => fifo_net_to_pci_din(18*i+15 downto 18*i), + PACKET_NUM_IN => fifo_net_to_pci_din(18*i+17 downto 18*i+16), DATA_OUT => fifo_net_to_pci_dout(32*i+15 downto 32*i), PACKET_NUM_OUT => fifo_net_to_pci_dout(32*i+17 downto 32*i+16), DATA_COUNT_OUT => fifo_net_to_pci_data_count(10*i+9 downto 10*i), @@ -289,13 +292,13 @@ begin WRITE_ENABLE_IN => fifo_pci_to_net_write(i), DATA_IN => reg_CPU_DATA_IN(15 downto 0), PACKET_NUM_IN => reg_CPU_DATA_IN(17 downto 16), - DATA_OUT => fifo_pci_to_net_dout(32*i+15 downto 32*i), - PACKET_NUM_OUT => fifo_pci_to_net_dout(32*i+17 downto 32*i+16), + DATA_OUT => fifo_pci_to_net_dout(18*i+15 downto 18*i), + PACKET_NUM_OUT => fifo_pci_to_net_dout(18*i+17 downto 18*i+16), DATA_COUNT_OUT => fifo_pci_to_net_data_count(10*i+9 downto 10*i), full_out => fifo_pci_to_net_full(i), empty_out => fifo_pci_to_net_empty(i) ); - +-- fifo_pci_to_net_dout(32*i+31 downto 32*i+18) <= (others => '0'); end generate; process(CLK) @@ -308,7 +311,7 @@ process(CLK) --write/read flags for fifo - process(reg_CPU_ADDRESS, reg_CPU_READ, reg_CPU_WRITE, comb_channel_address, channel_address) + process(reg_CPU_ADDRESS, reg_CPU_READ, reg_CPU_WRITE, channel_address) begin fifo_net_to_pci_read <= (others => '0'); fifo_pci_to_net_write <= (others => '0'); @@ -335,7 +338,7 @@ process(CLK) process(CPU_ADDRESS, buf_CPU_DATA_OUT, fifo_net_to_pci_dout,reg_CPU_ADDRESS, last_fifo_read, buf_CPU_DATAREADY_OUT) begin - last_CPU_ADDRESS <= CPU_ADDRESS; +-- last_CPU_ADDRESS <= CPU_ADDRESS; if reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0) = x"23" then CPU_DATA_OUT <= fifo_net_to_pci_dout((conv_integer(reg_CPU_ADDRESS(6 downto 4)))*32+31 downto conv_integer(reg_CPU_ADDRESS(6 downto 4))*32); b_CPU_DATAREADY_OUT <= last_fifo_read; diff --git a/special/trb_net_bridge_etrax_endpoint.vhd b/special/trb_net_bridge_etrax_endpoint.vhd index 7116010..1b71918 100644 --- a/special/trb_net_bridge_etrax_endpoint.vhd +++ b/special/trb_net_bridge_etrax_endpoint.vhd @@ -165,8 +165,7 @@ architecture trb_net_bridge_etrax_endpoint_arch of trb_net_bridge_etrax_endpoint -- Status and control port STAT_GEN : out std_logic_vector (31 downto 0); STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); - CTRL_GEN : in std_logic_vector (31 downto 0); - STAT_CTRL_IBUF_BUFFER : in std_logic_vector (31 downto 0) + CTRL_GEN : in std_logic_vector (31 downto 0) ); end component; @@ -270,17 +269,16 @@ architecture trb_net_bridge_etrax_endpoint_arch of trb_net_bridge_etrax_endpoint signal buf_api_stat_fifo_to_int : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0); signal buf_api_stat_fifo_to_apl : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0); - signal buf_DATA_OUT : std_logic_vector(31 downto 0); signal CLK_EN : std_logic; signal m_DATAREADY_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); signal m_DATA_OUT : std_logic_vector (c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto 0); signal m_PACKET_NUM_OUT: std_logic_vector (c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto 0); signal m_READ_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); - signal m_DATAREADY_IN : std_logic_vector (c_MUX_WIDTH-1 downto 0); + signal m_DATAREADY_IN : std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0); signal m_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); signal m_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); - signal m_READ_OUT : std_logic_vector (c_MUX_WIDTH-1 downto 0); + signal m_READ_OUT : std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0); signal MPLEX_CTRL : std_logic_vector (31 downto 0); signal apl_to_buf_INIT_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); @@ -305,13 +303,9 @@ architecture trb_net_bridge_etrax_endpoint_arch of trb_net_bridge_etrax_endpoint signal STAT_GEN : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); - signal STAT_LOCKED : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); signal STAT_INIT_BUFFER : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); - signal STAT_REPLY_BUFFER : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); signal CTRL_GEN : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); signal CTRL_LOCKED : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); - signal STAT_CTRL_INIT_BUFFER : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); - signal STAT_CTRL_REPLY_BUFFER : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); signal RESET_i : std_logic; signal RESET_CNT : std_logic_vector(1 downto 0); signal counter : std_logic_vector(12 downto 0); @@ -366,7 +360,6 @@ begin CTRL => MPLEX_CTRL ); - STAT_CTRL_INIT_BUFFER <= (others => '0'); gen_iobufs : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate IOBUF: trb_net16_iobuf port map ( @@ -408,11 +401,11 @@ begin -- Status and control port STAT_GEN => STAT_GEN((i+1)*32-1 downto i*32), STAT_IBUF_BUFFER => STAT_INIT_BUFFER((i+1)*32-1 downto i*32), - CTRL_GEN => CTRL_GEN((i+1)*32-1 downto i*32), - STAT_CTRL_IBUF_BUFFER => STAT_CTRL_INIT_BUFFER((i+1)*32-1 downto i*32) + CTRL_GEN => CTRL_GEN((i+1)*32-1 downto i*32) ); end generate; + CTRL_GEN <= (others => '0'); gen_pas_apis : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate DAT_PASSIVE_API: trb_net16_api_base diff --git a/trb_net16_addresses.vhd b/trb_net16_addresses.vhd index a673f70..52ca0be 100644 --- a/trb_net16_addresses.vhd +++ b/trb_net16_addresses.vhd @@ -75,7 +75,6 @@ signal last_ram_read_addr2 : std_logic_vector(3 downto 0); signal buf_API_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal buf_API_READ_OUT : std_logic; signal buf_API_SEND_OUT : std_logic; -signal read_UNIQUE_ID : std_logic; signal recv_set_address : std_logic; signal next_state, state : std_logic_vector(c_NUM_WIDTH-1 downto 0); @@ -101,7 +100,6 @@ begin elsif CLK_EN = '1' then buf_API_READ_OUT <= '1'; ADDRESS_REJECTED <= '0'; - read_UNIQUE_ID <= '0'; --recv_set_address <= '0'; --control sending state @@ -115,7 +113,7 @@ begin --read incoming data if API_DATAREADY_IN = '1' and buf_API_READ_OUT = '1' then buf_API_READ_OUT <= '0'; - if API_PACKET_NUM_IN = c_F0 and read_UNIQUE_ID = '0' and recv_set_address = '0' then + if API_PACKET_NUM_IN = c_F0 and recv_set_address = '0' then case API_DATA_IN is when READ_ID => sending_state <= send_uid_1; diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index 4e9a9f0..be1d811 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -170,12 +170,6 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_READ_OUT : out std_logic; - -- "mini" APL, just to see terminations coming in - APL_DTYPE_OUT : out std_logic_vector (3 downto 0); - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - APL_GOT_TRM : out std_logic; - APL_RELEASE_TRM : in std_logic; APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) ); end component; @@ -306,7 +300,6 @@ begin INT_DATA_IN => INT_MASTER_DATA_IN, INT_PACKET_NUM_IN => INT_MASTER_PACKET_NUM_IN, INT_READ_OUT => INT_MASTER_READ_OUT, - APL_RELEASE_TRM => '1', APL_ERROR_PATTERN_IN => (others => '0') ); end generate; @@ -821,7 +814,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; end if; when RUNNING => fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and not master_counter(2); - next_INT_MASTER_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or (master_counter(2) and not fifo_to_int_empty); + next_INT_MASTER_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or (master_counter(2) and not fifo_to_int_empty)); if APL_SEND_IN = '0' then --and fifo_was_not_empty = '1' then -- terminate the transfer update_registered_trailer <= '1'; if fifo_to_int_empty = '1' and master_counter = c_F3 and sbuf_free = '1' then diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index 07a00b6..361779d 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -374,6 +374,9 @@ counter_match <= '1'; INT_REPLY_PACKET_NUM_OUT <= tmp_INT_PACKET_NUM_OUT; INT_REPLY_DATAREADY_OUT <= tmp_INT_REPLY_DATAREADY_OUT; sbuf_REPLY_free <= INT_REPLY_READ_IN; + comb_next_init_read <= '1'; + comb_next_reply_read <= '1'; + stat_sbufs <= (others => '0'); end generate; diff --git a/trb_net16_term.vhd b/trb_net16_term.vhd index 81c1476..73e3b6e 100644 --- a/trb_net16_term.vhd +++ b/trb_net16_term.vhd @@ -36,74 +36,45 @@ entity trb_net16_term is INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_READ_OUT : out std_logic; - - -- "mini" APL, just to see terminations coming in - APL_DTYPE_OUT : out std_logic_vector (3 downto 0); - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - APL_GOT_TRM : out std_logic; - APL_RELEASE_TRM : in std_logic; - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) + APL_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) ); end entity; architecture trb_net16_term_arch of trb_net16_term is - signal next_APL_DTYPE_OUT, reg_APL_DTYPE_OUT: std_logic_vector(3 downto 0); - signal reg_APL_ERROR_PATTERN_OUT: std_logic_vector(31 downto 0); - signal next_APL_SEQNR_OUT, reg_APL_SEQNR_OUT: std_logic_vector(7 downto 0); - signal next_APL_GOT_TRM, reg_APL_GOT_TRM: std_logic; - signal reg_APL_DTYPE_IN : std_logic_vector(3 downto 0); - signal reg_APL_ERROR_PATTERN_IN, buf_APL_ERROR_PATTERN_IN: std_logic_vector(31 downto 0); - - signal saved_packet_type : std_logic_vector(2 downto 0); signal transfer_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal send_trm, next_send_trm : std_logic; signal buf_INT_DATAREADY_OUT, next_INT_DATAREADY_OUT : std_logic; signal buf_INT_DATA_OUT, next_INT_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal reg_APL_GOT_TRM, next_APL_GOT_TRM : std_logic; + signal reg_APL_SEQNR_OUT, next_APL_SEQNR_OUT : std_logic_vector(7 downto 0); begin - g1: if USE_APL_PORT = 1 generate - APL_DTYPE_OUT <= reg_APL_DTYPE_OUT; - APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT; - APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; - APL_GOT_TRM <= reg_APL_GOT_TRM; - INT_READ_OUT <= '1'; --not send_trm and not reg_APL_GOT_TRM; - end generate; - g1n: if USE_APL_PORT = 0 generate - APL_DTYPE_OUT <= (others => '0'); - APL_ERROR_PATTERN_OUT <= (others => '0'); - APL_SEQNR_OUT <= (others => '0'); - APL_GOT_TRM <= '0'; - INT_READ_OUT <= '1'; --not send_trm; - end generate; - - - process(RESET, reg_APL_DTYPE_OUT, reg_APL_SEQNR_OUT, reg_APL_GOT_TRM, - INT_PACKET_NUM_IN, INT_DATA_IN, APL_RELEASE_TRM, send_trm, - transfer_counter, INT_READ_IN, saved_packet_type, buf_APL_ERROR_PATTERN_IN, + INT_READ_OUT <= '1'; --not send_trm; + + + process(RESET, reg_APL_GOT_TRM, reg_APL_SEQNR_OUT, APL_ERROR_PATTERN_IN, + INT_PACKET_NUM_IN, INT_DATA_IN, send_trm, + transfer_counter, INT_READ_IN, saved_packet_type, buf_INT_DATA_OUT, buf_INT_DATAREADY_OUT) begin - next_APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; - if USE_APL_PORT = 1 then - next_APL_DTYPE_OUT <= reg_APL_DTYPE_OUT; - next_APL_GOT_TRM <= reg_APL_GOT_TRM; - if saved_packet_type = TYPE_TRM then - if INT_PACKET_NUM_IN = c_F3 then - next_APL_DTYPE_OUT <= INT_DATA_IN(3 downto 0); - next_APL_SEQNR_OUT <= INT_DATA_IN(11 downto 4); - next_APL_GOT_TRM <= '1'; - end if; - end if; - end if; next_send_trm <= '0'; next_INT_DATAREADY_OUT <= '0'; next_INT_DATA_OUT <= buf_INT_DATA_OUT; + next_APL_GOT_TRM <= '0'; + next_APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; + if saved_packet_type = TYPE_TRM then + if INT_PACKET_NUM_IN = c_F3 then + next_APL_SEQNR_OUT <= INT_DATA_IN(11 downto 4); + next_APL_GOT_TRM <= '1'; + end if; + end if; + - if (reg_APL_GOT_TRM = '1' and (APL_RELEASE_TRM = '1' or USE_APL_PORT = 0)) or send_trm = '1' then + if (reg_APL_GOT_TRM = '1') or send_trm = '1' then -- if (reg_APL_GOT_TRM = '1' and (APL_RELEASE_TRM = '1' )) or send_trm = '1' or 0 = 0 then --next_transfer_counter is used for transmission! if transfer_counter = c_F3_next and INT_READ_IN = '1' then @@ -120,37 +91,16 @@ begin elsif transfer_counter = c_F0_next then next_INT_DATA_OUT <= (others => '0'); elsif transfer_counter = c_F1_next then - next_INT_DATA_OUT <= buf_APL_ERROR_PATTERN_IN(31 downto 16); + next_INT_DATA_OUT <= APL_ERROR_PATTERN_IN(31 downto 16); elsif transfer_counter = c_F2_next then - next_INT_DATA_OUT <= buf_APL_ERROR_PATTERN_IN(15 downto 0); + next_INT_DATA_OUT <= APL_ERROR_PATTERN_IN(15 downto 0); else next_INT_DATA_OUT <= (others => '0'); next_INT_DATA_OUT(11 downto 4) <= reg_APL_SEQNR_OUT; end if; end if; - if (APL_RELEASE_TRM = '1' and reg_APL_GOT_TRM = '1') or USE_APL_PORT = c_NO then - next_APL_GOT_TRM <= '0'; - end if; end process; - --save data from api while sending trailer in secure mode - SECURE_GEN: if SECURE_MODE = 1 generate - CLK_REG2: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - buf_APL_ERROR_PATTERN_IN <= (others => '0'); - elsif APL_RELEASE_TRM = '1' then - buf_APL_ERROR_PATTERN_IN <= APL_ERROR_PATTERN_IN; - end if; - end if; - end process; - end generate; - - SECURE_GEN2: if SECURE_MODE = 0 generate - buf_APL_ERROR_PATTERN_IN <= APL_ERROR_PATTERN_IN; - end generate; - --count packets REG_TRANSFER_COUNTER : process(CLK) @@ -211,38 +161,4 @@ begin end if; end process; - g2: if USE_APL_PORT = 1 generate - CLK_REG: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_APL_DTYPE_OUT <= (others => '0'); - else - reg_APL_DTYPE_OUT <= next_APL_DTYPE_OUT; - end if; - end if; - end process; - - ERROROUT1_REG: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_APL_ERROR_PATTERN_OUT(31 downto 16) <= (others => '0'); - elsif INT_PACKET_NUM_IN = c_F1 then - reg_APL_ERROR_PATTERN_OUT(31 downto 16) <= INT_DATA_IN; - end if; - end if; - end process; - ERROROUT2_REG: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_APL_ERROR_PATTERN_OUT(15 downto 0) <= (others => '0'); - elsif INT_PACKET_NUM_IN = c_F3 then - reg_APL_ERROR_PATTERN_OUT(15 downto 0) <= INT_DATA_IN; - end if; - end if; - end process; - end generate; - end architecture; diff --git a/xilinx/virtex4/trb_net16_fifo_arch.vhd b/xilinx/virtex4/trb_net16_fifo_arch.vhd index 66cc43a..81731f6 100644 --- a/xilinx/virtex4/trb_net16_fifo_arch.vhd +++ b/xilinx/virtex4/trb_net16_fifo_arch.vhd @@ -116,6 +116,7 @@ attribute box_type of xilinx_fifo_18x64 : component is "black_box"; full: OUT std_logic ); end component; +attribute box_type of xilinx_fifo_18x1k_datacount : component is "black_box"; signal din, dout : std_logic_vector(c_DATA_WIDTH + 2-1 downto 0); signal data_counter : std_logic_vector(9 downto 0);