From: Jan Michel <j.michel@gsi.de>
Date: Tue, 26 Apr 2016 14:43:59 +0000 (+0200)
Subject: Fix fifo recognition problem.
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=55e73b2543b2fd0360529438d45d7dd1c607cdb7;p=trb3.git

Fix fifo recognition problem.
---

diff --git a/ADC/source/adc_processor.vhd b/ADC/source/adc_processor.vhd
index 1ecb722..00f1665 100644
--- a/ADC/source/adc_processor.vhd
+++ b/ADC/source/adc_processor.vhd
@@ -68,7 +68,7 @@ signal ram_debug_read    : std_logic_vector(CHANNELS-1 downto 0) := (others => '
 signal ram_clear         : std_logic_vector(CHANNELS-1 downto 0) := (others => '0');
 signal ram_reset         : std_logic := '0';
 signal ram_data_in       : unsigned_array_18(0 to CHANNELS-1) := (others => (others => '0'));
-signal ram_data_out      : unsigned_array_18(0 to CHANNELS-1) := (others => (others => '0'));
+signal ram_data_out      : unsigned_array_18(0 to CHANNELS-1); -- := (others => (others => '0'));
 signal reg_ram_data_out  : unsigned_array_18(0 to CHANNELS-1) := (others => (others => '0'));
 signal reg_buffer_addr   : std_logic_vector(4 downto 0);
 signal reg_buffer_read   : std_logic;