From: Tobias Weber <toweber86@gmail.com>
Date: Fri, 10 Aug 2018 12:45:42 +0000 (+0200)
Subject: Merge with faster Link Simulation. Simulation with 80 MHz results in timing issues.
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=55f63052b94a9afbf841d1ef2a5c62d9141c22f1;p=trb3.git

Merge with faster Link Simulation. Simulation with 80 MHz results in timing issues.
---

55f63052b94a9afbf841d1ef2a5c62d9141c22f1
diff --cc mupix/Mupix8/sources/SlowControl/PixelControl.vhd
index ea92d9a,da3902f..0ac9536
--- a/mupix/Mupix8/sources/SlowControl/PixelControl.vhd
+++ b/mupix/Mupix8/sources/SlowControl/PixelControl.vhd
@@@ -134,9 -134,13 +134,14 @@@ architecture Behavioral of PixelContro
    signal mupix_ctrl_i, mupix_ctrl_ext, mupix_ctrl_sel, mupix_ctrl_reg : MupixSlowControl := c_mupix_slctrl_init;
  
    signal reset_fastcontrol_i             : std_logic                    := '0';
 +  signal start_fastcontrol_i             : std_logic                    := '0';
    signal configure_state, sendbits_state : std_logic_vector(3 downto 0) := (others => '0');
  
+   signal SLV_READ_IN_i  : std_logic;
+   signal SLV_WRITE_IN_i : std_logic;
+   signal SLV_DATA_IN_i  : std_logic_vector(31 downto 0);
+   signal SLV_ADDR_IN_i  : std_logic_vector(15 downto 0);
+ 
  begin  -- Behavioral
  
    fifo_1 : entity work.STD_FIFO
@@@ -417,26 -424,24 +426,26 @@@
        reset_crc_from_mupix_ext <= '0';
        reset_readback_i         <= '0';
        reset_fastcontrol_i      <= '0';
 +      start_fastcontrol_i      <= '0';
        slv_data_out             <= (others => '0');
-       if SLV_WRITE_IN = '1' then
-         case SLV_ADDR_IN is
+       if SLV_WRITE_IN_i = '1' then
+         case SLV_ADDR_IN_i is
            when x"0080" =>
-             DataIn      <= SLV_DATA_IN;
+             DataIn      <= SLV_DATA_IN_i;
              WriteEn     <= '1';
              SLV_ACK_OUT <= '1';
            when x"0083" =>
-             mupix_ctrl_ext.sin       <= SLV_DATA_IN(0);
-             mupix_ctrl_ext.clk1      <= SLV_DATA_IN(1);
-             mupix_ctrl_ext.clk2      <= SLV_DATA_IN(2);
-             mupix_ctrl_ext.load      <= SLV_DATA_IN(3);
-             mupix_ctrcl_select       <= SLV_DATA_IN(4);
-             reset_crc_to_mupix_ext   <= SLV_DATA_IN(5);
-             reset_crc_from_mupix_ext <= SLV_DATA_IN(6);
-             mupix_ctrl_ext.rb        <= SLV_DATA_IN(7);
-             reset_fastcontrol_i      <= SLV_DATA_IN(8);
-             start_fastcontrol_i      <= SLV_DATA_IN(9);
-             bitstosend               <= unsigned(SLV_DATA_IN(31 downto 16));
+             mupix_ctrl_ext.sin       <= SLV_DATA_IN_i(0);
+             mupix_ctrl_ext.clk1      <= SLV_DATA_IN_i(1);
+             mupix_ctrl_ext.clk2      <= SLV_DATA_IN_i(2);
+             mupix_ctrl_ext.load      <= SLV_DATA_IN_i(3);
+             mupix_ctrcl_select       <= SLV_DATA_IN_i(4);
+             reset_crc_to_mupix_ext   <= SLV_DATA_IN_i(5);
+             reset_crc_from_mupix_ext <= SLV_DATA_IN_i(6);
+             mupix_ctrl_ext.rb        <= SLV_DATA_IN_i(7);
+             reset_fastcontrol_i      <= SLV_DATA_IN_i(8);
++            start_fastcontrol_i      <= SLV_DATA_IN_i(9);
+             bitstosend               <= unsigned(SLV_DATA_IN_i(31 downto 16));
              SLV_ACK_OUT              <= '1';
            when x"0084" =>
              slv_ack_out      <= '1';