From: Peter Lemmens Date: Mon, 7 Jul 2014 08:54:09 +0000 (+0200) Subject: implementing tx_full_clk_chx as clock for downstream data. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=564f78c0059ec1a9aa22bcbc9fa548e00758cec0;p=soda.git implementing tx_full_clk_chx as clock for downstream data. --- diff --git a/code/med_ecp3_sfp_4_sync_down.vhd b/code/med_ecp3_sfp_4_sync_down.vhd index d19f4cb..b378b81 100644 --- a/code/med_ecp3_sfp_4_sync_down.vhd +++ b/code/med_ecp3_sfp_4_sync_down.vhd @@ -175,7 +175,10 @@ gen_clocks : for i in 0 to 3 generate rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i)); rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i)); + CLK_RX_HALF_OUT(i) <= clk_rx_half(i); CLK_RX_FULL_OUT(i) <= clk_rx_full(i); + CLK_TX_HALF_OUT(i) <= clk_tx_half(i); + CLK_TX_FULL_OUT(i) <= clk_tx_full(i); -- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate -- NO WAY IN HELL !! this downlink is a master -- clk_200_i(i) <= clk_rx_full(i); diff --git a/code/med_ecp3_sfp_sync_down.vhd b/code/med_ecp3_sfp_sync_down.vhd index 6f17719..6688014 100644 --- a/code/med_ecp3_sfp_sync_down.vhd +++ b/code/med_ecp3_sfp_sync_down.vhd @@ -10,7 +10,6 @@ use work.trb_net_components.all; use work.med_sync_define.all; use work.soda_components.all; - entity med_ecp3_sfp_sync_down is generic( SERDES_NUM : integer range 0 to 3 := 0; IS_SYNC_SLAVE : integer := c_NO); --select slave mode @@ -19,9 +18,6 @@ entity med_ecp3_sfp_sync_down is SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset - -- --- PCSA_REFCLKP : in std_logic; -- external refclock straight into serdes PL! --- PCSA_REFCLKN : in std_logic; -- external refclock straight into serdes PL! --Internal Connection TX MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); @@ -82,7 +78,6 @@ architecture med_ecp3_sfp_sync_down_arch of med_ecp3_sfp_sync_down is attribute syn_sharing of med_ecp3_sfp_sync_down_arch : architecture is "off"; - component DCS -- synthesis translate_off generic @@ -137,6 +132,30 @@ signal sci_write_i : std_logic; signal sci_write_shift_i : std_logic_vector(2 downto 0); signal sci_read_shift_i : std_logic_vector(2 downto 0); +-- fix signal names for constraining +attribute syn_preserve : boolean;-- +attribute syn_keep : boolean;-- +attribute syn_preserve of sci_ch_i : signal is true;-- +attribute syn_keep of sci_ch_i : signal is true;-- +attribute syn_preserve of sci_qd_i : signal is true;-- +attribute syn_keep of sci_qd_i : signal is true;-- +attribute syn_preserve of sci_reg_i : signal is true;-- +attribute syn_keep of sci_reg_i : signal is true;-- +attribute syn_preserve of sci_addr_i : signal is true;-- +attribute syn_keep of sci_addr_i : signal is true;-- +attribute syn_preserve of sci_data_in_i : signal is true;-- +attribute syn_keep of sci_data_in_i : signal is true;-- +attribute syn_preserve of sci_data_out_i : signal is true;-- +attribute syn_keep of sci_data_out_i : signal is true;-- +attribute syn_preserve of sci_read_i : signal is true;-- +attribute syn_keep of sci_read_i : signal is true;-- +attribute syn_preserve of sci_write_i : signal is true;-- +attribute syn_keep of sci_write_i : signal is true;-- +attribute syn_preserve of sci_write_shift_i : signal is true;-- +attribute syn_keep of sci_write_shift_i : signal is true;-- +attribute syn_preserve of sci_read_shift_i : signal is true;-- +attribute syn_keep of sci_read_shift_i : signal is true;-- + signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF"; signal tx_allow : std_logic; @@ -153,6 +172,11 @@ signal make_link_reset_i : std_logic; signal got_link_ready_i : std_logic; signal internal_make_link_reset_out : std_logic; +attribute syn_preserve of wa_position : signal is true;-- +attribute syn_keep of wa_position : signal is true;-- +attribute syn_preserve of wa_position_rx : signal is true;-- +attribute syn_keep of wa_position_rx : signal is true;-- + signal stat_rx_control_i : std_logic_vector(31 downto 0); signal stat_tx_control_i : std_logic_vector(31 downto 0); signal debug_rx_control_i : std_logic_vector(31 downto 0); diff --git a/code/med_ecp3_sfp_sync_up.vhd b/code/med_ecp3_sfp_sync_up.vhd index bced937..7a0bd97 100644 --- a/code/med_ecp3_sfp_sync_up.vhd +++ b/code/med_ecp3_sfp_sync_up.vhd @@ -1,6 +1,5 @@ --Media interface for Lattice ECP3 using PCS at 2GHz - LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.all; @@ -13,7 +12,6 @@ use work.soda_components.all; entity med_ecp3_sfp_sync_up is generic( SERDES_NUM : integer range 0 to 3 := 0; - -- MASTER_CLOCK_SWITCH : integer := c_NO; --just for debugging, should be NO IS_SYNC_SLAVE : integer := c_YES); --select slave mode port( CLK : in std_logic; -- 200 MHz reference clock @@ -32,6 +30,8 @@ entity med_ecp3_sfp_sync_up is MED_READ_IN : in std_logic; CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz + CLK_TX_HALF_OUT : out std_logic := '0'; --received 100 MHz + CLK_TX_FULL_OUT : out std_logic := '0'; --received 200 MHz --Sync operation RX_DLM : out std_logic := '0'; @@ -86,7 +86,6 @@ generic DCSMODE : string :=“POS” ); -- synthesis translate_on - port ( CLK0 :in std_logic ; CLK1 :in std_logic ; @@ -197,13 +196,13 @@ signal watchdog_trigger : std_logic :='0'; begin clk_200_internal <= CLK; + CLK_RX_HALF_OUT <= clk_rx_half; CLK_RX_FULL_OUT <= clk_rx_full; +CLK_TX_HALF_OUT <= clk_tx_half; +CLK_TX_FULL_OUT <= clk_tx_full; - - ---SD_TXDIS_OUT <= not (rx_allow_q or not IS_SYNC_SLAVE); --slave only switches on when RX is ready -SD_TXDIS_OUT <= '0'; --not (rx_allow_q); --slave only switches on when RX is ready +SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready LINK_READY_OUT <= got_link_ready_i; @@ -347,8 +346,6 @@ begin end if; end if; end process; - - ------------------------------------------------- -- TX Data ------------------------------------------------- @@ -386,13 +383,12 @@ THE_TX : soda_tx_control ); LINK_PHASE_OUT <= link_phase_S; --PL! - ------------------------------------------------- -- RX Data ------------------------------------------------- THE_RX_CONTROL : rx_control port map( - CLK_200 => clk_200_i, + CLK_200 => clk_rx_full, --clk_200_i, PL! CLK_100 => SYSCLK, RESET_IN => rst, --CLEAR, PL! @@ -542,7 +538,6 @@ STAT_DEBUG <= debug_reg; internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0'; sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL! - STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK); STAT_OP(14) <= '0'; STAT_OP(13) <= internal_make_link_reset_out when rising_edge(SYSCLK); --make trbnet reset diff --git a/code/soda_calibration_timer.vhd b/code/soda_calibration_timer.vhd index a8820cc..99b215b 100644 --- a/code/soda_calibration_timer.vhd +++ b/code/soda_calibration_timer.vhd @@ -1,63 +1,73 @@ -library ieee; -use ieee.std_logic_1164.all; ---use ieee.numeric_std.all; ---use ieee.std_logic_arith.all; +library ieee; +use ieee.std_logic_1164.all; +--use ieee.numeric_std.all; +use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; - + library work; use work.trb_net_std.all; use work.trb_net_components.all; -use work.trb_net16_hub_func.all; +use work.trb_net16_hub_func.all; use work.soda_components.all; - -entity soda_calibration_timer is - port( - SODACLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; - --Internal Connection - START_CALIBRATION : in std_logic := '0'; - END_CALIBRATION : in std_logic := '0'; - CALIB_VALID_OUT : out std_logic := '0'; -- - CALIB_TIME_OUT : out std_logic_vector(15 downto 0) := (others => '0') - ); -end soda_calibration_timer; - -architecture Behavioral of soda_calibration_timer is - - signal calibration_running_S : std_logic := '0'; - signal calibration_timer_S : std_logic_vector(15 downto 0) := (others => '0'); -- from super-burst-nr-generator - -begin - - packet_fsm_proc : process(SODACLK)--, RESET, packet_state_S, crc_valid_S, START_OF_SUPERBURST, soda_cmd_strobe_S) - begin - if rising_edge(SODACLK) then + +entity soda_calibration_timer is + generic( + cCALIBRATION_TIMEOUT : natural range 1 to 5000 := cSODA_CALIBRATION_TIMEOUT -- clock-period in ns + ); + port( + SODACLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + START_CALIBRATION : in std_logic := '0'; + END_CALIBRATION : in std_logic := '0'; + VALID_OUT : out std_logic := '0'; -- + CALIB_TIME_OUT : out std_logic_vector(15 downto 0) := (others => '0'); + TIMEOUT_ERROR : out std_logic := '0' + ); +end soda_calibration_timer; + +architecture Behavioral of soda_calibration_timer is + + constant cCALIBRATION_LIMIT : std_logic_vector(11 downto 0) := conv_std_logic_vector((cSODA_CALIBRATION_TIMEOUT / cSODA_CLOCK_PERIOD), 12); + + signal calibration_running_S : std_logic := '0'; + signal calibration_timer_S : std_logic_vector(15 downto 0) := (others => '0'); -- from super-burst-nr-generator + +begin + + packet_fsm_proc : process(SODACLK)--, RESET, packet_state_S, crc_valid_S, START_OF_SUPERBURST, soda_cmd_strobe_S) + begin + if rising_edge(SODACLK) then if (RESET='1') then - CALIB_VALID_OUT <= '0'; + VALID_OUT <= '0'; CALIB_TIME_OUT <= (others => '0'); calibration_running_S <= '0'; - calibration_timer_S <= (others => '0'); + calibration_timer_S <= (others => '0'); + TIMEOUT_ERROR <= '0'; else if (START_CALIBRATION='1') then calibration_running_S <= '1'; calibration_timer_S <= (others => '0'); - CALIB_VALID_OUT <= '0'; + VALID_OUT <= '0'; CALIB_TIME_OUT <= (others => '0'); + TIMEOUT_ERROR <= '0'; -- reset timeout error at start of new calibration elsif (END_CALIBRATION='1') then calibration_running_S <= '0'; - CALIB_VALID_OUT <= '1'; + VALID_OUT <= '1'; CALIB_TIME_OUT <= calibration_timer_S; - elsif (calibration_timer_S = x"ffff") then + TIMEOUT_ERROR <= '0'; -- reset timeout error because a correct reply was received + elsif (calibration_timer_S = cCALIBRATION_TIMEOUT) then calibration_running_S <= '0'; - CALIB_VALID_OUT <= '1'; + VALID_OUT <= '1'; CALIB_TIME_OUT <= calibration_timer_S; + TIMEOUT_ERROR <= '1'; -- set timeout error because NO correct reply was received elsif (calibration_running_S='1') then calibration_timer_S <= calibration_timer_S + 1; - end if; - end if; - end if; - end process; - + end if; + end if; + end if; + end process; + end architecture; \ No newline at end of file diff --git a/code/soda_components.vhd b/code/soda_components.vhd index a987eee..74a70fd 100644 --- a/code/soda_components.vhd +++ b/code/soda_components.vhd @@ -21,7 +21,8 @@ package soda_components is constant cSODA_CLOCK_PERIOD : natural range 1 to 20 := 5; -- soda clock-period in ns constant cSYS_CLOCK_PERIOD : natural range 1 to 20 := 10; -- soda clock-period in ns constant cBURST_PERIOD : natural := 2400; -- particle-beam burst-period in ns - constant cSODA_COMMAND_WINDOS_SIZE : natural range 1 to 65535 := 5000; -- size of the window in which soda-cmds are allowed after a superburst-pulse in ns + constant cSODA_COMMAND_WINDOS_SIZE : natural range 1 to 65535 := 5000; -- size of the window in which soda-cmds are allowed after a superburst-pulse in ns + constant cSODA_CALIBRATION_TIMEOUT : natural range 100 to 5000 := 250; -- soda clock-period in ns constant cWINDOW_delay : std_logic_vector(7 downto 0) := conv_std_logic_vector(28, 8); -- in clock-cycles constant cCLOCKS_PER_WINDOW : std_logic_vector(15 downto 0) := conv_std_logic_vector((cSODA_COMMAND_WINDOS_SIZE / cSODA_CLOCK_PERIOD) - 1, 16); -- in clock-cycles @@ -149,6 +150,7 @@ package soda_components is port( SYSCLK : in std_logic; -- fabric clock SODACLK : in std_logic; -- recovered clock + TX_SODACLK : in t_HUB_BIT; -- transmit clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; @@ -249,8 +251,9 @@ package soda_components is --Internal Connection START_CALIBRATION : in std_logic := '0'; END_CALIBRATION : in std_logic := '0'; - CALIB_VALID_OUT : out std_logic := '0'; -- - CALIB_TIME_OUT : out std_logic_vector(15 downto 0) := (others => '0') + VALID_OUT : out std_logic := '0'; -- + CALIB_TIME_OUT : out std_logic_vector(15 downto 0) := (others => '0'); + TIMEOUT_ERROR : out std_logic := '0' ); end component; @@ -550,5 +553,16 @@ port ( SEL : in std_logic ; DCSOUT : out std_logic) ; end component; + +component dff_re + Port ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + enable : in STD_LOGIC; + d : in STD_LOGIC_VECTOR; + q : out STD_LOGIC_VECTOR; + data_valid : out STD_LOGIC + ); +end component; end package; \ No newline at end of file diff --git a/code/soda_hub.vhd b/code/soda_hub.vhd index 4f6b442..698e8da 100644 --- a/code/soda_hub.vhd +++ b/code/soda_hub.vhd @@ -13,6 +13,7 @@ entity soda_hub is port( SYSCLK : in std_logic; -- fabric clock SODACLK : in std_logic; -- recovered clock + TX_SODACLK : in t_HUB_BIT; -- tx-full clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; @@ -24,7 +25,7 @@ entity soda_hub is TXUP_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0'); TXUP_DLM_PREVIEW_OUT : out std_logic := '0'; --PL! UPLINK_PHASE_IN : in std_logic := '0'; --PL! - + -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM RXDN_DLM_IN : in t_HUB_BIT; RXDN_DLM_WORD_IN : in t_HUB_BYTE; @@ -39,7 +40,7 @@ entity soda_hub is SODA_READ_IN : in std_logic := '0'; SODA_WRITE_IN : in std_logic := '0'; SODA_ACK_OUT : out std_logic := '0'; - LEDS_OUT : out std_logic_vector(3 downto 0); + LEDS_OUT : out std_logic_vector(3 downto 0); LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0') ); end soda_hub; @@ -47,31 +48,52 @@ end soda_hub; architecture Behavioral of soda_hub is --SODA - signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0'); - signal soda_cmd_valid_S : std_logic := '0'; - signal start_of_superburst_S : std_logic := '0'; - signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator - signal crc_data_S : std_logic_vector(7 downto 0) := (others => '0'); - signal crc_valid_S : std_logic := '0'; + signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0'); + signal soda_cmd_valid_S : std_logic := '0'; + signal soda_cmd_strobe_S : std_logic := '0'; -- for commands sent in a SODA package + signal soda_cmd_strobe_sodaclk_S : std_logic := '0'; -- for commands sent in a SODA package + signal trb_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0'); + signal trb_cmd_valid_S : std_logic := '0'; + signal trb_cmd_strobe_S : std_logic := '0'; -- for commands sent over trbnet + signal trb_cmd_strobe_sodaclk_S : std_logic := '0'; -- for commands sent over trbnet +-- signal soda_cmd_pending_S : std_logic := '0'; +-- signal soda_send_cmd_S : std_logic := '0'; + signal start_of_superburst_S : std_logic := '0'; + signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator + signal crc_data_S : std_logic_vector(7 downto 0) := (others => '0'); + signal crc_valid_S : std_logic := '0'; -- Signals type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); signal CURRENT_STATE, NEXT_STATE: STATES; signal last_packet_sent_S : t_PACKET_TYPE_SENT; - signal expected_reply_S : std_logic_vector(7 downto 0); - signal reply_valid_S : t_HUB_BIT_ARRAY; + signal expected_reply_S : t_HUB_BYTE_ARRAY; --std_logic_vector(7 downto 0); + signal reply_data_valid_S : t_HUB_BIT_ARRAY; signal reply_OK_S : t_HUB_BIT_ARRAY; - signal start_of_calibration_S : std_logic := '0'; + signal recv_start_calibration_S : std_logic := '0'; + signal send_start_calibration_S : t_HUB_BIT_ARRAY; signal start_calibration_S : t_HUB_BIT_ARRAY; - signal calibration_valid_S : t_HUB_BIT_ARRAY; + signal calib_data_valid_S : t_HUB_BIT_ARRAY; signal calibration_time_S : t_HUB_WORD_ARRAY; signal calib_register_s : t_HUB_LWORD_ARRAY; - - signal dead_channels_S : t_HUB_BIT_ARRAY; - signal channel_status_S : t_HUB_BIT_ARRAY; - signal status_register : std_logic_vector(31 downto 0) := (others => '0'); - + signal reply_timeout_error_S : t_HUB_BIT_ARRAY; + signal channel_timeout_status_S : t_HUB_BIT_ARRAY; + signal downstream_error_S : t_HUB_BIT_ARRAY; + + signal dead_channel_S : t_HUB_BIT_ARRAY; + + signal CTRL_STATUS_register_S : t_HUB_LWORD_ARRAY; + + signal TXstart_of_superburst_S : t_HUB_BIT_ARRAY; + signal TXsuper_burst_nr_S : t_HUB_LWORD_ARRAY; -- from super-burst-nr-generator + signal TXsoda_cmd_valid_S : t_HUB_BIT_ARRAY; + signal TXsoda_cmd_word_S : t_HUB_LWORD_ARRAY; + + +-- signal channel_status_S : t_HUB_BIT_ARRAY; +-- signal status_register : std_logic_vector(31 downto 0) := (others => '0'); + -- slave bus signals signal bus_ack_x : std_logic; signal bus_ack : std_logic; @@ -82,13 +104,13 @@ architecture Behavioral of soda_hub is signal buf_bus_data_out : std_logic_vector(31 downto 0) := (others => '0'); signal ledregister_i : std_logic_vector(31 downto 0) := (others => '0'); signal txup_dlm_out_S : std_logic; - --- debug - signal debug_status_S : std_logic_vector(31 downto 0) := (others => '0'); - signal debug_rx_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); - signal debug_tx_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); - signal debug_SOS_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); - signal debug_cmd_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); + +-- debug +-- signal debug_status_S : std_logic_vector(31 downto 0) := (others => '0'); +-- signal debug_rx_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); +-- signal debug_tx_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); +-- signal debug_SOS_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); +-- signal debug_cmd_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); begin @@ -100,22 +122,22 @@ begin CLK_EN => '1', --Internal Connection START_OF_SUPERBURST_OUT => start_of_superburst_S, - START_OF_CALIBRATION_OUT => start_of_calibration_S, + START_OF_CALIBRATION_OUT => recv_start_calibration_S, SUPER_BURST_NR_OUT => super_burst_nr_S, SODA_CMD_VALID_OUT => soda_cmd_valid_S, SODA_CMD_WORD_OUT => soda_cmd_word_S, RX_DLM_IN => RXUP_DLM_IN, RX_DLM_WORD_IN => RXUP_DLM_WORD_IN ); - - hub_reply_packet_builder : soda_reply_pkt_builder + + hub_reply_packet_builder : soda_reply_pkt_builder port map( SODACLK => SODACLK, RESET => RESET, CLEAR => '0', CLK_EN => CLK_EN, --Internal Connection - LINK_PHASE_IN => UPLINK_PHASE_IN, + LINK_PHASE_IN => UPLINK_PHASE_IN, START_OF_SUPERBURST => start_of_superburst_S, SUPER_BURST_NR_IN => super_burst_nr_S, SODA_CMD_STROBE_IN => soda_cmd_valid_S, @@ -123,83 +145,139 @@ begin TX_DLM_PREVIEW_OUT => TXUP_DLM_PREVIEW_OUT, TX_DLM_OUT => txup_dlm_out_S, --TX_DLM_OUT, TX_DLM_WORD_OUT => TXUP_DLM_WORD_OUT - ); - + ); + + + channel :for i in c_HUB_CHILDREN-1 downto 0 generate - start_calibration_S(i) <= start_of_calibration_S; - + X_clk_domain : process(TX_SODACLK(i)) + begin + if rising_edge(TX_SODACLK(i)) then + if RESET='1' then + TXsoda_cmd_valid_S(i) <= '0'; + TXstart_of_superburst_S(i) <= '0'; + TXsoda_cmd_word_S(i) <= (others => '0'); + TXsuper_burst_nr_S(i) <= (others => '0'); + else + TXsoda_cmd_valid_S(i) <= soda_cmd_valid_S; + TXstart_of_superburst_S(i) <= start_of_superburst_S; + TXsoda_cmd_word_S(i) <= '0' & soda_cmd_word_S; + TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S; + end if; + end if; + end process; + + + + start_calibration_S(i) <= send_start_calibration_S(i); + packet_builder : soda_packet_builder port map( - SODACLK => SODACLK, + SODACLK => TX_SODACLK(i), RESET => RESET, --Internal Connection - SODA_CMD_STROBE_IN => soda_cmd_valid_S, - START_OF_SUPERBURST => start_of_superburst_S, - SUPER_BURST_NR_IN => super_burst_nr_S, - SODA_CMD_WORD_IN => soda_cmd_word_S, - EXPECTED_REPLY_OUT => open, - TIME_CAL_OUT => open, --start_calibration_S(i), - TX_DLM_PREVIEW_OUT => TXDN_DLM_PREVIEW_OUT(i), - TX_DLM_OUT => TXDN_DLM_OUT(i), - TX_DLM_WORD_OUT => TXDN_DLM_WORD_OUT(i) + SODA_CMD_STROBE_IN => TXsoda_cmd_valid_S(i), + START_OF_SUPERBURST => TXstart_of_superburst_S(i), + SUPER_BURST_NR_IN => TXsuper_burst_nr_S(i)(30 downto 0), + SODA_CMD_WORD_IN => TXsoda_cmd_word_S(i)(30 downto 0), + EXPECTED_REPLY_OUT => expected_reply_S(i), + TIME_CAL_OUT => send_start_calibration_S(i), + TX_DLM_PREVIEW_OUT => TXDN_DLM_PREVIEW_OUT(i), + TX_DLM_OUT => TXDN_DLM_OUT(i), + TX_DLM_WORD_OUT => TXDN_DLM_WORD_OUT(i) ); hub_reply_handler : soda_reply_handler port map( - SODACLK => SODACLK, + SODACLK => TX_SODACLK(i), RESET => RESET, CLEAR => '0', CLK_EN => '1', --Internal Connection -- LAST_PACKET => last_packet_sent_S, - EXPECTED_REPLY_IN => expected_reply_S, + EXPECTED_REPLY_IN => expected_reply_S(i), RX_DLM_IN => RXDN_DLM_IN(i), RX_DLM_WORD_IN => RXDN_DLM_WORD_IN(i), - REPLY_VALID_OUT => reply_valid_S(i), + REPLY_VALID_OUT => reply_data_valid_S(i), REPLY_OK_OUT => reply_OK_S(i) ); hub_calibration_timer : soda_calibration_timer port map( - SODACLK => SODACLK, + SODACLK => TX_SODACLK(i), RESET => RESET, CLEAR => '0', CLK_EN => '1', --Internal Connection START_CALIBRATION => start_calibration_S(i), - END_CALIBRATION => reply_valid_S(i), - CALIB_VALID_OUT => calibration_valid_S(i), - CALIB_TIME_OUT => calibration_time_S(i) + END_CALIBRATION => reply_data_valid_S(i), + VALID_OUT => calib_data_valid_S(i), + CALIB_TIME_OUT => calibration_time_S(i), + TIMEOUT_ERROR => reply_timeout_error_S(i) ); - hub_store_calib_proc : process(SYSCLK) + sodahub_calib_timeout_proc : process(SYSCLK) -- converting to sysclk domain begin if rising_edge(SYSCLK) then if( RESET = '1' ) then - calib_register_S(i) <= (others => '0'); - else - calib_register_S(i)(15 downto 0) <= calibration_time_S(i); + calib_register_S(i) <= (others => '0'); + channel_timeout_status_S(i) <= '0'; + downstream_error_S(i) <= '0'; + CTRL_STATUS_register_S(i)(16) <= '0'; -- reset DOWNSTREAM_ERROR status-bit + CTRL_STATUS_register_S(i)(17) <= '0'; -- reset DOWNSTREAM_ERROR status-bit + CTRL_STATUS_register_S(i)(31) <= '0'; -- reset REPORT_ERROR status-bit + elsif (calib_data_valid_S(i) = '1') then -- calibration finished in time + calib_register_S(i) <= x"0000" & calibration_time_S(i); + channel_timeout_status_S(i) <= '0'; + elsif (reply_data_valid_S(i) = '1') then -- the reply was correct + channel_timeout_status_S(i) <= '0'; + if (reply_OK_S(i) = '1') then + downstream_error_S(i) <= '0'; + elsif (dead_channel_S(i) = '0') then + downstream_error_S(i) <= '1'; + CTRL_STATUS_register_S(i)(16) <= '1'; -- set DOWNSTREAM_ERROR status-bit + CTRL_STATUS_register_S(i)(31) <= '1'; -- set REPORT_ERROR status-bit + end if; + elsif ((reply_timeout_error_S(i) = '1') and (reply_OK_S(i) = '1')) then + channel_timeout_status_S(i) <= '1'; + CTRL_STATUS_register_S(i)(17) <= '1'; -- set CALIBRATION_TIMEOUT_ERROR status-bit + CTRL_STATUS_register_S(i)(31) <= '1'; -- set REPORT_ERROR status-bit + elsif (CTRL_STATUS_register_S(i)(15) = '1') then -- check if slowcontrol wants to reset errors + CTRL_STATUS_register_S(i)(16) <= '0'; -- reset DOWNSTREAM_ERROR status-bit + CTRL_STATUS_register_S(i)(17) <= '0'; -- reset DOWNSTREAM_ERROR status-bit + CTRL_STATUS_register_S(i)(31) <= '0'; -- reset REPORT_ERROR status-bit end if; end if; end process; +-- hub_store_calib_proc : process(SYSCLK) +-- begin +-- if rising_edge(SYSCLK) then +-- if( RESET = '1' ) then +-- calib_register_S(i) <= (others => '0'); +-- else +-- calib_register_S(i)(15 downto 0) <= calibration_time_S(i); +-- end if; +-- end if; +-- end process; + ----------------------------------------------------------- -- Reply status report -- ----------------------------------------------------------- - reply_report_proc : process(SYSCLK) - begin - if rising_edge(SYSCLK) then - if( RESET = '1' ) then - channel_status_S(i) <= '0'; - elsif (reply_valid_S(i)='1') then - channel_status_S(i) <= reply_OK_S(i) or dead_channels_S(i); - else - channel_status_S(i) <= '0'; - end if; - end if; - - end process; +-- reply_report_proc : process(SYSCLK) +-- begin +-- if rising_edge(SYSCLK) then +-- if( RESET = '1' ) then +-- channel_status_S(i) <= '0'; +-- elsif (reply_data_valid_S(i)='1') then +-- channel_status_S(i) <= reply_OK_S(i) or dead_channels_S(i); +-- else +-- channel_status_S(i) <= '0'; +-- end if; +-- end if; +-- +-- end process; end generate; @@ -308,12 +386,37 @@ end process TRANSFORM; begin if( rising_edge(SYSCLK) ) then if ( RESET = '1' ) then - LEDregister_i <= (others => '0'); - elsif( (store_wr = '1') and (SODA_ADDR_IN = B"0000") ) then - LEDregister_i <= SODA_DATA_IN; + trb_cmd_strobe_S <= '0'; + trb_cmd_word_S <= (others => '0'); + CTRL_STATUS_register_S(0)(15 downto 0) <= (others => '0'); + CTRL_STATUS_register_S(1)(15 downto 0) <= (others => '0'); + CTRL_STATUS_register_S(2)(15 downto 0) <= (others => '0'); + CTRL_STATUS_register_S(3)(15 downto 0) <= (others => '0'); + elsif( (store_wr = '1') and (SODA_ADDR_IN = "0000") ) then + trb_cmd_strobe_S <= '1'; + trb_cmd_word_S <= SODA_DATA_IN(30 downto 0); + elsif( (store_wr = '1') and (SODA_ADDR_IN = "0001") ) then + trb_cmd_strobe_S <= '0'; + CTRL_STATUS_register_S(0)(15 downto 0) <= SODA_DATA_IN(15 downto 0); -- use only the 16 lower bits for control + elsif( (store_wr = '1') and (SODA_ADDR_IN = "0010") ) then + trb_cmd_strobe_S <= '0'; + CTRL_STATUS_register_S(1)(15 downto 0) <= SODA_DATA_IN(15 downto 0); -- use only the 16 lower bits for control + elsif( (store_wr = '1') and (SODA_ADDR_IN = "0011") ) then + trb_cmd_strobe_S <= '0'; + CTRL_STATUS_register_S(2)(15 downto 0) <= SODA_DATA_IN(15 downto 0); -- use only the 16 lower bits for control + elsif( (store_wr = '1') and (SODA_ADDR_IN = "0100") ) then + trb_cmd_strobe_S <= '0'; + CTRL_STATUS_register_S(3)(15 downto 0) <= SODA_DATA_IN(15 downto 0); -- use only the 16 lower bits for control + else + trb_cmd_strobe_S <= '0'; end if; end if; end process THE_WRITE_REG_PROC; + + dead_channel_S(0) <= CTRL_STATUS_register_S(0)(8); -- slow-control can declare a channel dead + dead_channel_S(1) <= CTRL_STATUS_register_S(1)(8); -- slow-control can declare a channel dead + dead_channel_S(2) <= CTRL_STATUS_register_S(2)(8); -- slow-control can declare a channel dead + dead_channel_S(3) <= CTRL_STATUS_register_S(3)(8); -- slow-control can declare a channel dead -- register read THE_READ_REG_PROC: process( SYSCLK ) @@ -325,50 +428,66 @@ end process TRANSFORM; buf_bus_data_out <= '0' & soda_cmd_word_S; elsif( (store_rd = '1') and (SODA_ADDR_IN = "0001") ) then buf_bus_data_out <= '0' & super_burst_nr_S; - elsif( (store_rd = '1') and (SODA_ADDR_IN = "0010") ) then - buf_bus_data_out <= LEDregister_i; - elsif( (store_rd = '1') and (SODA_ADDR_IN = "0011") ) then - buf_bus_data_out <= debug_status_S; elsif( (store_rd = '1') and (SODA_ADDR_IN = "0100") ) then - buf_bus_data_out <= debug_rx_cnt_S; + buf_bus_data_out <= calib_register_S(0); elsif( (store_rd = '1') and (SODA_ADDR_IN = "0101") ) then - buf_bus_data_out <= debug_tx_cnt_S; + buf_bus_data_out <= calib_register_S(0); elsif( (store_rd = '1') and (SODA_ADDR_IN = "0110") ) then - buf_bus_data_out <= debug_sos_cnt_S; + buf_bus_data_out <= calib_register_S(0); elsif( (store_rd = '1') and (SODA_ADDR_IN = "0111") ) then - buf_bus_data_out <= debug_cmd_cnt_S; + buf_bus_data_out <= calib_register_S(0); + elsif( (store_rd = '1') and (SODA_ADDR_IN = "0011") ) then + buf_bus_data_out <= CTRL_STATUS_register_S(0); + elsif( (store_rd = '1') and (SODA_ADDR_IN = "0100") ) then + buf_bus_data_out <= CTRL_STATUS_register_S(1); + elsif( (store_rd = '1') and (SODA_ADDR_IN = "0101") ) then + buf_bus_data_out <= CTRL_STATUS_register_S(2); + elsif( (store_rd = '1') and (SODA_ADDR_IN = "0110") ) then + buf_bus_data_out <= CTRL_STATUS_register_S(3); end if; end if; end process THE_READ_REG_PROC; - --- debug signals - DEBUG_HUB : process(SODACLK) - begin - if( rising_edge(SODACLK) ) then - debug_status_S(0) <= RESET; - debug_status_S(1) <= CLEAR; - debug_status_S(2) <= CLK_EN; - if ( RESET = '1' ) then - debug_rx_cnt_S <= (others => '0'); - debug_tx_cnt_S <= (others => '0'); - else - if (txup_dlm_out_S = '1') then - debug_tx_cnt_S <= debug_tx_cnt_S + 1; - end if; - if (RXUP_DLM_IN = '1') then - debug_rx_cnt_S <= debug_rx_cnt_S + 1; - end if; - if (start_of_superburst_S = '1') then - debug_sos_cnt_S <= debug_sos_cnt_S + 1; - end if; - if (soda_cmd_valid_S = '1') then - debug_cmd_cnt_S <= debug_cmd_cnt_S + 1; - end if; - end if; - end if; - end process; - - debug_status_S(31 downto 3) <= LINK_DEBUG_IN(31 downto 3); +-- buf_bus_data_out <= debug_status_S; +-- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0100") ) then +-- buf_bus_data_out <= debug_rx_cnt_S; +-- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0101") ) then +-- buf_bus_data_out <= debug_tx_cnt_S; +-- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0110") ) then +-- buf_bus_data_out <= debug_sos_cnt_S; +-- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0111") ) then +-- buf_bus_data_out <= debug_cmd_cnt_S; +-- end if; +-- end if; +-- end process THE_READ_REG_PROC; + +-- debug signals + --DEBUG_HUB : process(SODACLK) + --begin + --if( rising_edge(SODACLK) ) then + --debug_status_S(0) <= RESET; + --debug_status_S(1) <= CLEAR; + --debug_status_S(2) <= CLK_EN; + --if ( RESET = '1' ) then + --debug_rx_cnt_S <= (others => '0'); + --debug_tx_cnt_S <= (others => '0'); + --else + --if (txup_dlm_out_S = '1') then + --debug_tx_cnt_S <= debug_tx_cnt_S + 1; + --end if; + --if (RXUP_DLM_IN = '1') then + --debug_rx_cnt_S <= debug_rx_cnt_S + 1; + --end if; + --if (start_of_superburst_S = '1') then + --debug_sos_cnt_S <= debug_sos_cnt_S + 1; + --end if; + --if (soda_cmd_valid_S = '1') then + --debug_cmd_cnt_S <= debug_cmd_cnt_S + 1; + --end if; + --end if; + --end if; + --end process; + + --debug_status_S(31 downto 3) <= LINK_DEBUG_IN(31 downto 3); TXUP_DLM_OUT <= txup_dlm_out_S; -- output signals LEDS_OUT <= LEDregister_i(3 downto 0); @@ -376,4 +495,4 @@ end process TRANSFORM; SODA_DATA_OUT <= buf_bus_data_out; SODA_ACK_OUT <= bus_ack; -end architecture; +end architecture; \ No newline at end of file diff --git a/code/soda_source.vhd b/code/soda_source.vhd index 5f1b223..4f83cdc 100644 --- a/code/soda_source.vhd +++ b/code/soda_source.vhd @@ -53,26 +53,32 @@ architecture Behavioral of soda_source is -- signal last_packet_sent_S : t_PACKET_TYPE_SENT := c_NO_PACKET; -- slave bus signals - signal bus_ack_x : std_logic; - signal bus_ack : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; - signal buf_bus_data_out : std_logic_vector(31 downto 0); + signal bus_ack_x : std_logic; + signal bus_ack : std_logic; + signal store_wr_x : std_logic; + signal store_wr : std_logic; + signal store_rd_x : std_logic; + signal store_rd : std_logic; + signal buf_bus_data_out : std_logic_vector(31 downto 0); - signal ledregister_i : std_logic_vector(31 downto 0); - signal test_line_i : std_logic_vector(31 downto 0); + signal CTRL_STATUS_register_i : std_logic_vector(31 downto 0); + signal test_line_i : std_logic_vector(31 downto 0); - signal reply_valid_S : std_logic; - signal expected_reply_S : std_logic_vector(7 downto 0); - signal reply_OK_S : std_logic; - signal start_calibration_S : std_logic; + signal reply_data_valid_S : std_logic; + signal expected_reply_S : std_logic_vector(7 downto 0); + signal reply_OK_S : std_logic; + signal start_calibration_S : std_logic; + + signal calib_data_valid_S : std_logic; + signal calibration_time_s : std_logic_vector(15 downto 0) := (others => '0'); + signal calib_register_s : std_logic_vector(31 downto 0) := (others => '0'); +-- signal calib_register_rst_s : std_logic := '0'; -- read of calibration register resets contents to 0 + signal reply_timeout_error_S : std_logic; + signal channel_timeout_status_S : std_logic; + signal downstream_error_S : std_logic; + + signal dead_channel_S : std_logic; - signal calibration_valid_s : std_logic; - signal calibration_time_s : std_logic_vector(15 downto 0) := (others => '0'); - signal calib_register_s : std_logic_vector(31 downto 0) := (others => '0'); --- signal calib_register_rst_s : std_logic := '0'; -- read of calibration register resets contents to 0 begin @@ -115,8 +121,8 @@ begin EXPECTED_REPLY_IN => expected_reply_S, RX_DLM_IN => RX_DLM_IN, RX_DLM_WORD_IN => RX_DLM_WORD_IN, - REPLY_VALID_OUT => reply_valid_S, - REPLY_OK_OUT => reply_OK_S + REPLY_VALID_OUT => reply_data_valid_S, -- there was a reply + REPLY_OK_OUT => reply_OK_S -- the reply was as expected ); src_calibration_timer : soda_calibration_timer @@ -127,23 +133,48 @@ begin CLK_EN => '1', --Internal Connection START_CALIBRATION => start_calibration_S, - END_CALIBRATION => reply_valid_S, - CALIB_VALID_OUT => calibration_valid_S, - CALIB_TIME_OUT => calibration_time_S + END_CALIBRATION => reply_data_valid_S, + VALID_OUT => calib_data_valid_S, + CALIB_TIME_OUT => calibration_time_S, + TIMEOUT_ERROR => reply_timeout_error_S -- timeout because no reply was received ); - src_store_calib_proc : process(SYSCLK) -- converting to sysclk domain + sodasource_calib_timeout_proc : process(SYSCLK) -- converting to sysclk domain begin if rising_edge(SYSCLK) then if( RESET = '1' ) then - calib_register_S <= (others => '0'); - else - calib_register_S(15 downto 0) <= calibration_time_S; + calib_register_S <= (others => '0'); + channel_timeout_status_S <= '0'; + downstream_error_S <= '0'; + CTRL_STATUS_register_i(16) <= '0'; -- reset DOWNSTREAM_ERROR status-bit + CTRL_STATUS_register_i(17) <= '0'; -- reset DOWNSTREAM_ERROR status-bit + CTRL_STATUS_register_i(31) <= '0'; -- reset REPORT_ERROR status-bit + elsif (calib_data_valid_S = '1') then -- calibration finished in time + calib_register_S(15 downto 0) <= calibration_time_S; + channel_timeout_status_S <= '0'; + elsif (reply_data_valid_S = '1') then -- the reply was correct + channel_timeout_status_S <= '0'; + if (reply_OK_S = '1') then + downstream_error_S <= '0'; + elsif (dead_channel_S = '0') then + downstream_error_S <= '1'; + CTRL_STATUS_register_i(16) <= '1'; -- set DOWNSTREAM_ERROR status-bit + CTRL_STATUS_register_i(31) <= '1'; -- set REPORT_ERROR status-bit + end if; + elsif ((reply_timeout_error_S = '1') and (reply_OK_S = '1')) then + channel_timeout_status_S <= '1'; + CTRL_STATUS_register_i(17) <= '1'; -- set CALIBRATION_TIMEOUT_ERROR status-bit + CTRL_STATUS_register_i(31) <= '1'; -- set REPORT_ERROR status-bit + elsif (CTRL_STATUS_register_i(15) = '1') then -- check if slowcontrol wants to reset errors + CTRL_STATUS_register_i(16) <= '0'; -- reset DOWNSTREAM_ERROR status-bit + CTRL_STATUS_register_i(17) <= '0'; -- reset DOWNSTREAM_ERROR status-bit + CTRL_STATUS_register_i(31) <= '0'; -- reset REPORT_ERROR status-bit end if; end if; end process; + --------------------------------------------------------- -- RegIO Statemachine --------------------------------------------------------- @@ -246,20 +277,21 @@ soda_cmd_strobe_posedge_to_pulse: posedge_to_pulse if ( RESET = '1' ) then soda_cmd_strobe_S <= '0'; soda_cmd_word_S <= (others => '0'); - LEDregister_i <= (others => '0'); --- TEST_LINE_i <= (others => '0'); + CTRL_STATUS_register_i(15 downto 0) <= (others => '0'); elsif( (store_wr = '1') and (SODA_ADDR_IN = "0000") ) then soda_cmd_strobe_S <= '1'; soda_cmd_word_S <= SODA_DATA_IN(30 downto 0); elsif( (store_wr = '1') and (SODA_ADDR_IN = "0001") ) then soda_cmd_strobe_S <= '0'; - LEDregister_i <= SODA_DATA_IN; + CTRL_STATUS_register_i(15 downto 0) <= SODA_DATA_IN(15 downto 0); -- use only the 16 lower bits for control else soda_cmd_strobe_S <= '0'; end if; end if; end process THE_WRITE_REG_PROC; - + + dead_channel_S <= CTRL_STATUS_register_i(8); -- slow-control can declare a channel dead + -- register read THE_READ_REG_PROC: process( SYSCLK ) @@ -273,17 +305,14 @@ soda_cmd_strobe_posedge_to_pulse: posedge_to_pulse buf_bus_data_out <= '0' & super_burst_nr_S; elsif( (store_rd = '1') and (SODA_ADDR_IN = "0010") ) then buf_bus_data_out <= calib_register_S; --- calib_register_rst_S <= '1'; elsif( (store_rd = '1') and (SODA_ADDR_IN = "0011") ) then - buf_bus_data_out <= LEDregister_i; --- else --- calib_register_rst_S <= '0'; + buf_bus_data_out <= CTRL_STATUS_register_i; end if; end if; end process THE_READ_REG_PROC; -- output signals - LEDS_OUT <= LEDregister_i(3 downto 0); + LEDS_OUT <= CTRL_STATUS_register_i(3 downto 0); SODA_DATA_OUT <= buf_bus_data_out; SODA_ACK_OUT <= bus_ack; diff --git a/code/trb3_periph_sodahub.vhd b/code/trb3_periph_sodahub.vhd index ae61142..1a5ee3f 100644 --- a/code/trb3_periph_sodahub.vhd +++ b/code/trb3_periph_sodahub.vhd @@ -178,6 +178,7 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is signal soda_rxup_clock_full : std_logic; -- signal soda_rxdn_clock_half : t_HUB_BIT; signal soda_rxdn_clock_full : t_HUB_BIT; + signal soda_txdn_clock_full : t_HUB_BIT; signal make_reset : std_logic; --SODA uplink @@ -492,7 +493,6 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up CTRL_DEBUG => (others => '0') ); --- SFP_TXDIS(3) <= sfp_txdis_S; SFP_TXDIS <= sfp_txdis_S; --------------------------------------------------------------------------- @@ -503,6 +503,7 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up port map( SYSCLK => clk_sys_internal, --clk_sys_i, SODACLK => clk_soda_i, + TX_SODACLK => soda_txdn_clock_full, -- This is 4 clocks !! RESET => reset_i, CLEAR => clear_i, CLK_EN => '1', @@ -610,10 +611,10 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up CLK_TX_HALF_OUT(2) => open, CLK_TX_HALF_OUT(3) => open, - CLK_TX_FULL_OUT(0) => open, - CLK_TX_FULL_OUT(1) => open, - CLK_TX_FULL_OUT(2) => open, - CLK_TX_FULL_OUT(3) => open, + CLK_TX_FULL_OUT(0) => soda_txdn_clock_full(0), + CLK_TX_FULL_OUT(1) => soda_txdn_clock_full(1), + CLK_TX_FULL_OUT(2) => soda_txdn_clock_full(2), + CLK_TX_FULL_OUT(3) => soda_txdn_clock_full(3), RX_DLM(0) => rxdn_dlm_i(0), RX_DLM(1) => rxdn_dlm_i(1), diff --git a/code/trb3_periph_sodasource.vhd b/code/trb3_periph_sodasource.vhd index 6691f84..1706a74 100644 --- a/code/trb3_periph_sodasource.vhd +++ b/code/trb3_periph_sodasource.vhd @@ -225,35 +225,31 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is --SODA signal SOB_S : std_logic := '0'; -- fix signal names for constraining - attribute syn_preserve of CLK_GPLL_LEFT : signal is true; - attribute syn_keep of CLK_GPLL_LEFT : signal is true; --- attribute syn_noprune of CLK_GPLL_LEFT : signal is true; - attribute syn_preserve of CLK_GPLL_RIGHT : signal is true; - attribute syn_keep of CLK_GPLL_RIGHT : signal is true; --- attribute syn_noprune of CLK_GPLL_RIGHT : signal is true; - attribute syn_preserve of CLK_PCLK_LEFT : signal is true; - attribute syn_keep of CLK_PCLK_LEFT : signal is true; --- attribute syn_noprune of CLK_PCLK_LEFT : signal is true; - attribute syn_preserve of CLK_PCLK_RIGHT : signal is true; - attribute syn_keep of CLK_PCLK_RIGHT : signal is true; --- attribute syn_noprune of CLK_PCLK_RIGHT : signal is true; - -attribute syn_preserve of soda_rx_clock_full : signal is true; - attribute syn_keep of soda_rx_clock_full : signal is true; - attribute syn_preserve of soda_rx_clock_half : signal is true; - attribute syn_keep of soda_rx_clock_half : signal is true; - attribute syn_preserve of soda_tx_clock_full : signal is true; - attribute syn_keep of soda_tx_clock_full : signal is true; - attribute syn_preserve of soda_tx_clock_half : signal is true; - attribute syn_keep of soda_tx_clock_half : signal is true; - attribute syn_preserve of clk_sys_internal : signal is true; - attribute syn_keep of clk_sys_internal : signal is true; - attribute syn_preserve of clk_raw_internal : signal is true; - attribute syn_keep of clk_raw_internal : signal is true; - attribute syn_preserve of tx_dlm_i : signal is true; - attribute syn_keep of tx_dlm_i : signal is true; - attribute syn_preserve of rx_dlm_i : signal is true; - attribute syn_keep of rx_dlm_i : signal is true; + attribute syn_preserve of CLK_GPLL_LEFT : signal is true; + attribute syn_keep of CLK_GPLL_LEFT : signal is true; + attribute syn_preserve of CLK_GPLL_RIGHT : signal is true; + attribute syn_keep of CLK_GPLL_RIGHT : signal is true; + attribute syn_preserve of CLK_PCLK_LEFT : signal is true; + attribute syn_keep of CLK_PCLK_LEFT : signal is true; + attribute syn_preserve of CLK_PCLK_RIGHT : signal is true; + attribute syn_keep of CLK_PCLK_RIGHT : signal is true; + + attribute syn_preserve of soda_rx_clock_full : signal is true; + attribute syn_keep of soda_rx_clock_full : signal is true; + attribute syn_preserve of soda_rx_clock_half : signal is true; + attribute syn_keep of soda_rx_clock_half : signal is true; + attribute syn_preserve of soda_tx_clock_full : signal is true; + attribute syn_keep of soda_tx_clock_full : signal is true; + attribute syn_preserve of soda_tx_clock_half : signal is true; + attribute syn_keep of soda_tx_clock_half : signal is true; + attribute syn_preserve of clk_sys_internal : signal is true; + attribute syn_keep of clk_sys_internal : signal is true; + attribute syn_preserve of clk_raw_internal : signal is true; + attribute syn_keep of clk_raw_internal : signal is true; + attribute syn_preserve of tx_dlm_i : signal is true; + attribute syn_keep of tx_dlm_i : signal is true; + attribute syn_preserve of rx_dlm_i : signal is true; + attribute syn_keep of rx_dlm_i : signal is true; begin @@ -278,7 +274,7 @@ begin CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) DEBUG_OUT => open - ); + ); --------------------------------------------------------------------------- @@ -326,7 +322,7 @@ end generate; ) port map( CLK => clk_raw_internal, - SYSCLK => clk_sys_internal, --clk_sys_i, + SYSCLK => clk_sys_internal, RESET => reset_i, CLEAR => clear_i, CLK_EN => '1', @@ -392,7 +388,7 @@ THE_HUB : trb_net16_hub_base CLOCK_FREQUENCY => CLOCK_FREQUENCY ) port map ( - CLK => clk_sys_internal, --clk_sys_i, + CLK => clk_sys_internal, --clk_sys_i, PL! 30062014 RESET => reset_i, CLK_EN => '1', @@ -444,8 +440,8 @@ THE_HUB : trb_net16_hub_base PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0) ) port map( - CLK => clk_sys_internal, --clk_sys_i, - RESET => reset_i, + CLK => clk_sys_internal, + RESET => reset_i, DAT_ADDR_IN => regio_addr_out, DAT_DATA_IN => regio_data_out, @@ -525,8 +521,8 @@ THE_HUB : trb_net16_hub_base THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch port map( - CLK_IN => clk_sys_internal, --clk_sys_i, - RESET_IN => reset_i, + CLK_IN => clk_sys_internal, + RESET_IN => reset_i, BUS_ADDR_IN => spimem_addr, BUS_READ_IN => spimem_read_en, @@ -558,12 +554,10 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_down IS_SYNC_SLAVE => c_NO ) port map( - CLK => clk_raw_internal, --clk_200_i, - SYSCLK => clk_sys_internal, --clk_sys_i, - RESET => reset_i, + CLK => clk_raw_internal, + SYSCLK => clk_sys_internal, + RESET => reset_i, CLEAR => clear_i, --- PCSA_REFCLKP => PCSA_REFCLKP, -- external refclock straight into serdes PL! --- PCSA_REFCLKN => PCSA_REFCLKN, -- external refclock straight into serdes PL! --Internal Connection for TrbNet data -> not used a.t.m. MED_DATA_IN => med_data_out(31 downto 16), MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3), @@ -621,7 +615,7 @@ THE_SOB_SOURCE : soda_start_of_burst_faker BURST_PERIOD => cBURST_PERIOD -- burst-period in ns ) port map( - SYSCLK => clk_sys_internal, --soda_rx_clock_half, -- + SYSCLK => soda_tx_clock_half, --clk_sys_internal, PL! 30062014 RESET => reset_i, SODA_BURST_PULSE_OUT => SOB_S ); @@ -630,8 +624,8 @@ THE_SOB_SOURCE : soda_start_of_burst_faker THE_SODA_SOURCE : soda_source port map( - SYSCLK => clk_sys_internal, --clk_sys_i, - SODACLK => clk_raw_internal, + SYSCLK => soda_tx_clock_half, --clk_sys_internal, --clk_sys_i, PL! 30062014 + SODACLK => soda_tx_clock_full, --clk_raw_internal, PL! 30062014 RESET => reset_i, --Internal Connection SODA_BURST_PULSE_IN => SOB_S, @@ -652,21 +646,22 @@ THE_SODA_SOURCE : soda_source ); ---alive : soda_clockscaler --- port map( --- CLK => clk_raw_internal, --- RESET => reset_i, --- CLOCK_ENABLE_OUT => open, --- CLOCK_OUT => LED_GREEN --- ); +raw : soda_clockscaler + port map( + CLK => clk_raw_internal, + RESET => reset_i, + CLOCK_ENABLE_OUT => open, + CLOCK_OUT => open + ); ---rx_alive : soda_clockscaler --- port map( --- CLK => soda_rx_clock_full, --- RESET => reset_i, --- CLOCK_ENABLE_OUT => open, --- CLOCK_OUT => LED_RED --- ); +tx : soda_clockscaler + port map( + CLK => soda_tx_clock_full, + RESET => reset_i, + CLOCK_ENABLE_OUT => open, + CLOCK_OUT => open + + ); --------------------------------------------------------------------------- @@ -694,7 +689,7 @@ THE_SODA_SOURCE : soda_source --------------------------------------------------------------------------- process begin - wait until rising_edge(clk_sys_internal); + wait until rising_edge(soda_tx_clock_half); --clk_sys_internal); PL! 30062014 time_counter <= time_counter + 1; end process; diff --git a/soda_client.ldf b/soda_client.ldf index 5b10566..ab0653e 100644 --- a/soda_client.ldf +++ b/soda_client.ldf @@ -4,7 +4,7 @@