From: Jan Michel Date: Fri, 5 Sep 2014 14:27:36 +0000 (+0200) Subject: latest adc handler. acknowledges triggers, no readout X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5663dbde877907539220e426bd58465d8c87704a;p=trb3.git latest adc handler. acknowledges triggers, no readout --- diff --git a/.gitignore b/.gitignore index e47ec1a..3bd1b81 100644 --- a/.gitignore +++ b/.gitignore @@ -26,3 +26,9 @@ padiwa/project* ADC/test* */project/ */project2/ +modelsim.ini +*.mti +*.bak +work +*.wlf +*stacktrace.txt diff --git a/ADC/compile_constraints.pl b/ADC/compile_constraints.pl new file mode 100755 index 0000000..5644d4b --- /dev/null +++ b/ADC/compile_constraints.pl @@ -0,0 +1,9 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; + +my $TOPNAME = "trb3_periph_adc"; #Name of top-level entity + +system("cp ../base/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); diff --git a/ADC/compile_periph_frankfurt.pl b/ADC/compile_periph_frankfurt.pl index 3d739dc..cc76833 100755 --- a/ADC/compile_periph_frankfurt.pl +++ b/ADC/compile_periph_frankfurt.pl @@ -2,7 +2,7 @@ use Data::Dumper; use warnings; use strict; - +use FileHandle; @@ -17,14 +17,10 @@ my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; $ENV{'PAR_DESIGN_NAME'}=$TOPNAME; - - -use FileHandle; - $ENV{'SYNPLIFY'}=$synplify_path; $ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; - +my $tpmap = $TOPNAME . "_map" ; my $FAMILYNAME="LatticeECP3"; @@ -33,65 +29,16 @@ my $PACKAGE="FPBGA672"; my $SPEEDGRADE="8"; -#create full lpf file -system("cp ../base/$TOPNAME.lpf workdir/$TOPNAME.lpf"); -system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); - - -#set -e -#set -o errexit - -#generate timestamp -my $t=time; -my $fh = new FileHandle(">version.vhd"); -die "could not open file" if (! defined $fh); -print $fh <close; - -system("env| grep LM_"); -my $r = ""; my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; -$r=execute($c, "do_not_exit" ); - - -chdir "workdir"; -$fh = new FileHandle("<$TOPNAME".".srr"); -my @a = <$fh>; -$fh -> close; - - - -foreach (@a) -{ - if(/\@E:/) - { - print "\n"; - $c="cat $TOPNAME.srr | grep \"\@E\""; - system($c); - print "\n\n"; - exit 129; - } -} - +my $r=execute($c, "do_not_exit" ); +checksrr(); $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; - $c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; execute($c); @@ -101,8 +48,6 @@ execute($c); $c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; execute($c); -my $tpmap = $TOPNAME . "_map" ; - $c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; execute($c); @@ -112,9 +57,13 @@ system("rm $TOPNAME.ncd"); # $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; $c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 3 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|; execute($c); -# IOR IO Timing Report -# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -# execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf &|; +# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); # TWR Timing Report $c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; @@ -123,30 +72,45 @@ execute($c); $c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); -$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; -# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +#IOR IO Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); chdir ".."; exit; + + + sub execute { - my ($c, $op) = @_; - #print "option: $op \n"; - $op = "" if(!$op); - print "\n\ncommand to execute: $c \n"; - $r=system($c); - if($r) { - print "$!"; - if($op ne "do_not_exit") { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { exit; - } + } } - - return $r; - -} + return $r; + } + + +sub checksrr { + chdir "workdir"; + my $fh = new FileHandle("<$TOPNAME".".srr"); + my @a = <$fh>; + $fh -> close; + foreach (@a) { + if(/\@E:/) { + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); + print "\n\n"; + exit 129; + } + } + } \ No newline at end of file diff --git a/ADC/compile_periph_gsi.pl b/ADC/compile_periph_gsi.pl index f75159f..3f8e4af 100755 --- a/ADC/compile_periph_gsi.pl +++ b/ADC/compile_periph_gsi.pl @@ -47,8 +47,7 @@ unless(-d $WORKDIR) { # create full lpf file -system("cp ../base/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf"); -system("cat ".$TOPNAME."_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); +system ("./compile_constraints.pl"); # generate timestamp diff --git a/ADC/sim/adcprocessor.mpf b/ADC/sim/adcprocessor.mpf new file mode 100644 index 0000000..4e80e31 --- /dev/null +++ b/ADC/sim/adcprocessor.mpf @@ -0,0 +1,1808 @@ +; Copyright 1991-2012 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +vital2000 = $MODEL_TECH/../vital2000 +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; +verilog = $MODEL_TECH/../verilog +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std +mtiAvm = $MODEL_TECH/../avm +mtiOvm = $MODEL_TECH/../ovm-2.1.2 +mtiUvm = $MODEL_TECH/../uvm-1.1c +mtiUPF = $MODEL_TECH/../upf_lib +mtiPA = $MODEL_TECH/../pa_lib +floatfixlib = $MODEL_TECH/../floatfixlib +mc2_lib = $MODEL_TECH/../mc2_lib +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Run the 0-in compiler on the VHDL source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a FEC table, implementing +; a condition coverage or expression coverage expression, by changing FecEffort. +; Higher FecEffort leads to a longer compile time, but more expressions covered. +; This is a number from 1 to 3, with the following meanings (the default is 1): +; 3 -- High FecEffort, Allows large expressions to be covered, will cause longer compile time. +; 2 -- Medium FecEffort, Allows more number of inputs per expression than Low FecEffort to be covered. +; 1 -- Low FecEffort, Covers only small expressions or conditions and skips larger ones. +; FecEffort = 2 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn on `protect compiler directive processing. +; Default is to ignore `protect directives. +; Protect = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with depth equal to or more than the sparse memory threshold gets +; marked as sparse automatically, unless specified otherwise in source code +; or by +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with depth equal +; to or greater than 1M are marked as sparse) +; SparseMemThreshold = 1048576 + +; Run the 0-in compiler on the Verilog source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a FEC table, implementing +; a condition coverage or expression coverage expression, by changing FecEffort. +; Higher FecEffort leads to a longer compile time, but more expressions covered. +; This is a number from 1 to 3, with the following meanings (the default is 1): +; 3 -- High FecEffort, Allows large expressions to be covered, will cause longer compile time. +; 2 -- Medium FecEffort, Allows more number of inputs per expression than Low FecEffort to be covered. +; 1 -- Low FecEffort, Covers only small expressions or conditions and skips larger ones. +; FecEffort = 2 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "merge_instances" option for +; the Covergroup Type. This is a compile time option which forces +; "merge_instances" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupMergeInstancesDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SVFileExtensions = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2001 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "package_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. Valid extensions are "feci", +; "pae", "uslt" and "spsl". +; SVExtensions = uslt,spsl + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Increase or decrease the maximum number of rows allowed in a FEC table, implementing +; a condition coverage or expression coverage expression, by changing FecEffort. +; Higher FecEffort leads to a longer compile time, but more expressions covered. +; This is a number from 1 to 3, with the following meanings (the default is 1): +; 3 -- High FecEffort, Allows large expressions to be covered, will cause longer compile time. +; 2 -- Medium FecEffort, Allows more number of inputs per expression than Low FecEffort to be covered. +; 1 -- Low FecEffort, Covers only small expressions or conditions and skips larger ones. +; FecEffort = 2 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. Valid extensions are "feci", +; "pae", "uslt" and "spsl". +; SVExtensions = uslt,spsl + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 50 us + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer and vsim-viewer license +; features (PE ONLY) +; noslvhdl Disable checkout of qhsimvh and vsim license features +; noslvlog Disable checkout of qhsimvl and vsimvlog license features +; nomix Disable checkout of msimhdlmix and hdlmix license features +; nolnl Disable checkout of msimhdlsim and hdlsim license features +; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license +; features +; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix, +; hdlmix license features +; Single value: +; License = plus +; Multi-value: +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog immediate assertions that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is 0 (disabled). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase +DefaultRadix = symbolic +;DefaultRadixFlags = showbase + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR generate statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Uncomment this to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable changes in VHDL elaboration to allow for Variable Logging +; This trades off simulation performance for the ability to log variables +; efficiently. By default this is disable for maximum simulation performance +; VhdlVariableLogging = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = /bin/gcc + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; The default is UVMControl = struct + +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file. +; Value is the number of seconds between updated. After at least the +; interval number of seconds, the wlf file is flushed, ensuring that the data +; is correct when viewed from a separate live viewer. Setting to 0 means no +; updating. Default is 10 seconds, which has a tiny performance impact +; WLFUpdateInterval = 10 + +; Specify the WLF reader cache size limit for each open WLF file. +; The size is giving in megabytes. A value of 0 turns off the +; WLF cache. +; WLFSimCacheSize allows a different cache size to be set for +; simulation WLF file independent of post-simulation WLF file +; viewing. If WLFSimCacheSize is not set it defaults to the +; WLFCacheSize setting. +; The default WLFCacheSize setting is enabled to 2000M per open WLF file on most +; platforms; on Windows, the setting is 1000M to help avoid filling process memory. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines +; if 0, no threads will be used, if 1, threads will be used if the system has +; more than one processor +; WLFUseThreads = 1 + +; Specify the relative size of logged objects that will trigger "large object" +; messages at log/wave/list time. This size value is an approximation of +; the number of bytes needed to store the value of the object before compression +; and optimization. +; The default LargeObjectSize size is 500k +; LargeObjectSize = 500000 + +; Specify whether to output "large object" warning messages. +; The default is 0 which means the warning messages will come out. +; LargeObjectSilent = 0 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of run +; 3 == print at end of run and end of simulation +; default == 0 +; PrintSimStats = 1 + + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCover = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; Count all code coverage condition and expression truth table rows that match. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the 6.5 default behavior of covergroup get_coverage() builtin +; functions, GUI, and report. This setting changes the default values of +; type_option.merge_instances to ensure the 6.5 default behavior if explicit +; assignments are not made on type_option.merge_instances by the user. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SvCovergroupMergeInstancesDefault = 1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup +; MaxSVCoverpointBinsInst = 2147483648 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup +; MaxSVCrossBinsInst = 2147483648 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Run the 0in tools from within the simulator. +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0in runtime tool. +; Default value set to "". +; ZeroInOptions = "" + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify if the solver should attempt to ignore overflow/underflow semantics +; for arithmetic constraints (multiply, addition, subtraction) in order to +; improve performance. The "solveignoreoverflow" attribute can be specified on +; a per-call basis to randomize() to override this setting. +; The default value is 0 (overflow/underflow is not ignored). Set to 1 to +; ignore overflow/underflow. +; SolveIgnoreOverflow = 0 + +; Specifies the maximum size that a dynamic array may be resized to by the +; solver. If the solver attempts to resize a dynamic array to a size greater +; than the specified limit, the solver will abort with an error. +; The default value is 2000. A value of 0 indicates no limit. +; SolveArrayResizeMax = 2000 + +; Error message severity when randomize() failure is detected (SystemVerilog). +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; The default is 0 (no error). +; SolveFailSeverity = 0 + +; Enable/disable debug information for randomize() failures. +; NOTE: This variable can be overridden with the vsim "-solvefaildbug" command +; line switch. +; The default is 0 (disabled). Set to 1 to enable. +; SolveFailDebug = 0 + +; Specify the maximum size of the solution graph generated by the BDD solver. +; This value can be used to force the BDD solver to abort the evaluation of a +; complex constraint scenario that cannot be evaluated with finite memory. +; This value is specified in 1000s of nodes. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Specify the maximum number of evaluations that may be performed on the +; solution graph by the BDD solver. This value can be used to force the BDD +; solver to abort the evaluation of a complex constraint scenario that cannot +; be evaluated in finite time. This value is specified in 10000s of evaluations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Specify the maximum number of tests that the ACT solver may evaluate before +; abandoning an attempt to solve a particular constraint scenario. +; The default value is 2000000. A value of 0 indicates no limit. +; SolveACTMaxTests = 2000000 + +; Specify the maximum number of operations that the ACT solver may perform +; before abandoning an attempt to solve a particular constraint scenario. The +; value is specified in 1000000s of operations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveACTMaxOps = 10000 + +; Specify the number of times the ACT solver will retry to evaluate a constraint +; scenario that fails due to the SolveACTMaxTests threshold. +; The default value is 0 (no retry). +; SolveACTRetryCount = 0 + +; SolveSpeculateLevel controls whether or not the solver performs speculation +; during the evaluation of a constraint scenario. +; Speculation is an attempt to partition complex constraint scenarios by +; choosing a 'speculation' subset of the variables and constraints. This +; 'speculation' set is solved independently of the remaining constraints. +; The solver then attempts to solve the remaining variables and constraints +; (the 'dependent' set). If this attempt fails, the solver backs up and +; re-solves the 'speculation' set, then retries the 'dependent' set. +; Valid values are: +; 0 - no speculation +; 1 - enable speculation that maintains LRM specified distribution +; 2 - enable other speculation - may yield non-LRM distribution +; Currently, distribution constraints and solve-before constraints are +; used in selecting the 'speculation' sets for speculation level 1. Non-LRM +; compliant speculation includes random variables in condition expressions. +; The default value is 0. +; SolveSpeculateLevel = 0 + +; By default, when speculation is enabled, the solver first tries to solve a +; constraint scenario *without* speculation. If the solver fails to evaluate +; the constraint scenario (due to time/memory limits) then the solver will +; re-evaluate the constraint scenario with speculation. If SolveSpeculateFirst +; is set to 1, the solver will skip the initial non-speculative attempt to +; evaluate the constraint scenario. (Only applies when SolveSpeculateLevel is +; non-zero) +; The default value is 0. +; SolveSpeculateFirst = 0 + +; Specify the maximum bit width of a variable in a conditional expression that +; may be considered as the basis for "conditional" speculation. (Only applies +; when SolveSpeculateLevel=2) +; The default value is 6. +; SolveSpeculateMaxCondWidth = 6 + +; Specify the maximum number of attempts to solve a speculative set of random +; variables and constraints. Exceeding this limit will cause the solver to +; abandon the current speculative set. (Only applies when SolveSpeculateLevel +; is non-zero) +; The default value is 100. +; SolveSpeculateMaxIterations = 100 + +; Specifies whether to attempt speculation on solve-before constraints or +; distribution constraints first. A value of 0 specifies that solve-before +; constraints are attempted first as the basis for speculative randomization. +; A value of 1 specifies that distribution constraints are attempted first +; as the basis for speculative randomization. +; The default value is 0. +; SolveSpeculateDistFirst = 0 + +; If the non-speculative BDD solver fails to evaluate a constraint scenario +; (due to time/memory limits) then the solver can be instructed to automatically +; re-evaluate the constraint scenario with the ACT solver engine. Set +; SolveACTbeforeSpeculate to 1 to enable this feature. +; The default value is 0 (do not re-evaluate with the ACT solver). +; SolveACTbeforeSpeculate = 0 + +; Use SolveFlags to specify options that will guide the behavior of the +; constraint solver. These options may improve the performance of the +; constraint solver for some testcases, and decrease the performance of the +; constraint solver for others. +; Valid flags are: +; i = disable bit interleaving for >, >=, <, <= constraints (BDD engine) +; n = disable bit interleaving for all constraints (BDD engine) +; r = reverse bit interleaving (BDD engine) +; The default value is "" (no options). +; SolveFlags = + +; Specify random sequence compatiblity with a prior letter release. This +; option is used to get the same random sequences during simulation as +; as a prior letter release. Only prior letter releases (of the current +; number release) are allowed. +; NOTE: Only those random sequence changes due to solver optimizations are +; reverted by this variable. Random sequence changes due to solver bugfixes +; cannot be un-done. +; NOTE: This variable can be overridden with the vsim "-solverev" command +; line switch. +; Default value set to "" (no compatibility). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +MvcHome = $MODEL_TECH/.. + +; Initialize SystemVerilog enums using the base type's default value +; instead of the leftmost value. +; EnumBaseInit = 1 + +; Suppress file type registration. +; SuppressFileTypeReg = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. Valid extensions are "feci", +; "pae", "uslt" and "spsl". +; SVExtensions = uslt,spsl + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; suppress can be used to achieve +nowarn functionality +; The format is: suppress = ,,[,,...] +; Examples: +suppress = 8780 ;an explanation can be had by running: verror 8780 +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; suppress = 3009,CNNODP,3043,TFMPC +; suppress = 8683,8684 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear only in the transcript. The other settings +; are to send messages to the wlf file only (messages that are +; recorded in the wlf file can be viewed in the MsgViewer) or to both +; the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; msgmode = tran +[Project] +; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 10 +Project_File_0 = /d/jspc22/trb/git/trbnet/trb_net_components.vhd +Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1406911647 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_1 = /d/jspc22/trb/git/trb3/ADC/sim/dummyADC.vhd +Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1409147194 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_2 = /d/jspc22/trb/git/trb3/ADC/sim/tb_adcprocessor.vhd +Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1409926749 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_3 = /d/jspc22/trb/git/trbnet/trb_net_std.vhd +Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1408718845 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_4 = /d/jspc22/trb/git/trb3/ADC/sim/txt_util.vhd +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1409066711 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_5 = /d/jspc22/trb/git/trb3/ADC/config.vhd +Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1408362979 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_6 = /d/jspc22/trb/git/trb3/ADC/version.vhd +Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} 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/d/jspc22/trb/git/trb3/ADC/source/adc_processor.vhd +Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1409926897 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_9 = /d/jspc22/trb/git/trb3/base/trb3_components.vhd +Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1407152059 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 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+100_100_100_100 +100_100_100_100 +100_100_100_100 +100_100_100_100 +100_100_100_100 +100_100_100_100 +100_100_100_100 +100_100_100_100 +100_100_100_100 +100_100_100_100 \ No newline at end of file diff --git a/ADC/sim/dummyADC.vhd b/ADC/sim/dummyADC.vhd new file mode 100644 index 0000000..91505e6 --- /dev/null +++ b/ADC/sim/dummyADC.vhd @@ -0,0 +1,79 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_textio.all; +USE ieee.math_real.ALL; +use ieee.numeric_std.all; + +library std; +use std.textio.all; + +library work; +use work.txt_util.all; + +entity dummyADC is + generic( + stim_file: string :="adcsim.dat" + ); + port( + CLK : in std_logic; + DATA : out std_logic_vector(39 downto 0) := (others => '0'); + VALID : out std_logic + ); +end entity; + + + +architecture dummyADC_arch of dummyADC is + +constant randrange : real := 20.0; + +begin +receive_data: process +variable seed1, seed2 : positive; +variable rand : real; +variable random1, random2, random3, random4 : unsigned(9 downto 0); +variable l : line; +variable s : std_logic_vector(47 downto 0); +variable toggle : std_logic := '0'; +variable s1, s2, s3, s4 : std_logic_vector(9 downto 0); + file stimulus: TEXT; +begin + + file_open(stimulus, stim_file, read_mode); + while not endfile(stimulus) loop + readline(stimulus, l); + hread(l, s); + + UNIFORM(seed1, seed2, rand); + random1 := to_unsigned(INTEGER(TRUNC(rand*randrange*2.0)),10); + UNIFORM(seed1, seed2, rand); + random2 := to_unsigned(INTEGER(TRUNC(rand*randrange*2.0)),10); + UNIFORM(seed1, seed2, rand); + random3 := to_unsigned(INTEGER(TRUNC(rand*randrange*2.0)),10); + UNIFORM(seed1, seed2, rand); + random4 := to_unsigned(INTEGER(TRUNC(rand*randrange*2.0)),10); + + + s1 := std_logic_vector(unsigned(s( 9 downto 0))+random1-to_unsigned(integer(randrange),10)); + s2 := std_logic_vector(unsigned(s(21 downto 12))+random2-to_unsigned(integer(randrange),10)); + s3 := std_logic_vector(unsigned(s(33 downto 24))+random3-to_unsigned(integer(randrange),10)); + s4 := std_logic_vector(unsigned(s(45 downto 36))+random4-to_unsigned(integer(randrange),10)); + + + DATA <= s4 & s3 & s2 & s1; + VALID <= '1'; + wait until CLK = '1'; wait for 0.5 ns; + VALID <= '0'; + wait until CLK = '1'; wait for 0.5 ns; + if toggle = '0' then + wait until CLK = '1'; wait for 0.5 ns; + toggle := '1'; + else + toggle := '0'; + end if; + + end loop; + file_close(stimulus); + + end process receive_data; +end architecture; \ No newline at end of file diff --git a/ADC/sim/tb_adcprocessor.vhd b/ADC/sim/tb_adcprocessor.vhd new file mode 100644 index 0000000..afa00f3 --- /dev/null +++ b/ADC/sim/tb_adcprocessor.vhd @@ -0,0 +1,163 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb3_components.all; +use work.adc_package.all; + +entity tb is +end entity; + + +architecture tb_arch of tb is + +component dummyADC is + generic( + stim_file: string :="adcsim.dat" + ); + port( + CLK : in std_logic; + DATA : out std_logic_vector(39 downto 0); + VALID : out std_logic + ); +end component; + +component adc_processor is + generic( + DEVICE : integer range 0 to 15 := 15 + ); + port( + CLK : in std_logic; + + ADC_DATA : in std_logic_vector(RESOLUTION*CHANNELS-1 downto 0); + ADC_VALID : in std_logic; + STOP_IN : in std_logic; + TRIGGER_OUT: out std_logic; + + CONTROL : in std_logic_vector(63 downto 0); + CONFIG : in cfg_t; + + DEBUG_BUFFER_READ : in std_logic; + DEBUG_BUFFER_ADDR : in std_logic_vector(4 downto 0); + DEBUG_BUFFER_DATA : out std_logic_vector(31 downto 0); + DEBUG_BUFFER_READY: out std_logic; + + READOUT_RX : in READOUT_RX; + READOUT_TX : out READOUT_TX + + ); +end component; + +signal clock : std_logic := '1'; +signal adc_data : std_logic_vector(39 downto 0) := (others => '0'); +signal adc_valid : std_logic := '0'; +signal stop_in : std_logic := '0'; +signal trigger_out: std_logic := '0'; +signal config : cfg_t; +signal readout_rx : READOUT_RX; +signal readout_tx : READOUT_TX; +signal control : std_logic_vector(63 downto 0); + +begin + +clock <= not clock after 5 ns; + +config.buffer_depth <= to_unsigned(100 ,11); +config.samples_after <= to_unsigned(20 ,11); +config.block_count <= to_unsigned(1 , 2); +config.trigger_threshold <= to_unsigned(70 ,18); +config.readout_threshold <= to_unsigned(70 ,18); +config.presum <= to_unsigned(0 , 8); +config.averaging <= to_unsigned(5 , 4); +config.block_avg(0) <= to_unsigned(0 , 8); +config.block_avg(1) <= to_unsigned(0 , 8); +config.block_avg(2) <= to_unsigned(0 , 8); +config.block_avg(3) <= to_unsigned(0 , 8); +config.block_sums(0) <= to_unsigned(2 , 8); +config.block_sums(1) <= to_unsigned(2 , 8); +config.block_sums(2) <= to_unsigned(2 , 8); +config.block_sums(3) <= to_unsigned(2 , 8); +config.block_scale(0) <= to_unsigned(0 , 8); +config.block_scale(1) <= to_unsigned(0 , 8); +config.block_scale(2) <= to_unsigned(0 , 8); +config.block_scale(3) <= to_unsigned(0 , 8); +config.baseline_reset_value <= to_unsigned(1023*32, 32); + +config.trigger_enable <= x"0000_0000_0000", x"ffff_ffff_fff1" after 5 us; +config.baseline_always_on <= '0'; --'1', '0' after 10 us; + + +readout_rx.valid_notiming_trg <= '0'; +readout_rx.invalid_trg <= '0'; +readout_rx.trg_type <= (others => '0'); +readout_rx.trg_number <= (others => '0'); +readout_rx.trg_code <= (others => '0'); +readout_rx.trg_information <= (others => '0'); +readout_rx.trg_int_number <= (others => '0'); +readout_rx.trg_multiple <= '0'; +readout_rx.trg_timeout <= '0'; +readout_rx.trg_spurious <= '0'; +readout_rx.trg_missing <= '0'; +readout_rx.trg_spike <= '0'; +readout_rx.buffer_almost_full <= '0'; + +control <= (others => '0'), (8 => '1',others => '0') after 1us, (others => '0') after 1.01 us,(5 => '1',others => '0') after 5us, (others => '0') after 5.01 us ; + +proc_rdo : process begin + readout_rx.data_valid <= '0'; + readout_rx.valid_timing_trg <= '0'; + wait for 15 us; wait until rising_edge(clock); wait for 0.5 ns; + readout_rx.valid_timing_trg <= '1'; + wait until rising_edge(clock); wait for 0.5 ns; + readout_rx.valid_timing_trg <= '0'; + wait for 300 ns; wait until rising_edge(clock); wait for 0.5 ns; + readout_rx.data_valid <= '1'; + wait until readout_tx.busy_release = '1'; + wait for 10 ns; wait until rising_edge(clock); wait for 0.5 ns; + readout_rx.data_valid <= '0'; +end process; + +THE_ADC : dummyADC + port map( + CLK => clock, + DATA => adc_data, + VALID => adc_valid + ); + +UUT: adc_processor + generic map( + DEVICE => 0 + ) + port map( + CLK => clock, + ADC_DATA => adc_data, + ADC_VALID => adc_valid, + STOP_IN => stop_in, + TRIGGER_OUT=> trigger_out, + + CONTROL => control, + CONFIG => config, + + DEBUG_BUFFER_READ => '0', + DEBUG_BUFFER_ADDR => (others => '0'), + DEBUG_BUFFER_DATA => open, + DEBUG_BUFFER_READY=> open, + + READOUT_TX => readout_tx, + READOUT_RX => readout_rx + ); + + +PROC_ADC : process begin + wait until rising_edge(clock); wait for 0.5 ns; + +end process; + + + + + + +end architecture; \ No newline at end of file diff --git a/ADC/sim/txt_util.vhd b/ADC/sim/txt_util.vhd new file mode 100644 index 0000000..d42303b --- /dev/null +++ b/ADC/sim/txt_util.vhd @@ -0,0 +1,586 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + diff --git a/ADC/sim/wave.do b/ADC/sim/wave.do new file mode 100644 index 0000000..1ac341d --- /dev/null +++ b/ADC/sim/wave.do @@ -0,0 +1,58 @@ +onerror {resume} +quietly virtual signal -install /tb { /tb/adc_data(9 downto 0)} adc_data_0 +quietly virtual signal -install /tb { /tb/adc_data(19 downto 10)} adc_data_1 +quietly virtual signal -install /tb { /tb/adc_data(29 downto 20)} adc_data_2 +quietly virtual signal -install /tb { /tb/adc_data(39 downto 30)} adc_data_3 +quietly WaveActivateNextPane {} 0 +add wave -noupdate -radix hexadecimal /tb/clock +add wave -noupdate -format Analog-Step -height 84 -max 1023.0 -radix hexadecimal -childformat {{/tb/adc_data_0(9) -radix hexadecimal} {/tb/adc_data_0(8) -radix hexadecimal} {/tb/adc_data_0(7) -radix hexadecimal} {/tb/adc_data_0(6) -radix hexadecimal} {/tb/adc_data_0(5) -radix hexadecimal} {/tb/adc_data_0(4) -radix hexadecimal} {/tb/adc_data_0(3) -radix hexadecimal} {/tb/adc_data_0(2) -radix hexadecimal} {/tb/adc_data_0(1) -radix hexadecimal} {/tb/adc_data_0(0) -radix hexadecimal}} -subitemconfig {/tb/adc_data(9) {-radix hexadecimal} /tb/adc_data(8) {-radix hexadecimal} /tb/adc_data(7) {-radix hexadecimal} /tb/adc_data(6) {-radix hexadecimal} /tb/adc_data(5) {-radix hexadecimal} /tb/adc_data(4) {-radix hexadecimal} /tb/adc_data(3) {-radix hexadecimal} /tb/adc_data(2) {-radix hexadecimal} /tb/adc_data(1) {-radix hexadecimal} /tb/adc_data(0) {-radix hexadecimal}} /tb/adc_data_0 +add wave -noupdate -clampanalog 1 -format Analog-Step -height 80 -max 1024.0 -radix hexadecimal -childformat {{/tb/adc_data_1(19) -radix hexadecimal} {/tb/adc_data_1(18) -radix hexadecimal} {/tb/adc_data_1(17) -radix hexadecimal} {/tb/adc_data_1(16) -radix hexadecimal} {/tb/adc_data_1(15) -radix hexadecimal} {/tb/adc_data_1(14) -radix hexadecimal} {/tb/adc_data_1(13) -radix hexadecimal} {/tb/adc_data_1(12) -radix hexadecimal} {/tb/adc_data_1(11) -radix hexadecimal} {/tb/adc_data_1(10) -radix hexadecimal}} -subitemconfig {/tb/adc_data(19) {-radix hexadecimal} /tb/adc_data(18) {-radix hexadecimal} /tb/adc_data(17) {-radix hexadecimal} /tb/adc_data(16) {-radix hexadecimal} /tb/adc_data(15) {-radix hexadecimal} /tb/adc_data(14) {-radix hexadecimal} /tb/adc_data(13) {-radix hexadecimal} /tb/adc_data(12) {-radix hexadecimal} /tb/adc_data(11) {-radix hexadecimal} /tb/adc_data(10) {-radix hexadecimal}} /tb/adc_data_1 +add wave -noupdate -clampanalog 1 -format Analog-Step -height 80 -max 1024.0 -radix hexadecimal /tb/adc_data_2 +add wave -noupdate -clampanalog 1 -format Analog-Step -height 80 -max 1024.0 -radix hexadecimal /tb/adc_data_3 +add wave -noupdate -radix hexadecimal /tb/adc_valid +add wave -noupdate -divider {Buffer Input} +add wave -noupdate -radix hexadecimal /tb/UUT/ram_data_in +add wave -noupdate -radix hexadecimal /tb/UUT/ram_write +add wave -noupdate -radix hexadecimal /tb/UUT/stop_writing +add wave -noupdate -divider Buffers +add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/ram_wr_pointer(9) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(8) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(7) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(6) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(5) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(4) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(3) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(2) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(1) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(0) -radix hexadecimal}} -subitemconfig {/tb/UUT/ram_wr_pointer(9) {-height 16 -radix hexadecimal} /tb/UUT/ram_wr_pointer(8) {-height 16 -radix hexadecimal} /tb/UUT/ram_wr_pointer(7) {-height 16 -radix hexadecimal} /tb/UUT/ram_wr_pointer(6) {-height 16 -radix hexadecimal} /tb/UUT/ram_wr_pointer(5) {-height 16 -radix hexadecimal} /tb/UUT/ram_wr_pointer(4) {-height 16 -radix hexadecimal} /tb/UUT/ram_wr_pointer(3) {-height 16 -radix hexadecimal} /tb/UUT/ram_wr_pointer(2) {-height 16 -radix hexadecimal} /tb/UUT/ram_wr_pointer(1) {-height 16 -radix hexadecimal} /tb/UUT/ram_wr_pointer(0) {-height 16 -radix hexadecimal}} /tb/UUT/ram_wr_pointer +add wave -noupdate -radix hexadecimal /tb/UUT/ram_rd_pointer(0) +add wave -noupdate -radix hexadecimal /tb/UUT/ram_count(0) +add wave -noupdate -divider Reader +add wave -noupdate -radix hexadecimal /tb/UUT/ram_remove +add wave -noupdate -radix hexadecimal /tb/UUT/reg2_ram_remove +add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/ram_data_out(0)(17) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(16) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(15) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(14) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(13) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(12) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(11) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(10) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(9) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(8) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(7) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(6) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(5) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(4) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(3) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(2) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(1) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(0) -radix hexadecimal}} -subitemconfig {/tb/UUT/ram_data_out(0)(17) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(16) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(15) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(14) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(13) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(12) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(11) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(10) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(9) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(8) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(7) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(6) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(5) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(4) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(3) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(2) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(1) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(0) {-height 16 -radix hexadecimal}} /tb/UUT/ram_data_out(0) +add wave -noupdate -divider Baseline +add wave -noupdate -format Analog-Step -height 80 -max 1024.0 -radix hexadecimal /tb/UUT/baseline(0) +add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/baseline(0) -radix hexadecimal} {/tb/UUT/baseline(1) -radix hexadecimal} {/tb/UUT/baseline(2) -radix hexadecimal} {/tb/UUT/baseline(3) -radix hexadecimal}} -subitemconfig {/tb/UUT/baseline(0) {-height 16 -radix hexadecimal} /tb/UUT/baseline(1) {-height 16 -radix hexadecimal} /tb/UUT/baseline(2) {-height 16 -radix hexadecimal} /tb/UUT/baseline(3) {-height 16 -radix hexadecimal}} /tb/UUT/baseline +add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/baseline_averages(0) -radix hexadecimal} {/tb/UUT/baseline_averages(1) -radix hexadecimal} {/tb/UUT/baseline_averages(2) -radix hexadecimal} {/tb/UUT/baseline_averages(3) -radix hexadecimal}} -subitemconfig {/tb/UUT/baseline_averages(0) {-height 16 -radix hexadecimal} /tb/UUT/baseline_averages(1) {-height 16 -radix hexadecimal} /tb/UUT/baseline_averages(2) {-height 16 -radix hexadecimal} /tb/UUT/baseline_averages(3) {-height 16 -radix hexadecimal}} /tb/UUT/baseline_averages +add wave -noupdate -expand /tb/UUT/readout_flag +add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/thresh_counter(3) -radix hexadecimal} {/tb/UUT/thresh_counter(2) -radix hexadecimal} {/tb/UUT/thresh_counter(1) -radix hexadecimal} {/tb/UUT/thresh_counter(0) -radix hexadecimal}} -expand -subitemconfig {/tb/UUT/thresh_counter(3) {-height 16 -radix hexadecimal} /tb/UUT/thresh_counter(2) {-height 16 -radix hexadecimal} /tb/UUT/thresh_counter(1) {-height 16 -radix hexadecimal} /tb/UUT/thresh_counter(0) {-height 16 -radix hexadecimal}} /tb/UUT/thresh_counter +add wave -noupdate -divider Readout +add wave -noupdate /tb/UUT/READOUT_RX.data_valid +add wave -noupdate /tb/UUT/READOUT_RX.valid_timing_trg +add wave -noupdate /tb/UUT/state +add wave -noupdate /tb/UUT/stop_writing_rdo +add wave -noupdate -radix hexadecimal /tb/UUT/after_trg_cnt +add wave -noupdate -divider Config +add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/CONFIG.buffer_depth -radix hexadecimal} {/tb/UUT/CONFIG.samples_after -radix hexadecimal} {/tb/UUT/CONFIG.block_count -radix hexadecimal} {/tb/UUT/CONFIG.trigger_threshold -radix hexadecimal} {/tb/UUT/CONFIG.readout_threshold -radix hexadecimal} {/tb/UUT/CONFIG.presum -radix hexadecimal} {/tb/UUT/CONFIG.averaging -radix hexadecimal} {/tb/UUT/CONFIG.trigger_enable -radix hexadecimal} {/tb/UUT/CONFIG.baseline_always_on -radix hexadecimal} {/tb/UUT/CONFIG.baseline_reset_value -radix hexadecimal} {/tb/UUT/CONFIG.block_avg -radix hexadecimal} {/tb/UUT/CONFIG.block_sums -radix hexadecimal} {/tb/UUT/CONFIG.block_scale -radix hexadecimal}} -subitemconfig {/tb/UUT/CONFIG.buffer_depth {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.samples_after {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.block_count {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.trigger_threshold {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.readout_threshold {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.presum {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.averaging {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.trigger_enable {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.baseline_always_on {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.baseline_reset_value {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.block_avg {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.block_sums {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.block_scale {-height 16 -radix hexadecimal}} /tb/UUT/CONFIG +add wave -noupdate /tb/UUT/TRIGGER_OUT +add wave -noupdate -expand /tb/UUT/trigger_gen +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {15136 ns} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {14644 ns} {15626 ns} diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd index b932a47..9fb3678 100644 --- a/ADC/source/adc_ad9219.vhd +++ b/ADC/source/adc_ad9219.vhd @@ -23,7 +23,7 @@ entity adc_ad9219 is DATA_OUT : out std_logic_vector(NUM_DEVICES*CHANNELS*RESOLUTION-1 downto 0); FCO_OUT : out std_logic_vector(NUM_DEVICES*RESOLUTION-1 downto 0); DATA_VALID_OUT : out std_logic_vector(NUM_DEVICES-1 downto 0); - DEBUG : out std_logic_vector(NUM_DEVICES*CHANNELS*32-1 downto 0) + DEBUG : out std_logic_vector(NUM_DEVICES*32-1 downto 0) ); end entity; @@ -39,7 +39,8 @@ signal clk_data : std_logic; --100MHz signal clk_data_half : std_logic; signal restart_i : std_logic; - +type cnt_t is array(0 to NUM_DEVICES-1) of unsigned(27 downto 0); +signal counter : cnt_t; type state_t is (S1,S2,S3,S4,S5); type states_t is array(0 to NUM_DEVICES-1) of state_t; @@ -212,7 +213,7 @@ gen_chips : for i in 0 to NUM_DEVICES-1 generate end if; end process; - THE_FIFO : entity work.fifo_cdt_200_50 --60*16 + THE_FIFO : entity work.fifo_cdt_200_50 --50*16 port map( Data(9 downto 0) => fifo_input(i)(0), Data(19 downto 10) => fifo_input(i)(1), @@ -238,24 +239,23 @@ gen_chips : for i in 0 to NUM_DEVICES-1 generate DATA_OUT(i*40+39 downto i*40+0) <= fifo_output(i)(39 downto 0); FCO_OUT (i*10+9 downto i*10+0) <= fifo_output(i)(49 downto 40); DATA_VALID_OUT(i) <= '1'; + counter(i) <= counter(i) + 1; else DATA_VALID_OUT(i) <= '0'; end if; end process; - + proc_debug : process begin wait until rising_edge(CLK); - DEBUG(i*32+31 downto i*32) <= (others => '0'); - DEBUG(i*32+3 downto i*32+0) <= q_q(i)(3 downto 0); - DEBUG(i*32+7 downto i*32+4) <= q_q(i)(19 downto 16); + DEBUG(i*32+31 downto i*32+4) <= counter(i); case state_q(i) is - when S1 => DEBUG(i*32+11 downto i*32+8) <= x"1"; - when S2 => DEBUG(i*32+11 downto i*32+8) <= x"2"; - when S3 => DEBUG(i*32+11 downto i*32+8) <= x"3"; - when S4 => DEBUG(i*32+11 downto i*32+8) <= x"4"; - when S5 => DEBUG(i*32+11 downto i*32+8) <= x"5"; - when others => DEBUG(i*32+11 downto i*32+8) <= x"0"; + when S1 => DEBUG(i*32+3 downto i*32+0) <= x"1"; + when S2 => DEBUG(i*32+3 downto i*32+0) <= x"2"; + when S3 => DEBUG(i*32+3 downto i*32+0) <= x"3"; + when S4 => DEBUG(i*32+3 downto i*32+0) <= x"4"; + when S5 => DEBUG(i*32+3 downto i*32+0) <= x"5"; + when others => DEBUG(i*32+3 downto i*32+0) <= x"f"; end case; end process; diff --git a/ADC/source/adc_handler.vhd b/ADC/source/adc_handler.vhd index a74eaeb..2d42523 100644 --- a/ADC/source/adc_handler.vhd +++ b/ADC/source/adc_handler.vhd @@ -31,32 +31,45 @@ entity adc_handler is end entity; architecture adc_handler_arch of adc_handler is +attribute syn_keep : boolean; +attribute syn_preserve : boolean; + signal adc_data_out : std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0); signal adc_fco_out : std_logic_vector(DEVICES*RESOLUTION-1 downto 0); signal adc_valid_out : std_logic_vector(DEVICES-1 downto 0); -signal adc_debug : std_logic_vector(DEVICES*CHANNELS*32-1 downto 0); +signal adc_debug : std_logic_vector(DEVICES*32-1 downto 0); signal buffer_empty : std_logic; signal buffer_stop_override : std_logic; signal ctrl_reg : std_logic_vector(31 downto 0); +signal strobe_reg : std_logic_vector(31 downto 0); +attribute syn_keep of ctrl_reg : signal is true; +attribute syn_preserve of ctrl_reg : signal is true; +attribute syn_keep of strobe_reg : signal is true; +attribute syn_preserve of strobe_reg : signal is true; + +signal buffer_ctrl_reg : std_logic_vector(31 downto 0); signal adc_restart : std_logic; signal adc_trigger : std_logic_vector(DEVICES-1 downto 0); signal adc_stop : std_logic; signal config : cfg_t; -signal strobe_reg : std_logic_vector(31 downto 0); -signal buffer_addr : std_logic_vector(3 downto 0); +signal buffer_addr : std_logic_vector(4 downto 0); signal buffer_data : buffer_data_t; signal buffer_read : std_logic_vector(15 downto 0); signal buffer_ready : std_logic_vector(DEVICES-1 downto 0); signal buffer_device : integer range 0 to DEVICES-1; +type arr_4_32_t is array (0 to 3) of unsigned(31 downto 0); +signal baseline_reset_value : arr_4_32_t := (others => (others => '0')); -- 000 - 0ff configuration -- 000 reset, buffer clear strobes +-- 001 buffer control reg +-- 002 - 003 trigger generation channel enable -- 010 buffer depth (1-1023) -- 011 number of samples after trigger arrived (0-1023 * 25ns) -- 012 number of blocks to process (1-4) @@ -68,6 +81,7 @@ signal buffer_device : integer range 0 to DEVICES-1; -- 024 - 027 number of sums (1-255) -- 028 - 02b 2^k scaling factor (0-8) -- 02c - 02f +-- 080 ADC control: SPI, power -- 100 - 1ff status -- 100 clock valid (1 bit per ADC) -- 101 fco valid (1 bit per ADC) @@ -75,6 +89,7 @@ signal buffer_device : integer range 0 to DEVICES-1; -- 800 - 83f last ADC values (local 0x0 - 0x3) -- 840 - 87f long-term average / baseline (local 0x4 - 0x7) -- 880 - 8bf fifo access (debugging only) (local 0x8 - 0xb) +-- 900 - 9ff processor registers (local 0x10 - 0x1f) begin @@ -113,10 +128,10 @@ THE_ADC_LEFT : entity work.adc_ad9219 DATA_VALID_OUT(5 downto 0) => adc_valid_out(5 downto 0), DATA_VALID_OUT(6) => adc_valid_out(7), - DEBUG(32*6*CHANNELS-1 downto 0) - => adc_debug(32*6*CHANNELS-1 downto 0), - DEBUG(32*7*CHANNELS -1 downto 32*6*CHANNELS) - => adc_debug(32*8*CHANNELS-1 downto 32*7*CHANNELS) + DEBUG(32*6-1 downto 0) + => adc_debug(32*6-1 downto 0), + DEBUG(32*7 -1 downto 32*6) + => adc_debug(32*8-1 downto 32*7) ); @@ -150,10 +165,10 @@ THE_ADC_RIGHT : entity work.adc_ad9219 DATA_VALID_OUT(0) => adc_valid_out(6), DATA_VALID_OUT(4 downto 1) => adc_valid_out(11 downto 8), - DEBUG(32*1*CHANNELS-1 downto 0) - => adc_debug(32*7*CHANNELS-1 downto 32*6*CHANNELS), - DEBUG(32*5*CHANNELS -1 downto 32*1*CHANNELS) - => adc_debug(32*12*CHANNELS-1 downto 32*8*CHANNELS) + DEBUG(32*1-1 downto 0) + => adc_debug(32*7-1 downto 32*6), + DEBUG(32*5 -1 downto 32*1) + => adc_debug(32*12-1 downto 32*8) ); @@ -172,6 +187,8 @@ gen_processors : for i in 0 to DEVICES-1 generate STOP_IN => adc_stop, TRIGGER_OUT => adc_trigger(i), + CONTROL(31 downto 0) => strobe_reg, + CONTROL(63 downto 32) => buffer_ctrl_reg, CONFIG => config, --trigger offset, zero sup offset, depth, DEBUG_BUFFER_ADDR => buffer_addr, @@ -186,8 +203,11 @@ gen_processors : for i in 0 to DEVICES-1 generate end generate; TRIGGER_FLAG_OUT <= or_all(adc_trigger); +ADCSPI_CTRL <= ctrl_reg(7 downto 0); +adc_stop <= buffer_ctrl_reg(0); +config.baseline_always_on <= buffer_ctrl_reg(4); PROC_BUS : process begin wait until rising_edge(CLK); @@ -195,70 +215,118 @@ PROC_BUS : process begin BUS_TX.nack <= '0'; BUS_TX.unknown <= '0'; buffer_read <= (others => '0'); - + strobe_reg <= (others => '0'); if or_all(buffer_ready) = '1' then BUS_TX.data <= buffer_data(buffer_device); BUS_TX.ack <= '1'; elsif BUS_RX.read = '1' then - if BUS_RX.addr = x"0000" then - strobe_reg <= BUS_TX.data; + if BUS_RX.addr <= x"000f" then + BUS_TX.ack <= '1'; + case BUS_RX.addr(3 downto 0) is + when x"1" => BUS_TX.data <= buffer_ctrl_reg; + when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; + end case; + elsif BUS_RX.addr = x"0080" then + BUS_TX.data <= ctrl_reg; + BUS_TX.ack <= '1'; elsif BUS_RX.addr >= x"0010" and BUS_RX.addr <= x"001f" then --basic config registers BUS_TX.ack <= '1'; BUS_TX.data <= (others => '0'); case BUS_RX.addr(7 downto 0) is - when x"10" => BUS_TX.data(10 downto 0) <= config.buffer_depth; - when x"11" => BUS_TX.data(10 downto 0) <= config.samples_after; - when x"12" => BUS_TX.data( 1 downto 0) <= config.block_count; - when x"13" => BUS_TX.data(17 downto 0) <= config.trigger_threshold; - when x"14" => BUS_TX.data(17 downto 0) <= config.readout_threshold; - when x"15" => BUS_TX.data( 7 downto 0) <= config.presum; - when x"16" => BUS_TX.data( 3 downto 0) <= config.averaging; + when x"10" => BUS_TX.data(10 downto 0) <= std_logic_vector(config.buffer_depth); + when x"11" => BUS_TX.data(10 downto 0) <= std_logic_vector(config.samples_after); + when x"12" => BUS_TX.data( 1 downto 0) <= std_logic_vector(config.block_count); + when x"13" => BUS_TX.data(17 downto 0) <= std_logic_vector(config.trigger_threshold); + when x"14" => BUS_TX.data(17 downto 0) <= std_logic_vector(config.readout_threshold); + when x"15" => BUS_TX.data( 7 downto 0) <= std_logic_vector(config.presum); + when x"16" => BUS_TX.data( 3 downto 0) <= std_logic_vector(config.averaging); + when x"17" => BUS_TX.data(31 downto 0) <= config.trigger_enable(31 downto 0); + when x"18" => BUS_TX.data(15 downto 0) <= config.trigger_enable(47 downto 32); when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end case; elsif BUS_RX.addr >= x"0020" and BUS_RX.addr <= x"002f" then BUS_TX.ack <= '1'; BUS_TX.data <= (others => '0'); case BUS_RX.addr(3 downto 2) is - when "00" => BUS_TX.data( 7 downto 0) <= config.block_avg(to_integer(unsigned(BUS_RX.addr(1 downto 0)))); - when "01" => BUS_TX.data( 7 downto 0) <= config.block_sums(to_integer(unsigned(BUS_RX.addr(1 downto 0)))); - when "10" => BUS_TX.data( 7 downto 0) <= config.block_scale(to_integer(unsigned(BUS_RX.addr(1 downto 0)))); + when "00" => BUS_TX.data( 7 downto 0) <= std_logic_vector(config.block_avg(to_integer(unsigned(BUS_RX.addr(1 downto 0))))); + when "01" => BUS_TX.data( 7 downto 0) <= std_logic_vector(config.block_sums(to_integer(unsigned(BUS_RX.addr(1 downto 0))))); + when "10" => BUS_TX.data( 7 downto 0) <= std_logic_vector(config.block_scale(to_integer(unsigned(BUS_RX.addr(1 downto 0))))); when "11" => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end case; + elsif BUS_RX.addr >= x"0030" and BUS_RX.addr <= x"003b" then + BUS_TX.ack <= '1'; + BUS_TX.data <= adc_debug(to_integer(unsigned(BUS_RX.addr(3 downto 0)))*32+31 downto to_integer(unsigned(BUS_RX.addr(3 downto 0)))*32); + elsif BUS_RX.addr >= x"0800" and BUS_RX.addr <= x"08bf" and BUS_RX.addr(5 downto 0) < std_logic_vector(to_unsigned(DEVICES*CHANNELS,6)) then buffer_device <= to_integer(unsigned(BUS_RX.addr(5 downto 2))); - buffer_addr <= BUS_RX.addr(7 downto 6) & BUS_RX.addr(1 downto 0); + buffer_addr <= '0' & BUS_RX.addr(7 downto 6) & BUS_RX.addr(1 downto 0); buffer_read(to_integer(unsigned(BUS_RX.addr(5 downto 2)))) <= '1'; + elsif BUS_RX.addr >= x"0900" and BUS_RX.addr <= x"09ff" then + if BUS_RX.addr(3 downto 0) < std_logic_vector(to_unsigned(DEVICES,4)) then + buffer_device <= to_integer(unsigned(BUS_RX.addr(3 downto 0))); + buffer_addr <= '1' & BUS_RX.addr(7 downto 4); + buffer_read(to_integer(unsigned(BUS_RX.addr(3 downto 0)))) <= '1'; + else + BUS_TX.data <= (others => '0'); + BUS_TX.ack <= '1'; + end if; else BUS_TX.unknown <= '1'; end if; + + elsif BUS_RX.write = '1' then - if BUS_RX.addr >= x"0010" and BUS_RX.addr <= x"0016" then --basic config registers + if BUS_RX.addr >= x"0010" and BUS_RX.addr <= x"001f" then --basic config registers BUS_TX.ack <= '1'; case BUS_RX.addr(7 downto 0) is - when x"10" => config.buffer_depth <= BUS_RX.data(10 downto 0); - when x"11" => config.samples_after <= BUS_RX.data(10 downto 0); - when x"12" => config.block_count <= BUS_RX.data( 1 downto 0); - when x"13" => config.trigger_threshold <= BUS_RX.data(17 downto 0); - when x"14" => config.readout_threshold <= BUS_RX.data(17 downto 0); - when x"15" => config.presum <= BUS_RX.data( 7 downto 0); - when x"16" => config.averaging <= BUS_RX.data( 3 downto 0); + when x"10" => config.buffer_depth <= unsigned(BUS_RX.data(10 downto 0)); + when x"11" => config.samples_after <= unsigned(BUS_RX.data(10 downto 0)); + when x"12" => config.block_count <= unsigned(BUS_RX.data( 1 downto 0)); + when x"13" => config.trigger_threshold <= unsigned(BUS_RX.data(17 downto 0)); + when x"14" => config.readout_threshold <= unsigned(BUS_RX.data(17 downto 0)); + when x"15" => config.presum <= unsigned(BUS_RX.data( 7 downto 0)); + when x"16" => config.averaging <= unsigned(BUS_RX.data( 3 downto 0)); + when x"17" => config.trigger_enable(31 downto 0) <= BUS_RX.data(31 downto 0); + when x"18" => config.trigger_enable(47 downto 32) <= BUS_RX.data(15 downto 0); + when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end case; elsif BUS_RX.addr >= x"0020" and BUS_RX.addr <= x"002f" then BUS_TX.ack <= '1'; BUS_TX.data <= (others => '0'); case BUS_RX.addr(3 downto 2) is - when "00" => config.block_avg(to_integer(unsigned(BUS_RX.addr(1 downto 0)))) <= BUS_RX.data( 7 downto 0); - when "01" => config.block_sums(to_integer(unsigned(BUS_RX.addr(1 downto 0)))) <= BUS_RX.data( 7 downto 0); - when "10" => config.block_scale(to_integer(unsigned(BUS_RX.addr(1 downto 0))))<= BUS_RX.data( 7 downto 0); + when "00" => config.block_avg(to_integer(unsigned(BUS_RX.addr(1 downto 0)))) <= unsigned(BUS_RX.data( 7 downto 0)); + when "01" => config.block_sums(to_integer(unsigned(BUS_RX.addr(1 downto 0)))) <= unsigned(BUS_RX.data( 7 downto 0)); + when "10" => config.block_scale(to_integer(unsigned(BUS_RX.addr(1 downto 0))))<= unsigned(BUS_RX.data( 7 downto 0)); when "11" => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end case; + elsif BUS_RX.addr <= x"000f" then + BUS_TX.ack <= '1'; + case BUS_RX.addr(3 downto 0) is + when x"0" => strobe_reg <= BUS_RX.data; + when x"1" => buffer_ctrl_reg <= BUS_RX.data; + when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; + end case; + elsif BUS_RX.addr = x"0080" then + ctrl_reg <= BUS_RX.data; + BUS_TX.ack <= '1'; else BUS_TX.unknown <= '1'; end if; end if; end process; - + +proc_baseline_reset_value : process begin + wait until rising_edge(CLK); + baseline_reset_value(3) <= (others => '0'); + baseline_reset_value(3)(to_integer(config.averaging)+RESOLUTION-1 downto to_integer(config.averaging)) <= (others => not config.trigger_threshold(16)); + baseline_reset_value(2) <= baseline_reset_value(3); + baseline_reset_value(1) <= baseline_reset_value(2)(23 downto 0) * resize(config.presum+1,8); + baseline_reset_value(0) <= baseline_reset_value(1); +end process; + config.baseline_reset_value <= baseline_reset_value(0); + + end architecture; @@ -279,33 +347,3 @@ end architecture; -- end record; -- -- --- type READOUT_RX is record --- data_valid : std_logic; --- valid_timing_trg : std_logic; --- valid_notiming_trg : std_logic; --- invalid_trg : std_logic; --- -- --- trg_type : std_logic_vector( 3 downto 0); --- trg_number : std_logic_vector(15 downto 0); --- trg_code : std_logic_vector( 7 downto 0); --- trg_information : std_logic_vector(23 downto 0); --- trg_int_number : std_logic_vector(15 downto 0); --- -- --- trg_multiple : std_logic; --- trg_timeout : std_logic; --- trg_spurious : std_logic; --- trg_missing : std_logic; --- trg_spike : std_logic; --- -- --- buffer_almost_full : std_logic; --- end record; --- --- --- type READOUT_TX is record --- busy_release : std_logic; --- statusbits : std_logic_vector(31 downto 0); --- data : std_logic_vector(31 downto 0); --- data_write : std_logic; --- data_finished : std_logic; --- end record; --- \ No newline at end of file diff --git a/ADC/source/adc_package.vhd b/ADC/source/adc_package.vhd index 2ba6ce1..bd97b17 100644 --- a/ADC/source/adc_package.vhd +++ b/ADC/source/adc_package.vhd @@ -14,22 +14,32 @@ constant CHANNELS : integer := 4; constant RESOLUTION : integer := 10; +type buffer_data_t is array(0 to DEVICES-1) of std_logic_vector(31 downto 0); + +type std_logic_vector_array_18 is array (integer range <>) of std_logic_vector(17 downto 0); +type std_logic_vector_array_10 is array (integer range <>) of std_logic_vector( 9 downto 0); + +type unsigned_array_18 is array (integer range <>) of unsigned(17 downto 0); +type unsigned_array_10 is array (integer range <>) of unsigned( 9 downto 0); +type unsigned_array_8 is array (integer range <>) of unsigned( 7 downto 0); + type cfg_t is record - buffer_depth : std_logic_vector(10 downto 0); - samples_after : std_logic_vector(10 downto 0); - block_count : std_logic_vector( 1 downto 0); - trigger_threshold : std_logic_vector(17 downto 0); - readout_threshold : std_logic_vector(17 downto 0); - presum : std_logic_vector( 7 downto 0); - averaging : std_logic_vector( 3 downto 0); - block_avg : std_logic_vector_array_8(0 to 3); - block_sums : std_logic_vector_array_8(0 to 3); - block_scale : std_logic_vector_array_8(0 to 3); + buffer_depth : unsigned(10 downto 0); + samples_after : unsigned(10 downto 0); + block_count : unsigned( 1 downto 0); + trigger_threshold : unsigned(17 downto 0); + readout_threshold : unsigned(17 downto 0); + presum : unsigned( 7 downto 0); + averaging : unsigned( 3 downto 0); + trigger_enable : std_logic_vector(47 downto 0); + baseline_always_on: std_logic; + baseline_reset_value : unsigned(31 downto 0); + block_avg : unsigned_array_8(0 to 3); + block_sums : unsigned_array_8(0 to 3); + block_scale : unsigned_array_8(0 to 3); end record; -type buffer_data_t is array(0 to DEVICES-1) of std_logic_vector(31 downto 0); - end package; diff --git a/ADC/source/adc_processor.vhd b/ADC/source/adc_processor.vhd index e0c9040..1a6abb9 100644 --- a/ADC/source/adc_processor.vhd +++ b/ADC/source/adc_processor.vhd @@ -19,10 +19,11 @@ entity adc_processor is STOP_IN : in std_logic; TRIGGER_OUT: out std_logic; + CONTROL : in std_logic_vector(63 downto 0); CONFIG : in cfg_t; DEBUG_BUFFER_READ : in std_logic; - DEBUG_BUFFER_ADDR : in std_logic_vector(3 downto 0); + DEBUG_BUFFER_ADDR : in std_logic_vector(4 downto 0); DEBUG_BUFFER_DATA : out std_logic_vector(31 downto 0); DEBUG_BUFFER_READY: out std_logic; @@ -34,15 +35,62 @@ end entity; architecture adc_processor_arch of adc_processor is +attribute syn_hier : string; +attribute syn_ramstyle : string; +attribute syn_keep : boolean; +attribute syn_preserve : boolean; -type ram_t is array(0 to 1023) of std_logic_vector(17 downto 0); -type ram_arr_t is array(0 to 3) of ram_t; +attribute syn_hier of adc_processor_arch : architecture is "flatten, firm"; -signal ram : ram_arr_t; +type ram_t is array (0 to 1023) of unsigned(17 downto 0); +type ram_arr_t is array (0 to 3) of ram_t; +type arr_values_t is array (0 to CHANNELS-1) of unsigned(15 downto 0); +type arr_CHAN_RES_t is array (0 to CHANNELS-1) of unsigned(31 downto 0); -type arr_CHAN_RES_t is array(0 to CHANNELS-1) of std_logic_vector(23 downto 0); -signal baseline_averages : arr_CHAN_RES_t; +signal ram : ram_arr_t := (others => (others => (others => '0'))); +attribute syn_ramstyle of ram : signal is "block_ram"; +signal ram_wr_pointer : unsigned(9 downto 0) := (others => '0'); +signal ram_rd_pointer : unsigned_array_10(0 to CHANNELS-1) := (others => (others => '0')); +signal ram_count : unsigned_array_10(0 to CHANNELS-1) := (others => (others => '0')); + +signal ram_write : std_logic := '0'; +signal ram_remove : std_logic := '0'; +signal reg_ram_remove : std_logic := '0'; +signal reg2_ram_remove : std_logic := '0'; +signal ram_read : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); +signal ram_debug_read : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); +signal ram_clear : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); +signal ram_reset : std_logic := '0'; +signal ram_data_in : unsigned_array_18(0 to CHANNELS-1) := (others => (others => '0')); +signal ram_data_out : unsigned_array_18(0 to CHANNELS-1) := (others => (others => '0')); +signal reg_ram_data_out : unsigned_array_18(0 to CHANNELS-1) := (others => (others => '0')); +signal reg_buffer_addr : std_logic_vector(4 downto 0); +signal reg_buffer_read : std_logic; + +signal CONF : cfg_t; +attribute syn_keep of CONF : signal is true; +attribute syn_preserve of CONF : signal is true; + +signal stop_writing : std_logic := '0'; +signal stop_writing_rdo : std_logic := '0'; +signal finished_readout : std_logic := '0'; +signal baseline_reset : std_logic := '0'; +signal readout_reset : std_logic := '0'; +attribute syn_keep of baseline_reset : signal is true; +attribute syn_preserve of baseline_reset : signal is true; + +signal baseline_averages : arr_CHAN_RES_t := (others => (others => '0')); +signal baseline : arr_values_t := (others => (others => '0')); +signal trigger_gen : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); +signal reset_threshold_counter : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); +signal thresh_counter : unsigned_array_10(CHANNELS-1 downto 0) := (others => (others => '0')); +signal readout_flag : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); + +signal after_trg_cnt : unsigned(11 downto 0) := (others => '1'); + +type state_t is (IDLE, RELEASE_DIRECT, WAIT_FOR_END, CHECK_STATUS_TRIGGER, START, SEND_STATUS, READOUT, NEXT_BLOCK); +signal state : state_t; -- 800 - 83f last ADC values (local 0x0 - 0x3) -- 840 - 87f long-term average / baseline (local 0x4 - 0x7) @@ -50,27 +98,399 @@ signal baseline_averages : arr_CHAN_RES_t; begin +reg_buffer_addr <= DEBUG_BUFFER_ADDR when rising_edge(CLK); +reg_buffer_read <= DEBUG_BUFFER_READ when rising_edge(CLK); + +------------------------------------------------------------------------------- +-- Status registers +------------------------------------------------------------------------------- PROC_REGS : process variable c : integer range 0 to 3; begin wait until rising_edge(CLK); - c := to_integer(unsigned(DEBUG_BUFFER_ADDR(1 downto 0))); - DEBUG_BUFFER_READY <= '0'; - if DEBUG_BUFFER_READ = '1' then - case DEBUG_BUFFER_ADDR(3 downto 2) is - when "00" => DEBUG_BUFFER_DATA(RESOLUTION-1 downto 0) <= ADC_DATA(c*RESOLUTION+RESOLUTION-1 downto c*RESOLUTION); - DEBUG_BUFFER_READY <= '1'; - when "01" => DEBUG_BUFFER_DATA(23 downto 0) <= baseline_averages(c); - DEBUG_BUFFER_READY <= '1'; - when "10" => DEBUG_BUFFER_DATA <= x"DEADBEAF"; - DEBUG_BUFFER_READY <= '1'; - when "11" => DEBUG_BUFFER_DATA <= (others => '0'); DEBUG_BUFFER_READY <= '1'; - end case; + c := to_integer(unsigned(reg_buffer_addr(1 downto 0))); + DEBUG_BUFFER_DATA <= (others => '0'); + ram_debug_read <= (others => '0'); + if reg_buffer_read = '1' then + if reg_buffer_addr(4) = '0' then + DEBUG_BUFFER_READY <= '1'; + case reg_buffer_addr(3 downto 2) is + when "00" => DEBUG_BUFFER_DATA(RESOLUTION-1 downto 0) <= ADC_DATA(c*RESOLUTION+RESOLUTION-1 downto c*RESOLUTION); + when "01" => DEBUG_BUFFER_DATA(15 downto 0) <= std_logic_vector(baseline(c)); + when "10" => DEBUG_BUFFER_DATA(17 downto 0) <= std_logic_vector(reg_ram_data_out(to_integer(unsigned(reg_buffer_addr(1 downto 0))))); + ram_debug_read(to_integer(unsigned(reg_buffer_addr(1 downto 0)))) <= '1'; + when "11" => + DEBUG_BUFFER_DATA <= (others => '0'); + when others => null; + end case; + else + DEBUG_BUFFER_READY <= '1'; + DEBUG_BUFFER_DATA <= (others => '0'); + case reg_buffer_addr(3 downto 0) is + when x"0" => DEBUG_BUFFER_DATA <= std_logic_vector(resize(ram_count(1),16)) & + std_logic_vector(resize(ram_count(0),16)); + when x"1" => DEBUG_BUFFER_DATA <= std_logic_vector(resize(ram_count(3),16)) & + std_logic_vector(resize(ram_count(2),16)); + when x"2" => DEBUG_BUFFER_DATA(0) <= stop_writing; + DEBUG_BUFFER_DATA(1) <= stop_writing_rdo; + DEBUG_BUFFER_DATA(2) <= STOP_IN; + DEBUG_BUFFER_DATA(3) <= ram_remove; + DEBUG_BUFFER_DATA( 7 downto 4) <= ram_clear; + DEBUG_BUFFER_DATA(11 downto 8) <= ram_read; + DEBUG_BUFFER_DATA(12) <= ADC_VALID; + DEBUG_BUFFER_DATA(13) <= ram_write; + DEBUG_BUFFER_DATA(19 downto 16) <= trigger_gen; + DEBUG_BUFFER_DATA(23 downto 20) <= readout_flag; + when x"3" => DEBUG_BUFFER_DATA <= std_logic_vector(resize(ram_wr_pointer,32)); + when x"4" => DEBUG_BUFFER_DATA <= std_logic_vector(resize(ram_rd_pointer(1),16)) & + std_logic_vector(resize(ram_rd_pointer(0),16)); + when x"5" => DEBUG_BUFFER_DATA <= std_logic_vector(resize(ram_rd_pointer(3),16)) & + std_logic_vector(resize(ram_rd_pointer(2),16)); + when others => null; + end case; + end if; + end if; + + DEBUG_BUFFER_READY <= reg_buffer_read; + +end process; + +CONF <= CONFIG when rising_edge(CLK); + +ram_clear <= (others => CONTROL(4)) when rising_edge(CLK); +ram_reset <= CONTROL(5) when rising_edge(CLK); +baseline_reset <= CONTROL(8) when rising_edge(CLK); +readout_reset <= CONTROL(12) when rising_edge(CLK); + +------------------------------------------------------------------------------- +-- Preprocessing +------------------------------------------------------------------------------- + proc_preprocessor : process + variable cnt : integer range 0 to 255 := 0; + begin + wait until rising_edge(CLK); + ram_write <= '0'; + if ADC_VALID = '1' then + + gen_buffer_input : for i in 0 to CHANNELS-1 loop + if cnt = 0 then + ram_data_in(i)(15 downto 0) <= resize(unsigned(ADC_DATA(RESOLUTION*(i+1)-1 downto RESOLUTION*i)),16); + ram_data_in(i)(17) <= trigger_gen(i); + else + ram_data_in(i)(15 downto 0) <= ram_data_in(i)(15 downto 0) + resize(unsigned(ADC_DATA(RESOLUTION*(i+1)-1 downto RESOLUTION*i)),16); + ram_data_in(i)(17) <= ram_data_in(i)(17) or trigger_gen(i); + end if; + end loop; + + if cnt = to_integer(CONF.presum) then + cnt := 0; + ram_write <= not stop_writing; + elsif CONF.presum /= 0 then + cnt := cnt + 1; + end if; + end if; + + end process; + +-- if after_trg_cnt = 0 then +-- state <= READOUT; +-- stop_writing_rdo <= '1'; +-- else +-- after_trg_cnt <= after_trg_cnt - 1; +-- end if; + +------------------------------------------------------------------------------- +-- Data buffers +------------------------------------------------------------------------------- +proc_buffer_enable : process begin + wait until rising_edge(CLK); + if READOUT_RX.valid_timing_trg = '1' then + after_trg_cnt(10 downto 0) <= CONF.samples_after; + after_trg_cnt(11) <= '0'; + elsif after_trg_cnt(11) = '0' then + after_trg_cnt <= after_trg_cnt - 1; + end if; + + if or_all(std_logic_vector(after_trg_cnt)) = '0' then + stop_writing_rdo <= '1'; + after_trg_cnt <= (others => '1'); + end if; + + if finished_readout = '1' then + stop_writing_rdo <= '0'; + end if; + + stop_writing <= stop_writing_rdo or STOP_IN; + + if readout_reset = '1' then + stop_writing_rdo <= '0'; + after_trg_cnt <= (others => '1'); + end if; + +end process; + + +gen_buffers : for i in 0 to CHANNELS-1 generate + process begin + wait until rising_edge(CLK); + if ram_write = '1' then + ram(i)(to_integer(ram_wr_pointer)) <= ram_data_in(i); + end if; + ram_data_out(i) <= ram(i)(to_integer(ram_rd_pointer(i))); + end process; +end generate; + + +proc_buffer_write : process begin + wait until rising_edge(CLK); + if ram_reset = '1' then + ram_wr_pointer <= (others => '0'); + elsif ram_write = '1' then + ram_wr_pointer <= ram_wr_pointer + 1; + end if; +end process; + + +proc_buffer_rotate : process begin + wait until rising_edge(CLK); + if ram_count(0) >= CONF.buffer_depth and ram_write = '1' then + ram_remove <= '1'; + else + ram_remove <= '0'; end if; + reg_ram_remove <= ram_remove; + reg2_ram_remove <= reg_ram_remove; +end process; + + +gen_buffer_reader : for i in 0 to CHANNELS-1 generate + proc_buffer_reader : process begin + wait until rising_edge(CLK); + + if (ram_read(i) or ram_remove or ram_debug_read(i)) = ram_write then + ram_count(i) <= ram_wr_pointer - ram_rd_pointer(i); + elsif (ram_read(i) or ram_remove or ram_debug_read(i)) = '1' then + ram_count(i) <= ram_wr_pointer - ram_rd_pointer(i) -1; + elsif ram_write = '1' then + ram_count(i) <= ram_wr_pointer - ram_rd_pointer(i) +1; + end if; + + reg_ram_data_out(i) <= ram_data_out(i); + + if ram_reset = '1' then + ram_rd_pointer(i) <= (others => '1'); --one behind write pointer + elsif ram_clear(i) = '1' then + ram_rd_pointer(i) <= ram_wr_pointer; + elsif ram_read(i) = '1' then + ram_rd_pointer(i) <= ram_rd_pointer(i) + 1; + elsif ram_debug_read(i) = '1' then + ram_rd_pointer(i) <= ram_rd_pointer(i) + 1; + elsif ram_remove = '1' then + ram_rd_pointer(i) <= ram_rd_pointer(i) + 1; + end if; + + end process; +end generate; + + + +------------------------------------------------------------------------------- +-- Baseline +------------------------------------------------------------------------------- +gen_baselines : for i in 0 to CHANNELS-1 generate + proc_baseline_calc : process begin + wait until rising_edge(CLK); + if baseline_reset = '1' then + baseline_averages(i) <= CONF.baseline_reset_value; + elsif reg2_ram_remove = '1' and (ram_data_out(i)(17) = '0' or CONF.baseline_always_on = '1') then + baseline_averages(i) <= baseline_averages(i) + + resize(reg_ram_data_out(i)(15 downto 0),32) + - resize(baseline_averages(i)(to_integer(CONF.averaging)+15 downto to_integer(CONF.averaging)),32); + end if; + baseline(i) <= baseline_averages(i)(to_integer(CONF.averaging)+15 downto to_integer(CONF.averaging)); + end process; +end generate; + + + + + +------------------------------------------------------------------------------- +-- Trigger Output +------------------------------------------------------------------------------- +gen_triggers : for i in 0 to CHANNELS-1 generate + proc_trigger : process begin + wait until rising_edge(CLK); + if ram_write = '1' then + if (ram_data_in(i)(15 downto 0) > baseline(i) + CONF.trigger_threshold(15 downto 0) and CONF.trigger_threshold(16) = '0') + or (ram_data_in(i)(15 downto 0) < baseline(i) + CONF.trigger_threshold(15 downto 0) and CONF.trigger_threshold(16) = '1') then + trigger_gen(i) <= '1'; + else + trigger_gen(i) <= '0'; + end if; + elsif stop_writing = '1' then + trigger_gen(i) <= '0'; + end if; + end process; +end generate; + +TRIGGER_OUT <= or_all(trigger_gen and CONF.trigger_enable((DEVICE+1)*CHANNELS-1 downto DEVICE*CHANNELS)) when rising_edge(CLK); + + +------------------------------------------------------------------------------- +-- Readout Threshold +------------------------------------------------------------------------------- +gen_rdo_thresh : for i in 0 to CHANNELS-1 generate + proc_readout_threshold : process begin + wait until rising_edge(CLK); + if thresh_counter(i) > 0 and ram_write = '1' then + thresh_counter(i) <= thresh_counter(i) - 1; + end if; + + if thresh_counter(i) > 0 then + readout_flag(i) <= '1'; + else + readout_flag(i) <= '0'; + end if; + + if (ram_data_in(i)(15 downto 0) > baseline(i) + CONF.readout_threshold(15 downto 0) and CONF.readout_threshold(16) = '0') + or (ram_data_in(i)(15 downto 0) < baseline(i) + CONF.readout_threshold(15 downto 0) and CONF.readout_threshold(16) = '1') then + reset_threshold_counter(i) <= '1'; + else + reset_threshold_counter(i) <= '0'; + end if; + + if reset_threshold_counter(i) = '1' then + thresh_counter(i) <= CONF.buffer_depth(9 downto 0); + end if; + end process; +end generate; + + +------------------------------------------------------------------------------- +-- Readout State Machine +------------------------------------------------------------------------------- +proc_readout : process + variable wordcount : integer range 0 to 1023 := 0; + variable blockcount : integer range 0 to 3 := 0; + variable sumcount : integer range 0 to 1023 := 0; +begin + wait until rising_edge(CLK); + READOUT_TX.busy_release <= '0'; + READOUT_TX.data_finished <= '0'; + READOUT_TX.data_write <= '0'; + finished_readout <= '0'; - DEBUG_BUFFER_READY <= DEBUG_BUFFER_READ; - DEBUG_BUFFER_DATA(3 downto 0) <= DEBUG_BUFFER_ADDR; + case state is + when IDLE => + READOUT_TX.statusbits <= (others => '0'); + if READOUT_RX.valid_notiming_trg = '1' then + state <= CHECK_STATUS_TRIGGER; + elsif READOUT_RX.data_valid = '1' then --seems to have missed trigger... + READOUT_TX.statusbits <= (23 => '1', others => '0'); --event not found + state <= RELEASE_DIRECT; + elsif READOUT_RX.valid_timing_trg = '1' then + state <= START; + end if; + + when RELEASE_DIRECT => + if READOUT_RX.data_valid = '1' then + finished_readout <= '1'; + READOUT_TX.busy_release <= '1'; + READOUT_TX.data_finished <= '1'; + state <= WAIT_FOR_END; + end if; + + when WAIT_FOR_END => + if READOUT_RX.data_valid = '0' then + state <= IDLE; + end if; + + when CHECK_STATUS_TRIGGER => + if READOUT_RX.data_valid = '1' then + if READOUT_RX.trg_type = x"E" then + state <= SEND_STATUS; + else + state <= RELEASE_DIRECT; + end if; + end if; + + when START => + if stop_writing_rdo = '1' then + state <= READOUT; + end if; + + when READOUT => + state <= RELEASE_DIRECT; + READOUT_TX.data <= x"DEADBEEF"; + READOUT_TX.data_write <= '1'; + + when NEXT_BLOCK => + if blockcount = CONF.block_count -1 then + state <= RELEASE_DIRECT; + blockcount := 0; + else + state <= READOUT; + blockcount := blockcount + 1; + end if; + + when SEND_STATUS => + state <= RELEASE_DIRECT; + READOUT_TX.data <= x"DECAFBAD"; + READOUT_TX.data_write <= '1'; + end case; end process; end architecture; +-- type READOUT_RX is record +-- data_valid : std_logic; +-- valid_timing_trg : std_logic; +-- valid_notiming_trg : std_logic; +-- invalid_trg : std_logic; +-- -- +-- trg_type : std_logic_vector( 3 downto 0); +-- trg_number : std_logic_vector(15 downto 0); +-- trg_code : std_logic_vector( 7 downto 0); +-- trg_information : std_logic_vector(23 downto 0); +-- trg_int_number : std_logic_vector(15 downto 0); +-- -- +-- trg_multiple : std_logic; +-- trg_timeout : std_logic; +-- trg_spurious : std_logic; +-- trg_missing : std_logic; +-- trg_spike : std_logic; +-- -- +-- buffer_almost_full : std_logic; +-- end record; +-- +-- +-- type READOUT_TX is record +-- busy_release : std_logic; +-- statusbits : std_logic_vector(31 downto 0); +-- data : std_logic_vector(31 downto 0); +-- data_write : std_logic; +-- data_finished : std_logic; +-- end record; +-- + +-- +-- type cfg_t is record +-- buffer_depth : unsigned(10 downto 0); +-- samples_after : unsigned(10 downto 0); +-- block_count : unsigned( 1 downto 0); +-- trigger_threshold : unsigned(17 downto 0); +-- readout_threshold : unsigned(17 downto 0); +-- presum : unsigned( 7 downto 0); +-- averaging : unsigned( 3 downto 0); +-- block_avg : unsigned_array_8(0 to 3); +-- block_sums : unsigned_array_8(0 to 3); +-- block_scale : unsigned_array_8(0 to 3); +-- end record; + +-- 0-ACVVVV -- ADC data, 16 bit data, MSN=0x0 +-- vVVVvVVV -- ADC data, 2x 15 bit only after 0x0 channel header, MSB=1 +-- VVVVVVVV -- ADC data 2x 16 bit, only after 0x4 channel header +-- 1SSSSSSS -- Status word, MSN=0x1 +-- 4-AC--LL -- ADC Header, L: number of data words that follow, MSN=0x4 + diff --git a/ADC/trb3_periph_adc.prj b/ADC/trb3_periph_adc.prj index b0e442a..edc5426 100644 --- a/ADC/trb3_periph_adc.prj +++ b/ADC/trb3_periph_adc.prj @@ -154,4 +154,4 @@ add_file -vhdl -lib "work" "source/adc_handler.vhd" add_file -vhdl -lib "work" "source/adc_slowcontrol_data_buffer.vhd" add_file -vhdl -lib "work" "trb3_periph_adc.vhd" - +add_file -constraint "trb3_periph_adc.sdc" diff --git a/ADC/trb3_periph_adc.sdc b/ADC/trb3_periph_adc.sdc new file mode 100644 index 0000000..0909361 --- /dev/null +++ b/ADC/trb3_periph_adc.sdc @@ -0,0 +1,53 @@ +# Synopsys, Inc. constraint file +# /d/jspc22/trb/git/trb3/ADC/trb3_periph_adc.sdc +# Written on Tue Aug 26 14:58:43 2014 +# by Synplify Pro, F-2012.03-SP1 Scope Editor + +# +# Collections +# + +# +# Clocks +# +define_clock {CLK_PCLK_RIGHT} -name {CLK_PCLK_RIGHT} -freq 200 -clockgroup default_clkgroup_0 +define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -freq 100 -clockgroup default_clkgroup_1 +define_clock {TRIGGER_LEFT} -name {TRIGGER_LEFT} -freq 10 -clockgroup default_clkgroup_2 +define_clock {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk} -freq 100 -clockgroup default_clkgroup_3 +define_clock {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk} -freq 100 -clockgroup default_clkgroup_4 +define_clock {n:THE_MAIN_PLL.CLKOP} -name {n:THE_MAIN_PLL.CLKOP} -freq 100 -clockgroup default_clkgroup_5 +define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -freq 100 -clockgroup default_clkgroup_6 +define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_rx_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_rx_ch1} -freq 100 -clockgroup default_clkgroup_7 +define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_tx_ch} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_tx_ch} -freq 100 -clockgroup default_clkgroup_8 + +# +# Clock to Clock +# + +# +# Inputs/Outputs +# + +# +# Registers +# + +# +# Delay Paths +# + +# +# Attributes +# + +# +# I/O Standards +# + +# +# Compile Points +# + +# +# Other +# diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd index 849b178..d24e4ae 100644 --- a/ADC/trb3_periph_adc.vhd +++ b/ADC/trb3_periph_adc.vhd @@ -142,18 +142,6 @@ architecture trb3_periph_adc_arch of trb3_periph_adc is signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); - --RegIO - signal regio_addr_out : std_logic_vector (15 downto 0); - signal regio_read_enable_out : std_logic; - signal regio_write_enable_out : std_logic; - signal regio_data_out : std_logic_vector (31 downto 0); - signal regio_data_in : std_logic_vector (31 downto 0); - signal regio_dataready_in : std_logic; - signal regio_no_more_data_in : std_logic; - signal regio_write_ack_in : std_logic; - signal regio_unknown_addr_in : std_logic; - signal regio_timeout_out : std_logic; - --Timer signal global_time : std_logic_vector(31 downto 0); signal local_time : std_logic_vector(7 downto 0); @@ -164,13 +152,9 @@ architecture trb3_periph_adc_arch of trb3_periph_adc is signal spi_cs : std_logic_vector(15 downto 0); signal spi_sdi, spi_sdo, spi_sck : std_logic; signal adcspi_ctrl : std_logic_vector(7 downto 0); - - signal busadc_rx : CTRLBUS_RX; - signal busadc_tx : CTRLBUS_TX; - signal busspi_rx : CTRLBUS_RX; - signal busspi_tx : CTRLBUS_TX; - signal busmem_rx : CTRLBUS_RX; - signal busmem_tx : CTRLBUS_TX; + + signal regio_rx, busadc_rx, busspi_rx, busmem_rx : CTRLBUS_RX; + signal regio_tx, busadc_tx, busspi_tx, busmem_tx : CTRLBUS_TX; signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to 11); @@ -341,16 +325,16 @@ begin REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), - BUS_ADDR_OUT => regio_addr_out, - BUS_READ_ENABLE_OUT => regio_read_enable_out, - BUS_WRITE_ENABLE_OUT => regio_write_enable_out, - BUS_DATA_OUT => regio_data_out, - BUS_DATA_IN => regio_data_in, - BUS_DATAREADY_IN => regio_dataready_in, - BUS_NO_MORE_DATA_IN => regio_no_more_data_in, - BUS_WRITE_ACK_IN => regio_write_ack_in, - BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, - BUS_TIMEOUT_OUT => regio_timeout_out, + BUS_ADDR_OUT => regio_rx.addr, --regio_addr_out, + BUS_READ_ENABLE_OUT => regio_rx.read, --regio_read_enable_out, + BUS_WRITE_ENABLE_OUT => regio_rx.write, --regio_write_enable_out, + BUS_DATA_OUT => regio_rx.data, --regio_data_out, + BUS_DATA_IN => regio_tx.data, --regio_data_in, + BUS_DATAREADY_IN => regio_tx.ack, --regio_dataready_in, + BUS_NO_MORE_DATA_IN => regio_tx.nack, --regio_no_more_data_in, + BUS_WRITE_ACK_IN => regio_tx.ack, --regio_write_ack_in, + BUS_UNKNOWN_ADDR_IN => regio_tx.unknown, --regio_unknown_addr_in, + BUS_TIMEOUT_OUT => regio_rx.timeout, --regio_timeout_out, ONEWIRE_INOUT => TEMPSENS, ONEWIRE_MONITOR_OUT => open, @@ -399,7 +383,8 @@ gen_reallogic : if USE_DUMMY_READOUT = 0 generate ADC_DATA(54 downto 50) => ADC11_CH, ADC_DATA(59 downto 55) => ADC12_CH, ADC_DCO => ADC_DCO, - + TRIGGER_FLAG_OUT => FPGA5_COMM(7), + TRIGGER_IN => TRIGGER_LEFT, READOUT_RX => readout_rx, READOUT_TX => readout_tx, @@ -437,8 +422,8 @@ gen_dummyreadout : if USE_DUMMY_READOUT = 1 generate BUS_TX => busadc_tx ); end generate; - + --------------------------------------------------------------------------- -- Bus Handler --------------------------------------------------------------------------- @@ -453,22 +438,14 @@ end generate; CLK => clk_100_i, RESET => reset_i, - DAT_ADDR_IN => regio_addr_out, - DAT_DATA_IN => regio_data_out, - DAT_DATA_OUT => regio_data_in, - DAT_READ_ENABLE_IN => regio_read_enable_out, - DAT_WRITE_ENABLE_IN => regio_write_enable_out, - DAT_TIMEOUT_IN => regio_timeout_out, - DAT_DATAREADY_OUT => regio_dataready_in, - DAT_WRITE_ACK_OUT => regio_write_ack_in, - DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, - DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, - + REGIO_RX => regio_rx, + REGIO_TX => regio_tx, + BUS_RX(0) => busmem_rx, --Flash - BUS_TX(0) => busmem_tx, BUS_RX(1) => busspi_rx, --SPI - BUS_TX(1) => busspi_tx, BUS_RX(2) => busadc_rx, --ADC + BUS_TX(0) => busmem_tx, + BUS_TX(1) => busspi_tx, BUS_TX(2) => busadc_tx, STAT_DEBUG => open diff --git a/ADC/trb3_periph_adc_constraints.lpf b/ADC/trb3_periph_adc_constraints.lpf index d1099d2..97dda0e 100644 --- a/ADC/trb3_periph_adc_constraints.lpf +++ b/ADC/trb3_periph_adc_constraints.lpf @@ -9,9 +9,9 @@ BLOCK RD_DURING_WR_PATHS ; SYSCONFIG MCCLK_FREQ = 20; FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; -FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; -FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; -FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; +#FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +#FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; +#FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; ################################################################# # Reset Nets @@ -28,12 +28,46 @@ LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SI REGION "MEDIA_UPLINK" "R102C95D" 13 25; LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; +MULTICYCLE TO CELL "THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns; + + +################################################################# +# ADC Processor +################################################################# + +# UGROUP "Proc_0" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_0_THE_ADC_PROC; +# UGROUP "Proc_1" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_1_THE_ADC_PROC; +# UGROUP "Proc_2" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_2_THE_ADC_PROC; +# UGROUP "Proc_3" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_3_THE_ADC_PROC; +# UGROUP "Proc_4" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_4_THE_ADC_PROC; +# UGROUP "Proc_5" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_5_THE_ADC_PROC; +# UGROUP "Proc_6" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_6_THE_ADC_PROC; +# UGROUP "Proc_7" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_7_THE_ADC_PROC; +# UGROUP "Proc_8" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_8_THE_ADC_PROC; +# UGROUP "Proc_9" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_9_THE_ADC_PROC; +# UGROUP "Proc_10" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_10_THE_ADC_PROC; +# UGROUP "Proc_11" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_11_THE_ADC_PROC; + + ################################################################# # Clocks ################################################################# -USE PRIMARY NET "CLK_GPLL_RIGHT_c"; -USE PRIMARY NET "CLK_PCLK_LEFT_c"; +#USE PRIMARY NET "CLK_GPLL_RIGHT_c"; +#USE PRIMARY NET "CLK_PCLK_LEFT_c"; + USE PRIMARY NET "CLK_PCLK_RIGHT_c"; #USE PRIMARY2EDGE NET "THE_ADC/clk_adcfast_i_0"; diff --git a/base/make_version_vhd.pl b/base/make_version_vhd.pl new file mode 100755 index 0000000..a6d8849 --- /dev/null +++ b/base/make_version_vhd.pl @@ -0,0 +1,26 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; +use FileHandle; + +# generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; \ No newline at end of file