From: hadeshyp Date: Tue, 17 Apr 2012 14:00:49 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=569e66d4ad65d488cd92f77af0dd08c40b52a96f;p=trb3.git *** empty log message *** --- diff --git a/base/compile_periph_frankfurt.pl b/base/compile_periph_frankfurt.pl index 3c64fc9..1aeca21 100755 --- a/base/compile_periph_frankfurt.pl +++ b/base/compile_periph_frankfurt.pl @@ -10,8 +10,8 @@ use strict; #Settings for this project my $TOPNAME = "trb3_periph"; #Name of top-level entity my $BasePath = "../base/"; #path to "base" directory -my $lattice_path = '/d/sugar/lattice/diamond/1.3'; -my $synplify_path = '/d/sugar/lattice/synplify/D-2010.03/'; +my $lattice_path = '/d/jspc29/lattice/diamond/1.4'; +my $synplify_path = '/d/jspc29/lattice/synplify/D-2010.03/'; my $lm_license_file_for_synplify = "27000\@localhost"; my $lm_license_file_for_par = "1710\@cronos.e12.physik.tu-muenchen.de"; ################################################################################### diff --git a/base/cores/pll_in125_out125.ipx b/base/cores/pll_in125_out125.ipx new file mode 100644 index 0000000..05a2e8e --- /dev/null +++ b/base/cores/pll_in125_out125.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/base/cores/pll_in125_out125.lpc b/base/cores/pll_in125_out125.lpc new file mode 100644 index 0000000..e26f1c7 --- /dev/null +++ b/base/cores/pll_in125_out125.lpc @@ -0,0 +1,66 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.2 +ModuleName=pll_in125_out125 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=10/18/2011 +Time=17:58:51 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=125 +Div=1 +ClkOPBp=0 +Post=8 +U_OFrq=125 +OP_Tol=0.0 +OFrq=125.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=Internal +Mult=1 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=50 +OK_Tol=0.0 +KFrq=200.000000 +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth= +;DelayControl=No +EnCLKOS=1 +ClkOSBp=1 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 diff --git a/base/cores/pll_in125_out125.vhd b/base/cores/pll_in125_out125.vhd new file mode 100644 index 0000000..e38b9a1 --- /dev/null +++ b/base/cores/pll_in125_out125.vhd @@ -0,0 +1,104 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.2 +--/d/sugar/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n pll_in125_out125 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -bypasss -fclkop 125 -fclkop_tol 0.0 -fb_mode INTERNAL -phaseadj 0.0 -duty 8 -noclkok -norst -noclkok2 -e + +-- Tue Oct 18 17:58:51 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_in125_out125 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_in125_out125 : entity is true; +end pll_in125_out125; + +architecture Structure of pll_in125_out125 is + + -- internal signal declarations + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal CLKFB_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "125.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "125.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000"; + attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "50.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "ENABLED", CLKOP_BYPASS=> "DISABLED", CLKOK_INPUT=> "CLKOP", + DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, CLKOS_TRIM_DELAY=> 0, + CLKOS_TRIM_POL=> "RISING", CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 1, CLKI_DIV=> 1, + FIN=> "125.000000") + port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>CLKOS_t, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>CLKFB_t); + + CLKOS <= CLKOS_t; + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_in125_out125 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/trb3a.xcf b/base/trb3a.xcf new file mode 100644 index 0000000..e69de29