From: Andreas Neiser Date: Thu, 19 Feb 2015 16:17:35 +0000 (+0100) Subject: Integral delay correctly set X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=56f078bd5bed077002da8bf195c77ff31c8ef73d;p=trb3.git Integral delay correctly set --- diff --git a/ADC/sim/tb_adcprocessor_cfd.vhd b/ADC/sim/tb_adcprocessor_cfd.vhd index fb51cff..5eef971 100644 --- a/ADC/sim/tb_adcprocessor_cfd.vhd +++ b/ADC/sim/tb_adcprocessor_cfd.vhd @@ -40,6 +40,8 @@ begin config.CFDDelay <= to_unsigned(2, 5); config.CFDMult <= to_unsigned(2, 4); config.CFDMultDly <= to_unsigned(3, 4); + + config.IntegrateWindow <= to_unsigned(60, 8); config.CheckWord1 <= (others => '0'); config.CheckWord2 <= (others => '0'); diff --git a/ADC/source/adc_processor_cfd_ch.vhd b/ADC/source/adc_processor_cfd_ch.vhd index 524b9a7..f5b7c47 100644 --- a/ADC/source/adc_processor_cfd_ch.vhd +++ b/ADC/source/adc_processor_cfd_ch.vhd @@ -30,7 +30,7 @@ architecture arch of adc_processor_cfd_ch is constant RESOLUTION_BASEAVG : integer := RESOLUTION + 2 ** CONF.BaselineAverage'length - 1; constant LENGTH_BASEDLY : integer := 32; -- longer than typical pulses? constant LENGTH_CFDDLY : integer := 2 ** CONF.CFDDelay'length; - constant LENGTH_INTDLY : integer := 2; -- must match CFD/zeroX calculation chain + constant LENGTH_INTDLY : integer := 3; -- must match CFD/zeroX calculation chain type unsigned_in_thresh_t is record value : unsigned(RESOLUTION - 1 downto 0); @@ -74,7 +74,7 @@ architecture arch of adc_processor_cfd_ch is signal delay_cfd_out : signed(RESOLUTION_SUB - 1 downto 0) := (others => '0'); signal prod, prod_invert : product_thresh_t := product_thresh_t_INIT; - signal prod_delay : signed(RESOLUTION_PROD - 1 downto 0); + signal prod_delay : signed(RESOLUTION_PROD - 1 downto 0) := (others => '0'); signal cfd : cfd_thresh_t := cfd_thresh_t_INIT; -- the bipolar signal signal cfd_prev, cfd_prev_save, cfd_save : signed(RESOLUTION_CFD - 1 downto 0) := (others => '0');