From: hadeshyp <hadeshyp>
Date: Wed, 17 Mar 2010 15:39:16 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~317
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=575d733f7c7a51358de650601d2b5ad4827728ae;p=trbnet.git

*** empty log message ***
---

diff --git a/lattice/ecp2m/pll_in100_out25.lpc b/lattice/ecp2m/pll_in100_out25.lpc
index 5c5a0c8..91af49f 100644
--- a/lattice/ecp2m/pll_in100_out25.lpc
+++ b/lattice/ecp2m/pll_in100_out25.lpc
@@ -16,8 +16,8 @@ CoreRevision=5.1
 ModuleName=pll_in100_out25
 SourceFormat=Schematic/VHDL
 ParameterFileVersion=1.0
-Date=03/10/2010
-Time=19:09:50
+Date=03/12/2010
+Time=18:02:06
 
 [Parameters]
 Verilog=0
@@ -40,7 +40,7 @@ Div=4
 Mult=1
 Post=48
 SecD=2
-fb_mode=CLKOP
+fb_mode=Internal
 PhaseDuty=Static
 DelayControl=AUTO_NO_DELAY
 External=AUTO
diff --git a/lattice/ecp2m/pll_in100_out25.vhd b/lattice/ecp2m/pll_in100_out25.vhd
index a1a7468..d76bbde 100644
--- a/lattice/ecp2m/pll_in100_out25.vhd
+++ b/lattice/ecp2m/pll_in100_out25.vhd
@@ -1,8 +1,8 @@
 -- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
 -- Module  Version: 5.1
---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out25 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -fclkop 25 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode CLOCKTREE -extcap AUTO -noclkos -noclkok -norst -e 
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out25 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -fclkop 25 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode INTERNAL -extcap AUTO -noclkos -noclkok -norst -e 
 
--- Wed Mar 10 19:09:50 2010
+-- Fri Mar 12 18:02:07 2010
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -24,6 +24,7 @@ architecture Structure of pll_in100_out25 is
 
     -- internal signal declarations
     signal CLKOP_t: std_logic;
+    signal CLKFB_t: std_logic;
     signal scuba_vlo: std_logic;
     signal CLK_t: std_logic;
 
@@ -97,12 +98,12 @@ begin
         PHASE_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", CLKOP_DIV=>  48, 
         CLKFB_DIV=>  1, CLKI_DIV=>  4)
         -- synopsys translate_on
-        port map (CLKI=>CLK_t, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
+        port map (CLKI=>CLK_t, CLKFB=>CLKFB_t, RST=>scuba_vlo, 
             RSTK=>scuba_vlo, DPAMODE=>scuba_vlo, DRPAI3=>scuba_vlo, 
             DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
             DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
             DFPAI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, 
-            LOCK=>LOCK, CLKINTFB=>open);
+            LOCK=>LOCK, CLKINTFB=>CLKFB_t);
 
     CLKOP <= CLKOP_t;
     CLK_t <= CLK;