From: Tobias Weber Date: Fri, 21 Nov 2014 08:50:42 +0000 (+0100) Subject: Works fine with 1 sensor per fpga. Implementing 2 sensors leads to timing violation... X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=57f54ac8cb6678048551a4a65babf942b1304431;p=trb3.git Works fine with 1 sensor per fpga. Implementing 2 sensors leads to timing violation. First FiFo does not save data persistently, while second does. --- diff --git a/base/trb3_periph_mupix.lpf b/base/trb3_periph_mupix.lpf index 1053a3a..f5c16ef 100644 --- a/base/trb3_periph_mupix.lpf +++ b/base/trb3_periph_mupix.lpf @@ -123,112 +123,213 @@ DEFINE PORT GROUP "LED_group" "LED*" ; IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; ################################################################# -#MuPix 4 +#MuPix 3/4/6 ################################################################# +#Mupix 0 #SlowControl and Misc -LOCATE COMP "fpga_led_to_board_0" SITE "AB5"; -LOCATE COMP "fpga_led_to_board_1" SITE "AB6"; -LOCATE COMP "fpga_led_to_board_2" SITE "Y6"; -LOCATE COMP "fpga_led_to_board_3" SITE "Y7"; -DEFINE PORT GROUP "fpga_led_group" "fpga_led*"; -IOBUF GROUP "fpga_led_group" IO_TYPE=LVCMOS25; - -LOCATE COMP "fpga_aux_to_board_0" SITE "T7"; -LOCATE COMP "fpga_aux_to_board_1" SITE "R6"; -LOCATE COMP "fpga_aux_to_board_2" SITE "K2"; -LOCATE COMP "fpga_aux_to_board_3" SITE "T8"; -LOCATE COMP "fpga_aux_to_board_4" SITE "K4"; -LOCATE COMP "fpga_aux_to_board_5" SITE "K1"; -LOCATE COMP "fpga_aux_to_board_6" SITE "E1"; -LOCATE COMP "fpga_aux_to_board_7" SITE "K5"; -LOCATE COMP "fpga_aux_to_board_8" SITE "B2"; -LOCATE COMP "fpga_aux_to_board_9" SITE "B3"; -DEFINE PORT GROUP "fpga_aux_group" "fpga_aux*"; -IOBUF GROUP "fpga_aux_group" IO_TYPE=LVCMOS25; - -LOCATE COMP "testpulse2_to_board" SITE "AA4"; -LOCATE COMP "testpulse1_to_board" SITE "AA3"; -IOBUF PORT "testpulse2_to_board" IO_TYPE=LVCMOS25 ; -IOBUF PORT "testpulse1_to_board" IO_TYPE=LVCMOS25 ; - -LOCATE COMP "spi_din_to_board" SITE "T3"; -LOCATE COMP "spi_ld_to_board" SITE "R5"; -LOCATE COMP "spi_clk_to_board" SITE "R4"; -DEFINE PORT GROUP "spi_group" "spi*"; -IOBUF GROUP "spigroup" IO_TYPE=LVCMOS25; - -LOCATE COMP "hbus_from_mupix" SITE "W8"; -IOBUF PORT "hbus_from_mupix" IO_TYPE=LVCMOS25 ; -LOCATE COMP "sout_d_from_mupix" SITE "V1"; -IOBUF PORT "sout_d_from_mupix" IO_TYPE=LVCMOS25 ; -LOCATE COMP "sout_c_from_mupix" SITE "U2"; -IOBUF PORT "sout_c_from_mupix" IO_TYPE=LVCMOS25 ; -LOCATE COMP "sin_to_mupix" SITE "T1"; -IOBUF PORT "sin_to_mupix" IO_TYPE=LVCMOS25 ; -LOCATE COMP "ck_d_to_mupix" SITE "P4"; -IOBUF PORT "ck_d_to_mupix" IO_TYPE=LVCMOS25 ; -LOCATE COMP "ld_c_to_mupix" SITE "U1"; -IOBUF PORT "ld_c_to_mupix" IO_TYPE=LVCMOS25 ; -LOCATE COMP "ck_c_to_mupix" SITE "R3"; -IOBUF PORT "ck_c_to_mupix" IO_TYPE=LVCMOS25 ; +LOCATE COMP "fpga_led_to_board0_0" SITE "AB5"; +LOCATE COMP "fpga_led_to_board0_1" SITE "AB6"; +LOCATE COMP "fpga_led_to_board0_2" SITE "Y6"; +LOCATE COMP "fpga_led_to_board0_3" SITE "Y7"; +DEFINE PORT GROUP "fpga_led0_group" "fpga_led_to_board0*"; +IOBUF GROUP "fpga_led0_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "fpga_aux_to_board0_0" SITE "T7"; +LOCATE COMP "fpga_aux_to_board0_1" SITE "R6"; +LOCATE COMP "fpga_aux_to_board0_2" SITE "K2"; +LOCATE COMP "fpga_aux_to_board0_3" SITE "T8"; +LOCATE COMP "fpga_aux_to_board0_4" SITE "K4"; +LOCATE COMP "fpga_aux_to_board0_5" SITE "K1"; +LOCATE COMP "fpga_aux_to_board0_6" SITE "E1"; +LOCATE COMP "fpga_aux_to_board0_7" SITE "K5"; +LOCATE COMP "fpga_aux_to_board0_8" SITE "B2"; +LOCATE COMP "fpga_aux_to_board0_9" SITE "B3"; +DEFINE PORT GROUP "fpga_aux0_group" "fpga_aux_to_board0*"; +IOBUF GROUP "fpga_aux0_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "testpulse2_to_board0" SITE "AA4"; +LOCATE COMP "testpulse1_to_board0" SITE "AA3"; +IOBUF PORT "testpulse2_to_board0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "testpulse1_to_board0" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "spi_din_to_board0" SITE "T3"; +LOCATE COMP "spi_ld_to_board0" SITE "R5"; +LOCATE COMP "spi_clk_to_board0" SITE "R4"; +IOBUF PORT "spi_din_to_board0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "spi_ld_to_board0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "spi_clk_to_board0" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "hbus_from_mupix0" SITE "W8"; +IOBUF PORT "hbus_from_mupix0" IO_TYPE=LVCMOS25 ; +LOCATE COMP "sout_d_from_mupix0" SITE "V1"; +IOBUF PORT "sout_d_from_mupix0" IO_TYPE=LVCMOS25 ; +LOCATE COMP "sout_c_from_mupix0" SITE "U2"; +IOBUF PORT "sout_c_from_mupix0" IO_TYPE=LVCMOS25 ; +LOCATE COMP "sin_to_mupix0" SITE "T1"; +IOBUF PORT "sin_to_mupix0" IO_TYPE=LVCMOS25 ; +LOCATE COMP "ck_d_to_mupix0" SITE "P4"; +IOBUF PORT "ck_d_to_mupix0" IO_TYPE=LVCMOS25 ; +LOCATE COMP "ld_c_to_mupix0" SITE "U1"; +IOBUF PORT "ld_c_to_mupix0" IO_TYPE=LVCMOS25 ; +LOCATE COMP "ck_c_to_mupix0" SITE "R3"; +IOBUF PORT "ck_c_to_mupix0" IO_TYPE=LVCMOS25 ; #MuPix Readout -LOCATE COMP "rowaddr_from_mupix_0" SITE "H2"; -LOCATE COMP "rowaddr_from_mupix_1" SITE "H1"; -LOCATE COMP "rowaddr_from_mupix_2" SITE "M5"; -LOCATE COMP "rowaddr_from_mupix_3" SITE "L2"; -LOCATE COMP "rowaddr_from_mupix_4" SITE "C2"; -LOCATE COMP "rowaddr_from_mupix_5" SITE "K3"; -DEFINE PORT GROUP "rowaddr_from_mupix_group" "rowaddr_from_mupix*"; -IOBUF GROUP "rowaddr_from_mupix_group" IO_TYPE=LVCMOS25; - -LOCATE COMP "coladdr_from_mupix_0" SITE "W6"; -LOCATE COMP "coladdr_from_mupix_1" SITE "AA5"; -LOCATE COMP "coladdr_from_mupix_2" SITE "V7"; -LOCATE COMP "coladdr_from_mupix_3" SITE "G1"; -LOCATE COMP "coladdr_from_mupix_4" SITE "J1"; -LOCATE COMP "coladdr_from_mupix_5" SITE "L1"; -DEFINE PORT GROUP "coladdr_from_mupix_group" "coladdr_from_mupix*"; -IOBUF GROUP "coladdr_from_mupix_group" IO_TYPE=LVCMOS25; - -LOCATE COMP "timestamp_from_mupix_0" SITE "U3"; -LOCATE COMP "timestamp_from_mupix_1" SITE "R2"; -LOCATE COMP "timestamp_from_mupix_2" SITE "P3"; -LOCATE COMP "timestamp_from_mupix_3" SITE "P6"; -LOCATE COMP "timestamp_from_mupix_4" SITE "N6"; -LOCATE COMP "timestamp_from_mupix_5" SITE "AC3"; -LOCATE COMP "timestamp_from_mupix_6" SITE "AC1"; -LOCATE COMP "timestamp_from_mupix_7" SITE "AA2"; -DEFINE PORT GROUP "timestamp_from_mupix_group" "timestamp_from_mupix*"; -IOBUF GROUP "timestamp_from_mupix_group" IO_TYPE=LVCMOS25; - -LOCATE COMP "timestamp_to_mupix_0" SITE "P5"; -LOCATE COMP "timestamp_to_mupix_1" SITE "N5"; -LOCATE COMP "timestamp_to_mupix_2" SITE "AC2"; -LOCATE COMP "timestamp_to_mupix_3" SITE "AB1"; -LOCATE COMP "timestamp_to_mupix_4" SITE "AA1"; -LOCATE COMP "timestamp_to_mupix_5" SITE "W7"; -LOCATE COMP "timestamp_to_mupix_6" SITE "Y5"; -LOCATE COMP "timestamp_to_mupix_7" SITE "V6"; -DEFINE PORT GROUP "timestamp_to_mupix_group" "timestamp_to_mupix*"; -IOBUF GROUP "timestamp_to_mupix_group" IO_TYPE=LVCMOS25; - - -LOCATE COMP "ldpix_to_mupix" SITE "T2"; -IOBUF PORT "ldpix_to_mupix" IO_TYPE=LVCMOS25 ; -LOCATE COMP "ldcol_to_mupix" SITE "N3"; -IOBUF PORT "ldcol_to_mupix" IO_TYPE=LVCMOS25 ; -LOCATE COMP "rdcol_to_mupix" SITE "J4"; -IOBUF PORT "rdcol_to_mupix" IO_TYPE=LVCMOS25 ; -LOCATE COMP "pulldown_to_mupix" SITE "L3"; -IOBUF PORT "pulldown_to_mupix" IO_TYPE=LVCMOS25 ; -LOCATE COMP "priout_from_mupix" SITE "J3"; -IOBUF PORT "priout_from_mupix" IO_TYPE=LVCMOS25 ; - - - - +LOCATE COMP "rowaddr_from_mupix0_0" SITE "H2"; +LOCATE COMP "rowaddr_from_mupix0_1" SITE "H1"; +LOCATE COMP "rowaddr_from_mupix0_2" SITE "M5"; +LOCATE COMP "rowaddr_from_mupix0_3" SITE "L2"; +LOCATE COMP "rowaddr_from_mupix0_4" SITE "C2"; +LOCATE COMP "rowaddr_from_mupix0_5" SITE "K3"; +DEFINE PORT GROUP "rowaddr_from_mupix0_group" "rowaddr_from_mupix0*"; +IOBUF GROUP "rowaddr_from_mupix0_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "coladdr_from_mupix0_0" SITE "W6"; +LOCATE COMP "coladdr_from_mupix0_1" SITE "AA5"; +LOCATE COMP "coladdr_from_mupix0_2" SITE "V7"; +LOCATE COMP "coladdr_from_mupix0_3" SITE "G1"; +LOCATE COMP "coladdr_from_mupix0_4" SITE "J1"; +LOCATE COMP "coladdr_from_mupix0_5" SITE "L1"; +DEFINE PORT GROUP "coladdr_from_mupix0_group" "coladdr_from_mupix0*"; +IOBUF GROUP "coladdr_from_mupix0_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "timestamp_from_mupix0_0" SITE "M21"; +LOCATE COMP "timestamp_from_mupix0_1" SITE "J24"; +LOCATE COMP "timestamp_from_mupix0_2" SITE "M24"; +LOCATE COMP "timestamp_from_mupix0_3" SITE "K25"; +LOCATE COMP "timestamp_from_mupix0_4" SITE "N21"; +LOCATE COMP "timestamp_from_mupix0_5" SITE "K26"; +LOCATE COMP "timestamp_from_mupix0_6" SITE "N22"; +LOCATE COMP "timestamp_from_mupix0_7" SITE "L19"; +DEFINE PORT GROUP "timestamp_from_mupix0_group" "timestamp_from_mupix0*"; +IOBUF GROUP "timestamp_from_mupix0_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "timestamp_to_mupix0_0" SITE "L24"; +LOCATE COMP "timestamp_to_mupix0_1" SITE "M22"; +LOCATE COMP "timestamp_to_mupix0_2" SITE "J26"; +LOCATE COMP "timestamp_to_mupix0_3" SITE "N23"; +LOCATE COMP "timestamp_to_mupix0_4" SITE "K19"; +LOCATE COMP "timestamp_to_mupix0_5" SITE "P23"; +LOCATE COMP "timestamp_to_mupix0_6" SITE "L25"; +LOCATE COMP "timestamp_to_mupix0_7" SITE "P21"; +DEFINE PORT GROUP "timestamp_to_mupix0_group" "timestamp_to_mupix0*"; +IOBUF GROUP "timestamp_to_mupix0_group" IO_TYPE=LVCMOS25; + + +LOCATE COMP "ldpix_to_mupix0" SITE "L20"; +IOBUF PORT "ldpix_to_mupix0" IO_TYPE=LVCMOS25 ; +LOCATE COMP "ldcol_to_mupix0" SITE "M23"; +IOBUF PORT "ldcol_to_mupix0" IO_TYPE=LVCMOS25 ; +LOCATE COMP "rdcol_to_mupix0" SITE "L5"; +IOBUF PORT "rdcol_to_mupix0" IO_TYPE=LVCMOS25 ; +LOCATE COMP "pulldown_to_mupix0" SITE "D3"; +IOBUF PORT "pulldown_to_mupix0" IO_TYPE=LVCMOS25 ; +LOCATE COMP "priout_from_mupix0" SITE "L6"; +IOBUF PORT "priout_from_mupix0" IO_TYPE=LVCMOS25 ; + + +#Mupix 1 +LOCATE COMP "fpga_led_to_board1_0" SITE "G26"; +LOCATE COMP "fpga_led_to_board1_1" SITE "F26"; +LOCATE COMP "fpga_led_to_board1_2" SITE "H26"; +LOCATE COMP "fpga_led_to_board1_3" SITE "H25"; +DEFINE PORT GROUP "fpga_led1_group" "fpga_led_to_board1*"; +IOBUF GROUP "fpga_led1_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "fpga_aux_to_board1_0" SITE "AE25"; +LOCATE COMP "fpga_aux_to_board1_1" SITE "AE24"; +LOCATE COMP "fpga_aux_to_board1_2" SITE "W23"; +LOCATE COMP "fpga_aux_to_board1_3" SITE "AF24"; +LOCATE COMP "fpga_aux_to_board1_4" SITE "AA25"; +LOCATE COMP "fpga_aux_to_board1_5" SITE "W22"; +LOCATE COMP "fpga_aux_to_board1_6" SITE "AA26"; +LOCATE COMP "fpga_aux_to_board1_7" SITE "Y24"; +LOCATE COMP "fpga_aux_to_board1_8" SITE "W21"; +LOCATE COMP "fpga_aux_to_board1_9" SITE "W20"; +DEFINE PORT GROUP "fpga_aux1_group" "fpga_aux_to_board1*"; +IOBUF GROUP "fpga_aux01_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "testpulse2_to_board1" SITE "K23"; +LOCATE COMP "testpulse1_to_board1" SITE "K22"; +IOBUF PORT "testpulse2_to_board1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "testpulse1_to_board1" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "spi_din_to_board1" SITE "Y22"; +LOCATE COMP "spi_ld_to_board1" SITE "AD24"; +LOCATE COMP "spi_clk_to_board1" SITE "AA22"; +IOBUF PORT "spi_din_to_board1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "spi_ld_to_board1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "spi_clk_to_board1" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "hbus_from_mupix1" SITE "F25"; +IOBUF PORT "hbus_from_mupix1" IO_TYPE=LVCMOS25 ; +LOCATE COMP "sout_d_from_mupix1" SITE "AC26"; +IOBUF PORT "sout_d_from_mupix1" IO_TYPE=LVCMOS25 ; +LOCATE COMP "sout_c_from_mupix1" SITE "AC25"; +IOBUF PORT "sout_c_from_mupix1" IO_TYPE=LVCMOS25 ; +LOCATE COMP "sin_to_mupix1" SITE "T1"; +IOBUF PORT "sin_to_mupix1" IO_TYPE=LVCMOS25 ; +LOCATE COMP "ck_d_to_mupix1" SITE "AB24"; +IOBUF PORT "ck_d_to_mupix1" IO_TYPE=LVCMOS25 ; +LOCATE COMP "ld_c_to_mupix1" SITE "Y20"; +IOBUF PORT "ld_c_to_mupix1" IO_TYPE=LVCMOS25 ; +LOCATE COMP "ck_c_to_mupix1" SITE "AC24"; +IOBUF PORT "ck_c_to_mupix1" IO_TYPE=LVCMOS25 ; + + +#MuPix Readout +LOCATE COMP "rowaddr_from_mupix1_0" SITE "R25"; +LOCATE COMP "rowaddr_from_mupix1_1" SITE "T25"; +LOCATE COMP "rowaddr_from_mupix1_2" SITE "T26"; +LOCATE COMP "rowaddr_from_mupix1_3" SITE "V21"; +LOCATE COMP "rowaddr_from_mupix1_4" SITE "G5"; +LOCATE COMP "rowaddr_from_mupix1_5" SITE "C3"; +DEFINE PORT GROUP "rowaddr_from_mupix1_group" "rowaddr_from_mupix1*"; +IOBUF GROUP "rowaddr_from_mupix1_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "coladdr_from_mupix1_0" SITE "R22"; +LOCATE COMP "coladdr_from_mupix1_1" SITE "L26"; +LOCATE COMP "coladdr_from_mupix1_2" SITE "P22"; +LOCATE COMP "coladdr_from_mupix1_3" SITE "R26"; +LOCATE COMP "coladdr_from_mupix1_4" SITE "T24"; +LOCATE COMP "coladdr_from_mupix1_5" SITE "V22"; +DEFINE PORT GROUP "coladdr_from_mupix1_group" "coladdr_from_mupix1*"; +IOBUF GROUP "coladdr_from_mupix1_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "timestamp_from_mupix1_0" SITE "U3"; +LOCATE COMP "timestamp_from_mupix1_1" SITE "R2"; +LOCATE COMP "timestamp_from_mupix1_2" SITE "P3"; +LOCATE COMP "timestamp_from_mupix1_3" SITE "P6"; +LOCATE COMP "timestamp_from_mupix1_4" SITE "N6"; +LOCATE COMP "timestamp_from_mupix1_5" SITE "AC3"; +LOCATE COMP "timestamp_from_mupix1_6" SITE "AC1"; +LOCATE COMP "timestamp_from_mupix1_7" SITE "AA2"; +DEFINE PORT GROUP "timestamp_from_mupix1_group" "timestamp_from_mupix1*"; +IOBUF GROUP "timestamp_from_mupix1_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "timestamp_to_mupix1_0" SITE "P5"; +LOCATE COMP "timestamp_to_mupix1_1" SITE "N5"; +LOCATE COMP "timestamp_to_mupix1_2" SITE "AC2"; +LOCATE COMP "timestamp_to_mupix1_3" SITE "AB1"; +LOCATE COMP "timestamp_to_mupix1_4" SITE "AA1"; +LOCATE COMP "timestamp_to_mupix1_5" SITE "W7"; +LOCATE COMP "timestamp_to_mupix1_6" SITE "Y5"; +LOCATE COMP "timestamp_to_mupix1_7" SITE "V6"; +DEFINE PORT GROUP "timestamp_to_mupix1_group" "timestamp_to_mupix1*"; +IOBUF GROUP "timestamp_to_mupix1_group" IO_TYPE=LVCMOS25; + + +LOCATE COMP "ldpix_to_mupix1" SITE "T2"; +IOBUF PORT "ldpix_to_mupix1" IO_TYPE=LVCMOS25 ; +LOCATE COMP "ldcol_to_mupix1" SITE "N3"; +IOBUF PORT "ldcol_to_mupix1" IO_TYPE=LVCMOS25 ; +LOCATE COMP "rdcol_to_mupix1" SITE "J4"; +IOBUF PORT "rdcol_to_mupix1" IO_TYPE=LVCMOS25 ; +LOCATE COMP "pulldown_to_mupix1" SITE "L3"; +IOBUF PORT "pulldown_to_mupix1" IO_TYPE=LVCMOS25 ; +LOCATE COMP "priout_from_mupix1" SITE "J3"; +IOBUF PORT "priout_from_mupix1" IO_TYPE=LVCMOS25 ; diff --git a/mupix/sources/BlockMemory.vhd b/mupix/sources/BlockMemory.vhd index 7d80df6..e0a6116 100644 --- a/mupix/sources/BlockMemory.vhd +++ b/mupix/sources/BlockMemory.vhd @@ -45,7 +45,7 @@ end BlockMemory; architecture Behavioral of BlockMemory is type memory_type is array ((2**AddressWidth) - 1 downto 0) of std_logic_vector(DataWidth - 1 downto 0); - signal memory : memory_type; + signal memory : memory_type := (others => (others => '0')); begin diff --git a/mupix/sources/EventBuffer.vhd b/mupix/sources/EventBuffer.vhd index 99d7666..04ade9e 100644 --- a/mupix/sources/EventBuffer.vhd +++ b/mupix/sources/EventBuffer.vhd @@ -46,10 +46,13 @@ end eventbuffer; architecture behavioral of eventbuffer is + constant fifo_depth : integer := 12; + --response to fee signal fee_data_int : std_logic_vector(31 downto 0) := (others => '0'); signal fee_data_write_int : std_logic := '0'; signal fee_data_finished_int : std_logic := '0'; + signal fee_data_write_f : std_logic := '0'; --fifo signals signal fifo_reset : std_logic := '0'; @@ -57,7 +60,7 @@ architecture behavioral of eventbuffer is signal fifo_empty : std_logic; signal fifo_write : std_logic := '0'; signal fifo_status : std_logic_vector(31 downto 0) := (others => '0'); - signal fifo_write_ctr : std_logic_vector(10 downto 0) := (others => '0'); + signal fifo_write_ctr : std_logic_vector(fifo_depth - 1 downto 0) := (others => '0'); signal fifo_data_in : std_logic_vector(31 downto 0) := (others => '0'); signal fifo_data_out : std_logic_vector(31 downto 0) := (others => '0'); signal fifo_read_enable : std_logic := '0'; @@ -71,9 +74,10 @@ architecture behavioral of eventbuffer is signal fifo_reading_s : std_logic := '0'; signal fifo_read_done_s : std_logic := '0'; signal fifo_read_busy_s : std_logic := '0'; + signal slv_fifo_reset : std_logic := '0'; --fifo fast readout to trb data channel - type fifo_read_f_states is (idle, wait_for_data,flush_data, done); + type fifo_read_f_states is (idle, wait_for_data,flush_data, lastword, done); signal fifo_read_f_fsm : fifo_read_f_states := idle; signal fifo_read_f : std_logic := '0'; signal fifo_read_busy_f : std_logic := '0'; @@ -98,7 +102,7 @@ begin -- behavioral fifo_1: entity work.fifo generic map ( - addr_wd => 11, + addr_wd => fifo_depth, word_wd => 32) port map ( Din => fifo_data_in, @@ -112,7 +116,7 @@ begin -- behavioral CLK => clk); fifo_read_enable <= fifo_read_s or fifo_read_f; - fifo_reset <= clear_buffer_in; + fifo_reset <= clear_buffer_in or slv_fifo_reset; fifo_write_handler : process(clk) begin -- process fifo_write_handler @@ -127,8 +131,15 @@ begin -- behavioral end process fifo_write_handler; ------------------------------------------------------------ - --fifo readout using trb slow control channel + --fifo readout to ipu channel ------------------------------------------------------------ + fifo_data_write_ff: process (clk) is + begin -- process fifo_data_write_ff + if rising_edge(clk) then + fee_data_write_f <= fee_data_write_int; + end if; + end process fifo_data_write_ff; + fifo_data_read_f: process is begin -- process fifo_data_read_f wait until rising_edge(clk); @@ -163,10 +174,12 @@ begin -- behavioral fee_data_write_int <= '1'; if fifo_empty = '1' then fifo_read_f <= '0'; - fifo_read_f_fsm <= done; - else - fifo_read_f_fsm <= flush_data; + fifo_read_f_fsm <= lastword; end if; + when lastword => + fifo_read_f_fsm <= done; + fifo_read_busy_f <= '1'; + fee_data_int <= fifo_data_out; when done => fee_data_finished_int <= '1'; fifo_read_f_fsm <= idle; @@ -204,7 +217,7 @@ begin -- behavioral end if; when wait1 => fifo_read_busy_s <= '1'; - fifo_read_s_fsm <= wait2; + fifo_read_s_fsm <= done; when wait2 => fifo_read_busy_s <= '1'; fifo_read_s_fsm <= done; @@ -225,8 +238,8 @@ begin -- behavioral ----------------------------------------------------------------------------- fifo_status(1 downto 0) <= fifo_empty & fifo_full; - fifo_status(12 downto 2) <= fifo_write_ctr; - fifo_status(31 downto 13) <= (others => '0'); + fifo_status((fifo_depth - 1) + 2 downto 2) <= fifo_write_ctr; + fifo_status(31 downto fifo_depth + 2) <= (others => '0'); slv_bus_handler : process(clk) begin @@ -236,6 +249,7 @@ begin -- behavioral slv_no_more_data_out <= '0'; slv_unknown_addr_out <= '0'; fifo_start_read <= '0'; + slv_fifo_reset <= '0'; if fifo_reading_s = '1' then if (fifo_read_done_s = '0') then @@ -252,14 +266,21 @@ begin -- behavioral end if; elsif slv_write_in = '1' then - slv_unknown_addr_out <= '1'; + case SLV_ADDR_IN is + when x"0303" => + slv_fifo_reset <= '1'; + slv_ack_out <= '1'; + when others => + slv_unknown_addr_out <= '1'; + end case; + elsif slv_read_in = '1' then case slv_addr_in is when x"0300" => slv_data_out <= fifo_status; slv_ack_out <= '1'; when x"0301" => - slv_data_out(10 downto 0) <= fifo_write_ctr; + slv_data_out(fifo_depth - 1 downto 0) <= fifo_write_ctr; slv_ack_out <= '1'; when x"0302" => fifo_start_read <= '1'; @@ -275,7 +296,7 @@ begin -- behavioral --map output signals fee_data_out <= fee_data_int; - fee_data_write_out <= fee_data_write_int; + fee_data_write_out <= fee_data_write_f; fee_data_finished_out <= fee_data_finished_int; end behavioral; diff --git a/mupix/sources/FiFo.vhd b/mupix/sources/FiFo.vhd index 69f0b08..a4b00a5 100644 --- a/mupix/sources/FiFo.vhd +++ b/mupix/sources/FiFo.vhd @@ -27,31 +27,50 @@ architecture fifo_arch of fifo is -- decl signal wrcnt : unsigned (addr_wd-1 downto 0) := (others => '0'); signal rdcnt : unsigned (addr_wd-1 downto 0) := (others => '0'); + signal din_int : unsigned (word_wd-1 downto 0) := (others => '0'); type memory_type is array(0 to (2**addr_wd)-1) of unsigned(word_wd-1 downto 0); signal memory : memory_type; + signal memory_address : unsigned(addr_wd-1 downto 0) := (others => '0'); + signal full_loc : std_logic; signal empty_loc : std_logic; + signal write_int : std_logic; begin - process + + blockmemory: process(clk) begin - wait until rising_edge(CLK); - if Reset = '1' then - rdcnt <= (others => '0'); - wrcnt <= (others => '0'); - else - if (Wr = '1' and full_loc = '0') then - memory(to_integer(wrcnt)) <= unsigned(Din); - wrcnt <= wrcnt+1; - end if; + if rising_edge(clk) then + if (write_int = '1') then + memory(to_integer(memory_address)) <= din_int; + end if; + dout <= std_logic_vector(memory(to_integer(memory_address))); + end if; + end process blockmemory; - if (Rd = '1' and empty_loc = '0') then - Dout <= std_logic_vector(memory(to_integer(rdcnt))); - rdcnt <= rdcnt+1; + AddressMux: process (clk) + begin -- process AddressMux + if rising_edge(clk) then + if Reset = '1' then + rdcnt <= (others => '0'); + wrcnt <= (others => '0'); + else + if Wr = '1' and full_loc = '0' then + memory_address <= wrcnt; + write_int <= '1'; + din_int <= unsigned(Din); + wrcnt <= wrcnt + 1; + elsif (Rd = '1' and empty_loc = '0') then + memory_address <= rdcnt ; + rdcnt <= rdcnt + 1; + else + write_int <= '0'; + memory_address <= (others => '0'); + end if; end if; end if; - end process; - + end process AddressMux; + full_loc <= '1' when rdcnt = wrcnt+1 else '0'; empty_loc <= '1' when rdcnt = wrcnt else '0'; Full <= full_loc; diff --git a/mupix/sources/HitbusHistogram.vhd b/mupix/sources/HitbusHistogram.vhd index 6ac6b7d..5327963 100644 --- a/mupix/sources/HitbusHistogram.vhd +++ b/mupix/sources/HitbusHistogram.vhd @@ -193,6 +193,7 @@ begin --0x0802: Last Latency Value --0x0803: Read Histograms --0x0804: ReadCounter + --0x0805: snapshot of hitbus ----------------------------------------------------------------------------- SLV_BUS_HANDLER : process(clk) begin -- process SLV_BUS_HANDLER @@ -220,7 +221,7 @@ begin SLV_ACK_OUT <= '1'; when x"0801" => SLV_DATA_OUT(31 downto 16) <= (others => '0'); - SLV_DATA_OUT(HistogramRange - 1 downto 0) <= std_logic_vector(hitbus_counter); + SLV_DATA_OUT(HistogramRange - 1 downto 0) <= hitbus_HistoWrAddr; SLV_ACK_OUT <= '1'; when x"0802" => SLV_DATA_OUT(31 downto 16) <= (others => '0'); @@ -233,6 +234,9 @@ begin when x"0804" => SLV_DATA_OUT(HistogramRange - 1 downto 0) <= std_logic_vector(readcounter); SLV_ACK_OUT <= '1'; + when x"0805" => + SLV_DATA_OUT(0) <= hitbus; + SLV_ACK_OUT <= '1'; when others => SLV_UNKNOWN_ADDR_OUT <= '1'; end case; diff --git a/mupix/sources/MuPix3_board.vhd b/mupix/sources/MuPix3_board.vhd index 60ab42e..c3a44c4 100644 --- a/mupix/sources/MuPix3_board.vhd +++ b/mupix/sources/MuPix3_board.vhd @@ -24,7 +24,7 @@ entity MuPix3_Board is priout_from_mupix : in std_logic; sout_c_from_mupix : in std_logic; sout_d_from_mupix : in std_logic; - hbus_form_mupix : in std_logic; + hbus_from_mupix : in std_logic; fpga_aux_from_board : in std_logic_vector(9 downto 0); ldpix_to_mupix : out std_logic; ldcol_to_mupix : out std_logic; @@ -115,7 +115,7 @@ architecture Behavioral of MuPix3_Board is signal priout_from_mupix_sync : std_logic; signal sout_c_from_mupix_sync : std_logic; signal sout_d_from_mupix_sync : std_logic; - signal hbus_form_mupix_sync : std_logic; + signal hbus_from_mupix_sync : std_logic; signal fpga_aux_from_board_sync : std_logic_vector(9 downto 0); @@ -195,7 +195,7 @@ begin -- Behavioral priout_from_mupix => priout_from_mupix, sout_c_from_mupix => sout_c_from_mupix, sout_d_from_mupix => sout_d_from_mupix, - hbus_form_mupix => hbus_form_mupix, + hbus_from_mupix => hbus_from_mupix, fpga_aux_from_board => fpga_aux_from_board, timestamp_from_mupix_sync => timestamp_from_mupix_sync, rowaddr_from_mupix_sync => rowaddr_from_mupix_sync, @@ -203,7 +203,7 @@ begin -- Behavioral priout_from_mupix_sync => priout_from_mupix_sync, sout_c_from_mupix_sync => sout_c_from_mupix_sync, sout_d_from_mupix_sync => sout_d_from_mupix_sync, - hbus_form_mupix_sync => hbus_form_mupix_sync, + hbus_from_mupix_sync => hbus_from_mupix_sync, fpga_aux_from_board_sync => fpga_aux_from_board_sync, SLV_READ_IN => slv_read(7), SLV_WRITE_IN => slv_write(7), @@ -296,11 +296,11 @@ begin -- Behavioral HitbusHistogram_1 : HitbusHistogram generic map ( - HistogramRange => 8) + HistogramRange => 10) port map ( clk => clk, trigger => fpga_aux_to_board(0), - hitbus => hbus_form_mupix_sync, + hitbus => hbus_from_mupix_sync, SLV_READ_IN => slv_read(4), SLV_WRITE_IN => slv_write(4), SLV_DATA_OUT => slv_data_rd(4*32+31 downto 4*32), diff --git a/mupix/sources/MuPix3_boardinterface.vhd b/mupix/sources/MuPix3_boardinterface.vhd index 3f6bf79..b6bdb40 100644 --- a/mupix/sources/MuPix3_boardinterface.vhd +++ b/mupix/sources/MuPix3_boardinterface.vhd @@ -21,7 +21,7 @@ entity board_interface is priout_from_mupix : in std_logic; sout_c_from_mupix : in std_logic; sout_d_from_mupix : in std_logic; - hbus_form_mupix : in std_logic; + hbus_from_mupix : in std_logic; fpga_aux_from_board : in std_logic_vector(9 downto 0); --synced (and inverted) signals timestamp_from_mupix_sync : out std_logic_vector(7 downto 0); @@ -30,7 +30,7 @@ entity board_interface is priout_from_mupix_sync : out std_logic; sout_c_from_mupix_sync : out std_logic; sout_d_from_mupix_sync : out std_logic; - hbus_form_mupix_sync : out std_logic; + hbus_from_mupix_sync : out std_logic; fpga_aux_from_board_sync : out std_logic_vector(9 downto 0); --Trb Slv-Bus SLV_READ_IN : in std_logic; @@ -63,7 +63,7 @@ begin sout_c_from_mupix_sync <= not sout_c_from_mupix; sout_d_from_mupix_sync <= not sout_d_from_mupix; priout_from_mupix_sync <= priout_from_mupix; --is inverted on the chip - hbus_form_mupix_sync <= hbus_form_mupix; + hbus_from_mupix_sync <= hbus_from_mupix; fpga_aux_from_board_sync <= fpga_aux_from_board; else timestamp_from_mupix_sync <= timestamp_from_mupix; @@ -72,7 +72,7 @@ begin sout_c_from_mupix_sync <= sout_c_from_mupix; sout_d_from_mupix_sync <= sout_d_from_mupix; priout_from_mupix_sync <= not priout_from_mupix; --is inverted on the chip - hbus_form_mupix_sync <= not hbus_form_mupix; + hbus_from_mupix_sync <= not hbus_from_mupix; fpga_aux_from_board_sync <= not fpga_aux_from_board; end if; end process; diff --git a/mupix/sources/MuPix3_interface.vhd b/mupix/sources/MuPix3_interface.vhd index 66163c5..9e569ca 100644 --- a/mupix/sources/MuPix3_interface.vhd +++ b/mupix/sources/MuPix3_interface.vhd @@ -58,14 +58,16 @@ architecture RTL of mupix_interface is - signal delcounter : unsigned(3 downto 0) := (others => '0'); - signal delaycounters : std_logic_vector(31 downto 0) := (others => '0'); + signal delcounter : unsigned(7 downto 0) := (others => '0'); + signal delaycounters1 : std_logic_vector(31 downto 0) := (others => '0'); + signal delaycounters2 : std_logic_vector(31 downto 0) := (others => '0'); signal pauseregister : std_logic_vector(31 downto 0) := (others => '0'); signal pausecounter : unsigned (31 downto 0) := (others => '0'); signal ro_busy_int : std_logic := '0'; signal graycount : std_logic_vector(7 downto 0) := (others => '0'); signal eventcounter : unsigned(31 downto 0) := (others => '0'); signal hitcounter : unsigned(10 downto 0) := (others => '0'); + signal graycounter_clkdiv_counter : std_logic_vector(31 downto 0) := (others => '0'); signal triggering : std_logic := '0'; signal busy_r : std_logic := '0'; @@ -105,9 +107,11 @@ begin --x0021: Readout Controlbits (manual readout) --x0022: Timestamp Controlbits --x0023: Hit Generator - --x0024: Delay Counters + --x0024: Delay Counters 1 --x0025: EventCounter --x0026: Pause Register + --x0027: Delay Counters 2 + --x0028: Divider for graycounter clock ----------------------------------------------------------------------------- SLV_HANDLER : process(clk) @@ -134,7 +138,7 @@ begin SLV_DATA_OUT <= generatehitswait; SLV_ACK_OUT <= '1'; when x"0024" => - SLV_DATA_OUT <= delaycounters; + SLV_DATA_OUT <= delaycounters1; SLV_ACK_OUT <= '1'; when x"0025" => SLV_DATA_OUT <= std_logic_vector(eventcounter); @@ -142,6 +146,12 @@ begin when x"0026" => SLV_DATA_OUT <= pauseregister; SLV_ACK_OUT <= '1'; + when x"0027" => + SLV_DATA_OUT <= delaycounters2; + SLV_ACK_OUT <= '1'; + when x"0028" => + SLV_DATA_OUT <= graycounter_clkdiv_counter; + SLV_ACK_OUT <= '1'; when others => SLV_UNKNOWN_ADDR_OUT <= '1'; end case; @@ -163,11 +173,17 @@ begin generatehitswait <= SLV_DATA_IN; SLV_ACK_OUT <= '1'; when x"0024" => - delaycounters <= SLV_DATA_IN; + delaycounters1 <= SLV_DATA_IN; SLV_ACK_OUT <= '1'; when x"0026" => pauseregister <= SLV_DATA_IN; SLV_ACK_OUT <= '1'; + when x"0027" => + delaycounters2 <= SLV_DATA_IN; + SLV_ACK_OUT <= '1'; + when x"0028" => + graycounter_clkdiv_counter <= SLV_DATA_IN; + SLV_ACK_OUT <= '1'; when others => SLV_UNKNOWN_ADDR_OUT <= '1'; end case; @@ -289,15 +305,15 @@ begin elsif(continousread = '1' or readnow = '1' or(triggering = '1' and trigger_ext = '1' and generatetriggeredhits = '0')) then state <= loadpix; ldpix <= '1'; - delcounter <= unsigned(delaycounters(3 downto 0)); + delcounter <= unsigned(delaycounters1(7 downto 0)); eventcounter <= eventcounter + 1; elsif(generatetriggeredhits = '1' and trigger_ext = '1') then state <= hitgenerator; - delcounter <= "0100"; + delcounter <= "00000100"; eventcounter <= eventcounter + 1; elsif(generatehit = '1' or generatehits = '1') then state <= hitgenerator; - delcounter <= "0100"; + delcounter <= "00000100"; eventcounter <= eventcounter + 1; else state <= waiting; @@ -323,47 +339,47 @@ begin delcounter <= delcounter - 1; memwren <= '0'; state <= loadpix; - if(delcounter = "0100") then -- write event header + if(delcounter = "00000100") then -- write event header memdata <= "11111010101111101010101110111010"; --0xFABEABBA memwren <= '1'; - elsif(delcounter = "0011") then -- write event counter + elsif(delcounter = "00000011") then -- write event counter memdata <= std_logic_vector(eventcounter); memwren <= '1'; end if; - if(delcounter = "0000") then + if(delcounter = "00000000") then state <= pulld; pulldown <= '1'; - delcounter <= unsigned(delaycounters(7 downto 4)); + delcounter <= unsigned(delaycounters1(15 downto 8)); end if; endofevent <= '0'; when pulld => testoutro(3) <= '1'; memwren <= '0'; - if unsigned(delaycounters(7 downto 4)) = delcounter then + if unsigned(delaycounters1(15 downto 8)) = delcounter then pulldown <= '0'; end if; delcounter <= delcounter - 1; state <= pulld; - if(delcounter = "0000") then + if(delcounter = "00000000") then state <= loadcol; ldcol <= '1'; - delcounter <= unsigned(delaycounters(11 downto 8)); + delcounter <= unsigned(delaycounters1(23 downto 16)); end if; endofevent <= '0'; when loadcol => testoutro(4) <= '1'; memwren <= '0'; - if(delcounter = unsigned(delaycounters(11 downto 8))) then + if(delcounter = unsigned(delaycounters1(23 downto 16))) then ldcol <= '0'; end if; delcounter <= delcounter - 1; state <= loadcol; endofevent <= '0'; - if(delcounter = "0000" and priout = '1') then + if(delcounter = "00000000" and priout = '1') then state <= readcol; rdcol <= '1'; - delcounter <= unsigned(delaycounters(15 downto 12)); - elsif(delcounter = "0000") then + delcounter <= unsigned(delaycounters1(31 downto 24)); + elsif(delcounter = "00000000") then -- end of event memwren <= '1'; memdata <= "10111110111011111011111011101111"; --0xBEEFBEEF @@ -372,43 +388,43 @@ begin end if; when readcol => testoutro(5) <= '1'; - if(delcounter = unsigned(delaycounters(15 downto 12)) - unsigned(delaycounters(23 downto 20))) then + if(delcounter = unsigned(delaycounters1(31 downto 24)) - unsigned(delaycounters2(15 downto 8))) then rdcol <= '0'; end if; delcounter <= delcounter - 1; memwren <= '0'; state <= readcol; endofevent <= '0'; - if (std_logic_vector(delcounter) = delaycounters(27 downto 24)) then + if (std_logic_vector(delcounter) = delaycounters2(23 downto 16)) then priout_reg <= priout; end if; - if(std_logic_vector(delcounter) = delaycounters(31 downto 28)) then + if(std_logic_vector(delcounter) = delaycounters2(31 downto 24)) then memdata <= "111100001111" & hit_col & hit_row & hit_time; --0xF0F memwren <= '1'; hitcounter <= hitcounter + 1; state <= readcol; - elsif(delcounter = "0000" and hitcounter = "11111111111") then + elsif(delcounter = "00000000" and hitcounter = "11111111111") then -- 2048 hits - this makes no sense -- force end of event memwren <= '1'; memdata <= "10111110111011111011111011101111"; --0xBEEFBEEF endofevent <= '1'; state <= pause; - elsif(delcounter = "0000" and (priout = '1' or (delaycounters(27 downto 24) /= "0000" and priout_reg = '1'))) then + elsif(delcounter = "00000000" and (priout = '1' or (delaycounters2(23 downto 16) /= "00000000" and priout_reg = '1'))) then state <= readcol; rdcol <= '1'; - delcounter <= unsigned(delaycounters(15 downto 12)); - elsif(delcounter = "0000") then + delcounter <= unsigned(delaycounters1(31 downto 24)); + elsif(delcounter = "00000000") then state <= pulld; pulldown <= '1'; - delcounter <= unsigned(delaycounters(19 downto 16)); + delcounter <= unsigned(delaycounters2(7 downto 0)); end if; when hitgenerator => ro_busy_int <= '1'; testoutro(6) <= '1'; state <= hitgenerator; - if(delcounter = "0100") then -- write event header + if(delcounter = "00000100") then -- write event header state <= hitgenerator; memdata <= "11111010101111101010101110111010"; --0xFABEABBA memwren <= '1'; @@ -419,24 +435,24 @@ begin gen_hit_time <= (others => '0'); delcounter <= delcounter - 1; endofevent <= '0'; - elsif(delcounter = "0011") then -- write event counter + elsif(delcounter = "00000011") then -- write event counter state <= hitgenerator; memdata <= std_logic_vector(eventcounter); memwren <= '1'; delcounter <= delcounter - 1; endofevent <= '0'; - elsif(delcounter = "0010") then + elsif(delcounter = "00000010") then state <= hitgenerator; memwren <= '0'; delcounter <= delcounter - 1; endofevent <= '0'; - elsif(delcounter = "0001") then -- write trigger number + elsif(delcounter = "00000001") then -- write trigger number state <= hitgenerator; memdata <= (others => '0'); --empty trigger number memwren <= '1'; delcounter <= delcounter - 1; endofevent <= '0'; - elsif(delcounter = "0000" and ngeneratehitscounter > "0000000000000000") then + elsif(delcounter = "00000000" and ngeneratehitscounter > "0000000000000000") then state <= hitgenerator; delcounter <= delcounter; ngeneratehitscounter <= ngeneratehitscounter - 1; @@ -448,13 +464,13 @@ begin memdata <= "111100001111" & "0" & gen_hit_col(4 downto 0) & gen_hit_row & graycount; --0xF0F memwren <= '1'; endofevent <= '0'; - elsif(delcounter = "0000" and ngeneratehitscounter = "0000000000000000" and generatehits = '0') then + elsif(delcounter = "00000000" and ngeneratehitscounter = "0000000000000000" and generatehits = '0') then state <= waiting; -- end of event memwren <= '1'; memdata <= "10111110111011111011111011101111"; --0xBEEFBEEF endofevent <= '1'; - elsif(delcounter = "0000" and ngeneratehitscounter = "0000000000000000" and generatehits = '1') then + elsif(delcounter = "00000000" and ngeneratehitscounter = "0000000000000000" and generatehits = '1') then state <= hitgeneratorwait; -- end of event memwren <= '1'; @@ -475,7 +491,7 @@ begin generatehitswaitcounter <= generatehitswaitcounter - 1; if(to_integer(generatehitswaitcounter) = 0)then state <= hitgenerator; - delcounter <= "0100"; + delcounter <= "00000100"; eventcounter <= eventcounter + 1; end if; @@ -511,6 +527,7 @@ begin clk => clk, reset => resetgraycounter, sync_reset => timestampcontrolbits(9), + clk_divcounter => graycounter_clkdiv_counter(7 downto 0), counter => graycount ); diff --git a/mupix/sources/mupix_components.vhd b/mupix/sources/mupix_components.vhd index be8bfc9..01dd23b 100644 --- a/mupix/sources/mupix_components.vhd +++ b/mupix/sources/mupix_components.vhd @@ -16,7 +16,7 @@ package mupix_components is priout_from_mupix : in std_logic; sout_c_from_mupix : in std_logic; sout_d_from_mupix : in std_logic; - hbus_form_mupix : in std_logic; + hbus_from_mupix : in std_logic; fpga_aux_from_board : in std_logic_vector(9 downto 0); ldpix_to_mupix : out std_logic; ldcol_to_mupix : out std_logic; @@ -152,6 +152,7 @@ package mupix_components is clk : in std_logic; reset : in std_logic; sync_reset : in std_logic; + clk_divcounter : in std_logic_vector(7 downto 0); counter : out std_logic_vector(COUNTWIDTH-1 downto 0)); end component; @@ -263,7 +264,7 @@ package mupix_components is priout_from_mupix : in std_logic; sout_c_from_mupix : in std_logic; sout_d_from_mupix : in std_logic; - hbus_form_mupix : in std_logic; + hbus_from_mupix : in std_logic; fpga_aux_from_board : in std_logic_vector(9 downto 0); timestamp_from_mupix_sync : out std_logic_vector(7 downto 0); rowaddr_from_mupix_sync : out std_logic_vector(5 downto 0); diff --git a/mupix/trb3_periph.vhd b/mupix/trb3_periph.vhd index 6fe40a2..c11f8e9 100644 --- a/mupix/trb3_periph.vhd +++ b/mupix/trb3_periph.vhd @@ -44,31 +44,57 @@ entity trb3_periph is --------------------------------------------------------------------------- -- BEGIN SenorBoard MuPix --------------------------------------------------------------------------- - --Connections to MuPix 3 - timestamp_from_mupix : in std_logic_vector(7 downto 0); - rowaddr_from_mupix : in std_logic_vector(5 downto 0); - coladdr_from_mupix : in std_logic_vector(5 downto 0); - priout_from_mupix : in std_logic; - sout_c_from_mupix : in std_logic; - sout_d_from_mupix : in std_logic; - hbus_form_mupix : in std_logic; - fpga_aux_from_board : in std_logic_vector(9 downto 0); - ldpix_to_mupix : out std_logic; - ldcol_to_mupix : out std_logic; - timestamp_to_mupix : out std_logic_vector(7 downto 0); - rdcol_to_mupix : out std_logic; - pulldown_to_mupix : out std_logic; - sin_to_mupix : out std_logic; - ck_d_to_mupix : out std_logic; - ck_c_to_mupix : out std_logic; - ld_c_to_mupix : out std_logic; - testpulse1_to_board : out std_logic; - testpulse2_to_board : out std_logic; - spi_din_to_board : out std_logic; - spi_clk_to_board : out std_logic; - spi_ld_to_board : out std_logic; - fpga_led_to_board : out std_logic_vector(3 downto 0); - fpga_aux_to_board : out std_logic_vector(9 downto 0); + --Connections to Sensorboard 0 + timestamp_from_mupix0 : in std_logic_vector(7 downto 0); + rowaddr_from_mupix0 : in std_logic_vector(5 downto 0); + coladdr_from_mupix0 : in std_logic_vector(5 downto 0); + priout_from_mupix0 : in std_logic; + sout_c_from_mupix0 : in std_logic; + sout_d_from_mupix0 : in std_logic; + hbus_from_mupix0 : in std_logic; + fpga_aux_from_board0 : in std_logic_vector(9 downto 0); + ldpix_to_mupix0 : out std_logic; + ldcol_to_mupix0 : out std_logic; + timestamp_to_mupix0 : out std_logic_vector(7 downto 0); + rdcol_to_mupix0 : out std_logic; + pulldown_to_mupix0 : out std_logic; + sin_to_mupix0 : out std_logic; + ck_d_to_mupix0 : out std_logic; + ck_c_to_mupix0 : out std_logic; + ld_c_to_mupix0 : out std_logic; + testpulse1_to_board0 : out std_logic; + testpulse2_to_board0 : out std_logic; + spi_din_to_board0 : out std_logic; + spi_clk_to_board0 : out std_logic; + spi_ld_to_board0 : out std_logic; + fpga_led_to_board0 : out std_logic_vector(3 downto 0); + fpga_aux_to_board0 : out std_logic_vector(9 downto 0); + + --Connections to Sensorboard 1 + timestamp_from_mupix1 : in std_logic_vector(7 downto 0); + rowaddr_from_mupix1 : in std_logic_vector(5 downto 0); + coladdr_from_mupix1 : in std_logic_vector(5 downto 0); + priout_from_mupix1 : in std_logic; + sout_c_from_mupix1 : in std_logic; + sout_d_from_mupix1 : in std_logic; + hbus_from_mupix1 : in std_logic; + fpga_aux_from_board1 : in std_logic_vector(9 downto 0); + ldpix_to_mupix1 : out std_logic; + ldcol_to_mupix1 : out std_logic; + timestamp_to_mupix1 : out std_logic_vector(7 downto 0); + rdcol_to_mupix1 : out std_logic; + pulldown_to_mupix1 : out std_logic; + sin_to_mupix1 : out std_logic; + ck_d_to_mupix1 : out std_logic; + ck_c_to_mupix1 : out std_logic; + ld_c_to_mupix1 : out std_logic; + testpulse1_to_board1 : out std_logic; + testpulse2_to_board1 : out std_logic; + spi_din_to_board1 : out std_logic; + spi_clk_to_board1 : out std_logic; + spi_ld_to_board1 : out std_logic; + fpga_led_to_board1 : out std_logic_vector(3 downto 0); + fpga_aux_to_board1 : out std_logic_vector(9 downto 0); --------------------------------------------------------------------------- @@ -126,6 +152,7 @@ architecture trb3_periph_arch of trb3_periph is --Constants constant REGIO_NUM_STAT_REGS : integer := 5; constant REGIO_NUM_CTRL_REGS : integer := 3; + constant NumberFEECards : integer := 2; attribute syn_keep : boolean; attribute syn_preserve : boolean; @@ -177,12 +204,12 @@ architecture trb3_periph_arch of trb3_periph is signal trg_spike_detected_i : std_logic; --Data channel - signal fee_trg_release_i : std_logic_vector(2-1 downto 0); - signal fee_trg_statusbits_i : std_logic_vector(2*32-1 downto 0); - signal fee_data_i : std_logic_vector(2*32-1 downto 0); - signal fee_data_write_i : std_logic_vector(2-1 downto 0); - signal fee_data_finished_i : std_logic_vector(2-1 downto 0); - signal fee_almost_full_i : std_logic_vector(2-1 downto 0); + signal fee_trg_release_i : std_logic_vector(NumberFEECards-1 downto 0); + signal fee_trg_statusbits_i : std_logic_vector(NumberFEECards*32-1 downto 0); + signal fee_data_i : std_logic_vector(NumberFEECards*32-1 downto 0); + signal fee_data_write_i : std_logic_vector(NumberFEECards-1 downto 0); + signal fee_data_finished_i : std_logic_vector(NumberFEECards-1 downto 0); + signal fee_almost_full_i : std_logic_vector(NumberFEECards-1 downto 0); --Slow Control channel signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); @@ -247,22 +274,28 @@ architecture trb3_periph_arch of trb3_periph is --FPGA Test signal time_counter : unsigned(31 downto 0); - - -- MuPix-FEE-Board Clocks - signal mu_clk50 : std_logic; - signal pll_lock_clk50 : std_logic; - -- MuPix Regio Bus - signal mu_regio_addr_in : std_logic_vector (15 downto 0); - signal mu_regio_data_in : std_logic_vector (31 downto 0); - signal mu_regio_data_out : std_logic_vector (31 downto 0); - signal mu_regio_read_enable_in : std_logic; - signal mu_regio_write_enable_in : std_logic; - signal mu_regio_timeout_in : std_logic; - signal mu_regio_dataready_out : std_logic; - signal mu_regio_write_ack_out : std_logic; - signal mu_regio_no_more_data_out : std_logic; - signal mu_regio_unknown_addr_out : std_logic; + signal mu_regio_addr_in_0 : std_logic_vector (15 downto 0); + signal mu_regio_data_in_0 : std_logic_vector (31 downto 0); + signal mu_regio_data_out_0 : std_logic_vector (31 downto 0); + signal mu_regio_read_enable_in_0 : std_logic; + signal mu_regio_write_enable_in_0 : std_logic; + signal mu_regio_timeout_in_0 : std_logic; + signal mu_regio_dataready_out_0 : std_logic; + signal mu_regio_write_ack_out_0 : std_logic; + signal mu_regio_no_more_data_out_0 : std_logic; + signal mu_regio_unknown_addr_out_0 : std_logic; + + signal mu_regio_addr_in_1 : std_logic_vector (15 downto 0); + signal mu_regio_data_in_1 : std_logic_vector (31 downto 0); + signal mu_regio_data_out_1 : std_logic_vector (31 downto 0); + signal mu_regio_read_enable_in_1 : std_logic; + signal mu_regio_write_enable_in_1 : std_logic; + signal mu_regio_timeout_in_1 : std_logic; + signal mu_regio_dataready_out_1 : std_logic; + signal mu_regio_write_ack_out_1 : std_logic; + signal mu_regio_no_more_data_out_1 : std_logic; + signal mu_regio_unknown_addr_out_1 : std_logic; @@ -365,7 +398,7 @@ begin CLOCK_FREQUENCY => 125, TIMING_TRIGGER_RAW => c_YES, --Configure data handler - DATA_INTERFACE_NUMBER => 1, --number of FEE Cards + DATA_INTERFACE_NUMBER => 2, --number of FEE Cards DATA_BUFFER_DEPTH => 13, --13 DATA_BUFFER_WIDTH => 32, DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024 @@ -409,7 +442,7 @@ begin TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i, TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i, - --Response from FEE, i.e. MuPix 3 + --Response from FEE, i.e. MuPix FEE_TRG_RELEASE_IN(0) => fee_trg_release_i(0), FEE_TRG_STATUSBITS_IN(0*32+31 downto 0*32) => fee_trg_statusbits_i(0*32+31 downto 0*32), FEE_DATA_IN(0*32+31 downto 0*32) => fee_data_i(0*32+31 downto 0*32), @@ -417,6 +450,13 @@ begin FEE_DATA_FINISHED_IN(0) => fee_data_finished_i(0), FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i(0), + FEE_TRG_RELEASE_IN(1) => fee_trg_release_i(1), + FEE_TRG_STATUSBITS_IN(1*32+31 downto 1*32) => fee_trg_statusbits_i(1*32+31 downto 1*32), + FEE_DATA_IN(1*32+31 downto 1*32) => fee_data_i(1*32+31 downto 1*32), + FEE_DATA_WRITE_IN(1) => fee_data_write_i(1), + FEE_DATA_FINISHED_IN(1) => fee_data_finished_i(1), + FEE_DATA_ALMOST_FULL_OUT(1) => fee_almost_full_i(1), + -- Slow Control Data Port REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 @@ -462,12 +502,6 @@ begin timing_trg_received_i <= TRIGGER_LEFT; --- fee_trg_release_i(1) <= '1'; --- fee_data_i(1*32+31 downto 1*32) <= (others => '1'); --- fee_trg_statusbits_i(1*32+31 downto 1*32) <= (others => '0'); --- fee_data_write_i(1) <= '0'; --- fee_data_finished_i(1) <= '1'; - --------------------------------------------------------------------------- -- AddOn --------------------------------------------------------------------------- @@ -477,14 +511,16 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 3, + PORT_NUMBER => 4, PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8000", + 3 => x"9000", others => x"0000"), PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 12, + 3 => 12, others => 0) ) port map( @@ -529,17 +565,29 @@ begin BUS_UNKNOWN_ADDR_IN(1) => '0', --Bus Handler (MuPix trb_net16_regio_bus_handler) - BUS_READ_ENABLE_OUT(2) => mu_regio_read_enable_in, - BUS_WRITE_ENABLE_OUT(2) => mu_regio_write_enable_in, - BUS_DATA_OUT(2*32+31 downto 2*32) => mu_regio_data_in, - BUS_ADDR_OUT(2*16+11 downto 2*16) => mu_regio_addr_in(11 downto 0), + BUS_READ_ENABLE_OUT(2) => mu_regio_read_enable_in_0, + BUS_WRITE_ENABLE_OUT(2) => mu_regio_write_enable_in_0, + BUS_DATA_OUT(2*32+31 downto 2*32) => mu_regio_data_in_0, + BUS_ADDR_OUT(2*16+11 downto 2*16) => mu_regio_addr_in_0(11 downto 0), BUS_ADDR_OUT(2*16+15 downto 2*16+12) => open, BUS_TIMEOUT_OUT(2) => open, - BUS_DATA_IN(2*32+31 downto 2*32) => mu_regio_data_out, - BUS_DATAREADY_IN(2) => mu_regio_dataready_out, - BUS_WRITE_ACK_IN(2) => mu_regio_write_ack_out, - BUS_NO_MORE_DATA_IN(2) => mu_regio_no_more_data_out, - BUS_UNKNOWN_ADDR_IN(2) => mu_regio_unknown_addr_out, + BUS_DATA_IN(2*32+31 downto 2*32) => mu_regio_data_out_0, + BUS_DATAREADY_IN(2) => mu_regio_dataready_out_0, + BUS_WRITE_ACK_IN(2) => mu_regio_write_ack_out_0, + BUS_NO_MORE_DATA_IN(2) => mu_regio_no_more_data_out_0, + BUS_UNKNOWN_ADDR_IN(2) => mu_regio_unknown_addr_out_0, + + BUS_READ_ENABLE_OUT(3) => mu_regio_read_enable_in_1, + BUS_WRITE_ENABLE_OUT(3) => mu_regio_write_enable_in_1, + BUS_DATA_OUT(3*32+31 downto 3*32) => mu_regio_data_in_1, + BUS_ADDR_OUT(3*16+11 downto 3*16) => mu_regio_addr_in_1(11 downto 0), + BUS_ADDR_OUT(3*16+15 downto 3*16+12) => open, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(3*32+31 downto 3*32) => mu_regio_data_out_1, + BUS_DATAREADY_IN(3) => mu_regio_dataready_out_1, + BUS_WRITE_ACK_IN(3) => mu_regio_write_ack_out_1, + BUS_NO_MORE_DATA_IN(3) => mu_regio_no_more_data_out_1, + BUS_UNKNOWN_ADDR_IN(3) => mu_regio_unknown_addr_out_1, STAT_DEBUG => open ); @@ -622,30 +670,30 @@ begin port map ( clk => clk_100_i, reset => reset_i, - timestamp_from_mupix => timestamp_from_mupix, - rowaddr_from_mupix => rowaddr_from_mupix, - coladdr_from_mupix => coladdr_from_mupix, - priout_from_mupix => priout_from_mupix, - sout_c_from_mupix => sout_c_from_mupix, - sout_d_from_mupix => sout_d_from_mupix, - hbus_form_mupix => hbus_form_mupix, - fpga_aux_from_board => fpga_aux_from_board, - ldpix_to_mupix => ldpix_to_mupix, - ldcol_to_mupix => ldcol_to_mupix, - timestamp_to_mupix => timestamp_to_mupix, - rdcol_to_mupix => rdcol_to_mupix, - pulldown_to_mupix => pulldown_to_mupix, - sin_to_mupix => sin_to_mupix, - ck_d_to_mupix => ck_d_to_mupix, - ck_c_to_mupix => ck_c_to_mupix, - ld_c_to_mupix => ld_c_to_mupix, - testpulse1_to_board => testpulse1_to_board, - testpulse2_to_board => testpulse2_to_board, - spi_din_to_board => spi_din_to_board, - spi_clk_to_board => spi_clk_to_board, - spi_ld_to_board => spi_ld_to_board, - fpga_led_to_board => fpga_led_to_board, - fpga_aux_to_board => fpga_aux_to_board, + timestamp_from_mupix => timestamp_from_mupix0, + rowaddr_from_mupix => rowaddr_from_mupix0, + coladdr_from_mupix => coladdr_from_mupix0, + priout_from_mupix => priout_from_mupix0, + sout_c_from_mupix => sout_c_from_mupix0, + sout_d_from_mupix => sout_d_from_mupix0, + hbus_from_mupix => hbus_from_mupix0, + fpga_aux_from_board => fpga_aux_from_board0, + ldpix_to_mupix => ldpix_to_mupix0, + ldcol_to_mupix => ldcol_to_mupix0, + timestamp_to_mupix => timestamp_to_mupix0, + rdcol_to_mupix => rdcol_to_mupix0, + pulldown_to_mupix => pulldown_to_mupix0, + sin_to_mupix => sin_to_mupix0, + ck_d_to_mupix => ck_d_to_mupix0, + ck_c_to_mupix => ck_c_to_mupix0, + ld_c_to_mupix => ld_c_to_mupix0, + testpulse1_to_board => testpulse1_to_board0, + testpulse2_to_board => testpulse2_to_board0, + spi_din_to_board => spi_din_to_board0, + spi_clk_to_board => spi_clk_to_board0, + spi_ld_to_board => spi_ld_to_board0, + fpga_led_to_board => fpga_led_to_board0, + fpga_aux_to_board => fpga_aux_to_board0, TIMING_TRG_IN => TRIGGER_RIGHT, LVL1_TRG_DATA_VALID_IN => trg_data_valid_i, @@ -659,26 +707,80 @@ begin LVL1_INT_TRG_NUMBER_IN => trg_int_number_i, FEE_TRG_RELEASE_OUT => fee_trg_release_i(0), - FEE_TRG_STATUSBITS_OUT => fee_trg_statusbits_i(31 downto 0), - FEE_DATA_OUT => fee_data_i(31 downto 0), + FEE_TRG_STATUSBITS_OUT => fee_trg_statusbits_i(0*32+31 downto 0*32), + FEE_DATA_OUT => fee_data_i(0*32+31 downto 0*32), FEE_DATA_WRITE_OUT => fee_data_write_i(0), FEE_DATA_FINISHED_OUT => fee_data_finished_i(0), FEE_DATA_ALMOST_FULL_IN => fee_almost_full_i(0), - REGIO_ADDR_IN => mu_regio_addr_in, - REGIO_DATA_IN => mu_regio_data_in, - REGIO_DATA_OUT => mu_regio_data_out, - REGIO_READ_ENABLE_IN => mu_regio_read_enable_in, - REGIO_WRITE_ENABLE_IN => mu_regio_write_enable_in, - REGIO_TIMEOUT_IN => mu_regio_timeout_in, - REGIO_DATAREADY_OUT => mu_regio_dataready_out, - REGIO_WRITE_ACK_OUT => mu_regio_write_ack_out, - REGIO_NO_MORE_DATA_OUT => mu_regio_no_more_data_out, - REGIO_UNKNOWN_ADDR_OUT => mu_regio_unknown_addr_out - - --DEBUG_LINE_OUT => TEST_LINE - --DEBUG_LINE_OUT => open - ); + REGIO_ADDR_IN => mu_regio_addr_in_0, + REGIO_DATA_IN => mu_regio_data_in_0, + REGIO_DATA_OUT => mu_regio_data_out_0, + REGIO_READ_ENABLE_IN => mu_regio_read_enable_in_0, + REGIO_WRITE_ENABLE_IN => mu_regio_write_enable_in_0, + REGIO_TIMEOUT_IN => mu_regio_timeout_in_0, + REGIO_DATAREADY_OUT => mu_regio_dataready_out_0, + REGIO_WRITE_ACK_OUT => mu_regio_write_ack_out_0, + REGIO_NO_MORE_DATA_OUT => mu_regio_no_more_data_out_0, + REGIO_UNKNOWN_ADDR_OUT => mu_regio_unknown_addr_out_0); + + MuPix3_Board_1 : MuPix3_Board + port map ( + clk => clk_100_i, + reset => reset_i, + timestamp_from_mupix => timestamp_from_mupix1, + rowaddr_from_mupix => rowaddr_from_mupix1, + coladdr_from_mupix => coladdr_from_mupix1, + priout_from_mupix => priout_from_mupix1, + sout_c_from_mupix => sout_c_from_mupix1, + sout_d_from_mupix => sout_d_from_mupix1, + hbus_from_mupix => hbus_from_mupix1, + fpga_aux_from_board => fpga_aux_from_board1, + ldpix_to_mupix => ldpix_to_mupix1, + ldcol_to_mupix => ldcol_to_mupix1, + timestamp_to_mupix => timestamp_to_mupix1, + rdcol_to_mupix => rdcol_to_mupix1, + pulldown_to_mupix => pulldown_to_mupix1, + sin_to_mupix => sin_to_mupix1, + ck_d_to_mupix => ck_d_to_mupix1, + ck_c_to_mupix => ck_c_to_mupix1, + ld_c_to_mupix => ld_c_to_mupix1, + testpulse1_to_board => testpulse1_to_board1, + testpulse2_to_board => testpulse2_to_board1, + spi_din_to_board => spi_din_to_board1, + spi_clk_to_board => spi_clk_to_board1, + spi_ld_to_board => spi_ld_to_board1, + fpga_led_to_board => fpga_led_to_board1, + fpga_aux_to_board => fpga_aux_to_board1, + + TIMING_TRG_IN => TRIGGER_RIGHT, + LVL1_TRG_DATA_VALID_IN => trg_data_valid_i, + LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i, + LVL1_VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, + LVL1_INVALID_TRG_IN => trg_invalid_i, + LVL1_TRG_TYPE_IN => trg_type_i, + LVL1_TRG_NUMBER_IN => trg_number_i, + LVL1_TRG_CODE_IN => trg_code_i, + LVL1_TRG_INFORMATION_IN => trg_information_i, + LVL1_INT_TRG_NUMBER_IN => trg_int_number_i, + + FEE_TRG_RELEASE_OUT => fee_trg_release_i(1), + FEE_TRG_STATUSBITS_OUT => fee_trg_statusbits_i(1*32+31 downto 1*32), + FEE_DATA_OUT => fee_data_i(1*32+31 downto 1*32), + FEE_DATA_WRITE_OUT => fee_data_write_i(1), + FEE_DATA_FINISHED_OUT => fee_data_finished_i(1), + FEE_DATA_ALMOST_FULL_IN => fee_almost_full_i(1), + + REGIO_ADDR_IN => mu_regio_addr_in_1, + REGIO_DATA_IN => mu_regio_data_in_1, + REGIO_DATA_OUT => mu_regio_data_out_1, + REGIO_READ_ENABLE_IN => mu_regio_read_enable_in_1, + REGIO_WRITE_ENABLE_IN => mu_regio_write_enable_in_1, + REGIO_TIMEOUT_IN => mu_regio_timeout_in_1, + REGIO_DATAREADY_OUT => mu_regio_dataready_out_1, + REGIO_WRITE_ACK_OUT => mu_regio_write_ack_out_1, + REGIO_NO_MORE_DATA_OUT => mu_regio_no_more_data_out_1, + REGIO_UNKNOWN_ADDR_OUT => mu_regio_unknown_addr_out_1);