From: Michael Boehmer Date: Fri, 14 Jan 2022 08:52:10 +0000 (+0100) Subject: first backplane master compilation X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=58088219f496298612f524071e8a313c4bf8fa95;p=trb3sc.git first backplane master compilation --- diff --git a/backplanemaster/config.vhd b/backplanemaster/config.vhd index c207a67..2b3c20e 100644 --- a/backplanemaster/config.vhd +++ b/backplanemaster/config.vhd @@ -11,19 +11,19 @@ package config is ------------------------------------------------------------------------------ --We use an ECP3 - constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 + constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 --Gbe included? constant INCLUDE_GBE : integer := c_NO; --Runs with 120 MHz instead of 100 MHz - constant USE_120_MHZ : integer := c_NO; - constant USE_200MHZOSCILLATOR : integer := c_YES; - constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. - constant CLOCK_FAST_SELECT : integer := c_YES; --fast clock select (135us) or slow (280ms)? + constant USE_120_MHZ : integer := c_NO; + constant USE_200MHZOSCILLATOR : integer := c_YES; + constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_YES; --fast clock select (135us) or slow (280ms)? --Use sync mode, RX clock for all parts of the FPGA - constant USE_RXCLOCK : integer := c_NO; + constant USE_RXCLOCK : integer := c_NO; --Address settings constant INIT_ADDRESS : std_logic_vector := x"F3CE"; @@ -57,26 +57,26 @@ package config is --With GbE: --- for MII_NUMBER=10 --- port 0-8: downlinks to other FPGA --- port 9: LVL1/Data channel on uplink to CTS, but internal endpoint on SCTRL --- port 10: SCTRL channel on uplink to CTS --- port 11: SCTRL channel from GbE interface +-- for MII_NUMBER=5 +-- port 0-3: downlinks to other FPGA +-- port 4: LVL1/Data channel on uplink to CTS, but internal endpoint on SCTRL +-- port 5: SCTRL channel on uplink to CTS +-- port 6: SCTRL channel from GbE interface --Without GbE: --- for MII_NUMBER=11 --- port 0-8: downlinks to other FPGA --- port 9: SFP2 (outer) slow control --- port 10: SFP1 (inner) trigger --- port 11: internal sctrl - - constant INTERFACE_NUM_ARR : hub_mii_t := (6,5); -- number of SerDes links - constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,0,0, 1,1,0,0,0,0,0,0,0,0,0,0,0), - (0,0,0,0, 1,1,1,0,0,0,0,0,0,0,0,0,0)); - constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1, 0,1,1,0,0,0,0,0,0,0,0,0,0), - (1,1,1,1, 1,0,0,0,0,0,0,0,0,0,0,0,0)); - constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0, 1,0,0,0,0,0,0,0,0,0,0,0,0), - (0,0,0,0, 0,1,1,0,0,0,0,0,0,0,0,0,0)); +-- for MII_NUMBER=5 +-- port 0-3: downlinks to other FPGA +-- port 4: SFP2 (outer) uplink to CTS (slow control + trigger + readout) +-- port 5: internal endpoint on SCTRL (i.e. TRBnet access to hub) + + constant INTERFACE_NUM_ARR : hub_mii_t := (5,5); -- number of SerDes links +-- 0 1 2 3 4 5 6 7 8 9 a b c d e f + constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0)); + constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0), + (1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0)); + constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,1,1,0,0,0,0,0,0,0,0,0,0)); constant INTERFACE_NUM : integer; constant MII_IS_UPLINK : hub_ct; diff --git a/backplanemaster/trb3sc_master.lpf b/backplanemaster/trb3sc_master.lpf index 1e62b56..9ce4bd6 100644 --- a/backplanemaster/trb3sc_master.lpf +++ b/backplanemaster/trb3sc_master.lpf @@ -1,21 +1,10 @@ -LOCATE COMP "THE_MEDIA_INT_MIXED/THE_SERDES/PCSD_INST" SITE "PCSB" ; -LOCATE COMP "THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST" SITE "PCSA" ; -LOCATE COMP "THE_MEDIA_4_DOWN2/THE_SERDES/PCSD_INST" SITE "PCSC" ; -LOCATE COMP "gen_PCSD.THE_MEDIA_PCSD/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSD" ; - -#REGION "MEDIA_DOWN1" "R93C10D" 22 160; -#REGION "MEDIA_DOWN1" "R100C40D" 15 100; -#LOCATE UGROUP "THE_MEDIA_4_DOWN/media_interface_group" REGION "MEDIA_DOWN1" ; - +# locate the PCS blocks +LOCATE COMP "THE_MEDIA_INT_MIXED/THE_SERDES/PCSD_INST" SITE "PCSB" ; +LOCATE COMP "THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST" SITE "PCSA" ; LOCATE COMP "gen_GBE.GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD"; -REGION "MEDIA_A" "R75C100D" 45 46; -REGION "MEDIA_B" "R85C45D" 35 56; -REGION "MEDIA_C" "R75C135D" 45 46; -REGION "MEDIA_D" "R75C19D" 40 36; - -LOCATE UGROUP "THE_MEDIA_4_DOWN/media_interface_group" REGION "MEDIA_A" ; -LOCATE UGROUP "THE_MEDIA_INT_MIXED/media_interface_group" REGION "MEDIA_B" ; -LOCATE UGROUP "THE_MEDIA_4_DOWN2/media_interface_group" REGION "MEDIA_C" ; -LOCATE UGROUP "gen_PCSD.THE_MEDIA_PCSD/media_interface_group" REGION "MEDIA_D" ; - +# locate the media interfaces inside fabric +REGION "MEDIA_LEFT" "R102C17D" 13 75; # LEFT is for PCSD/PCSB +REGION "MEDIA_RIGHT" "R102C92D" 13 75; # RIGHT is for PCSA/PCSC +LOCATE UGROUP "THE_MEDIA_INT_MIXED/media_interface_group" REGION "MEDIA_LEFT" ; +LOCATE UGROUP "THE_MEDIA_4_DOWN/media_interface_group" REGION "MEDIA_RIGHT" ; diff --git a/backplanemaster/trb3sc_master.prj b/backplanemaster/trb3sc_master.prj index 81e1854..3169f83 100644 --- a/backplanemaster/trb3sc_master.prj +++ b/backplanemaster/trb3sc_master.prj @@ -50,8 +50,6 @@ impl -active "workdir" #################### - - #Packages add_file -vhdl -lib work "workdir/version.vhd" add_file -vhdl -lib work "config.vhd" @@ -74,7 +72,6 @@ add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record. add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd" - #Fifos add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" @@ -102,7 +99,6 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dual add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/ram_18x256_oreg.vhd" - #Flash & Reload, Tools add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" @@ -129,20 +125,16 @@ add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" #Media interface -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4_slave3.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd index 26780d7..07b27de 100644 --- a/backplanemaster/trb3sc_master.vhd +++ b/backplanemaster/trb3sc_master.vhd @@ -11,7 +11,7 @@ use work.trb3_components.all; use work.trb_net16_hub_func.all; use work.version.all; use work.trb_net_gbe_components.all; -use work.med_sync_define.all; +use work.med_sync_define_RS.all; entity trb3sc_master is port( @@ -21,7 +21,7 @@ entity trb3sc_master is -- Trigger TRIG_LEFT : in std_logic; --Additional IO - HDR_IO : inout std_logic_vector(10 downto 1); +-- HDR_IO : inout std_logic_vector(10 downto 1); RJ_IO : inout std_logic_vector( 3 downto 0); -- SPARE_IN : in std_logic_vector( 1 downto 0); BACK_LVDS : inout std_logic_vector( 1 downto 0); @@ -70,9 +70,9 @@ entity trb3sc_master is FLASH_OUT : in std_logic; PROGRAMN : out std_logic; ENPIRION_CLOCK : out std_logic; - TEMPSENS : inout std_logic; + TEMPSENS : inout std_logic --Test Connectors - TEST_LINE : out std_logic_vector(15 downto 0) +-- TEST_LINE : out std_logic_vector(15 downto 0) ); attribute syn_useioff : boolean; @@ -80,7 +80,7 @@ entity trb3sc_master is attribute syn_useioff of FLASH_CS : signal is true; attribute syn_useioff of FLASH_IN : signal is true; attribute syn_useioff of FLASH_OUT : signal is true; - attribute syn_useioff of HDR_IO : signal is false; +-- attribute syn_useioff of HDR_IO : signal is false; --Serdes: Backplane --Backplane A2,A3,A0,A1 Slave 3,4,1,2, A0: TrbNet from backplane @@ -96,7 +96,6 @@ architecture trb3sc_arch of trb3sc_master is signal clk_sys, clk_full, clk_full_osc : std_logic; signal GSR_N : std_logic; signal reset_i : std_logic; - signal clear_i : std_logic; signal do_reboot_i, reboot_from_gbe : std_logic; signal time_counter : unsigned(31 downto 0) := (others => '0'); @@ -162,8 +161,7 @@ architecture trb3sc_arch of trb3sc_master is signal med_stat_op : std_logic_vector (11*16-1 downto 0); signal med_ctrl_op : std_logic_vector (11*16-1 downto 0); signal rdack, wrack : std_logic; - signal reset_from_net_i : std_logic; - signal send_reset_i : std_logic; +-- signal reset_from_net_i : std_logic; signal external_reset_delayed : std_logic_vector(4 downto 0); signal trig_gen_out_i : std_logic_vector(3 downto 0); @@ -180,7 +178,24 @@ architecture trb3sc_arch of trb3sc_master is attribute syn_preserve of bustools_rx : signal is true; attribute syn_keep of bustc_rx : signal is true; attribute syn_preserve of bustc_rx : signal is true; - + + signal word_sync_i : std_logic; + signal master_clk_i : std_logic; + signal global_reset_i : std_logic; + signal tx_pll_lol_qd_a_i : std_logic; + signal tx_pll_lol_qd_b_i : std_logic; + signal tx_pll_lol_qd_c_i : std_logic; + signal tx_pll_lol_qd_d_i : std_logic; + signal tx_pll_lol_all_i : std_logic; + signal tx_clk_avail_i : std_logic; + signal tx_pcs_rst_i : std_logic; + signal sync_tx_quad_i : std_logic; + signal link_tx_ready_i : std_logic; + signal slave_active_i : std_logic; + signal rx_dlm_i : std_logic; + signal tx_reset_state : std_logic_vector(3 downto 0); + signal debug_i : std_logic_vector(31 downto 0); + begin --------------------------------------------------------------------------- @@ -188,138 +203,210 @@ begin --------------------------------------------------------------------------- THE_CLOCK_RESET : entity work.clock_reset_handler port map( - INT_CLK_IN => CLK_CORE_PCLK, - EXT_CLK_IN => CLK_EXT_PLL_LEFT, - NET_CLK_FULL_IN => med2int(4).clk_full, - NET_CLK_HALF_IN => med2int(4).clk_half, - RESET_FROM_NET => reset_from_net_i, - SEND_RESET_IN => send_reset_i, - - BUS_RX => bustc_rx, - BUS_TX => bustc_tx, - - RESET_OUT => reset_i, - CLEAR_OUT => clear_i, - GSR_OUT => GSR_N, - - FULL_CLK_OUT => clk_full, - SYS_CLK_OUT => clk_sys, - REF_CLK_OUT => clk_full_osc, - - ENPIRION_CLOCK => ENPIRION_CLOCK, - LED_RED_OUT => LED_RJ_RED, - LED_GREEN_OUT => LED_RJ_GREEN, - DEBUG_OUT => debug_clock_reset + INT_CLK_IN => CLK_CORE_PCLK, + EXT_CLK_IN => CLK_EXT_PLL_LEFT, + NET_CLK_FULL_IN => med2int(4).clk_full, + NET_CLK_HALF_IN => med2int(4).clk_half, + GLOBAL_RESET_IN => global_reset_i, + RESET_FROM_NET_IN => '0', + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + RESET_OUT => reset_i, + CLEAR_OUT => open, + GSR_OUT => GSR_N, + FULL_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + REF_CLK_OUT => clk_full_osc, + ENPIRION_CLOCK => ENPIRION_CLOCK, + LED_RED_OUT => LED_RJ_RED, + LED_GREEN_OUT => LED_RJ_GREEN, + DEBUG_OUT => debug_clock_reset ); - - reset_from_net_i <= med2int(4).stat_op(13) or external_reset_delayed(4); - send_reset_i <= med2int(4).stat_op(15); - + + tx_pll_lol_qd_c_i <= '0'; + --------------------------------------------------------------------------- -- TrbNet Uplink --------------------------------------------------------------------------- -THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync --PCSB +THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS --PCSB generic map( - SERDES_NUM => 3, - IS_SYNC_SLAVE => c_YES + IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE), + IS_WAP_ZERO => 1 ) port map( + -- Clocks and reset CLK_REF_FULL => clk_full_osc, - CLK_INTERNAL_FULL => clk_full_osc, SYSCLK => clk_sys, RESET => reset_i, - CLEAR => clear_i, - --Internal Connection - MEDIA_MED2INT => med2int(4), - MEDIA_INT2MED => int2med(4), - --Sync operation - RX_DLM => open, - RX_DLM_WORD => open, - TX_DLM => open, - TX_DLM_WORD => open, + -- Media Interface TX/RX + MEDIA_MED2INT(0) => open, + MEDIA_MED2INT(1) => open, + MEDIA_MED2INT(2) => open, + MEDIA_MED2INT(3) => med2int(4), + MEDIA_INT2MED(0) => open, + MEDIA_INT2MED(1) => open, + MEDIA_INT2MED(2) => open, + MEDIA_INT2MED(3) => int2med(4), + -- komma operation + RX_DLM_OUT(0) => open, + RX_DLM_OUT(1) => open, + RX_DLM_OUT(2) => open, + RX_DLM_OUT(3) => rx_dlm_i, + RX_DLM_WORD_OUT => open, + TX_DLM_IN => rx_dlm_i, + TX_DLM_WORD_IN => x"00", + RX_RST_OUT => open, + RX_RST_WORD_OUT => open, + TX_RST_IN => '0', + TX_RST_WORD_IN => x"00", + -- sync operation + WORD_SYNC_IN => word_sync_i, + WORD_SYNC_OUT => word_sync_i, + MASTER_CLK_IN => master_clk_i, + MASTER_CLK_OUT => master_clk_i, + QUAD_RST_IN => global_reset_i, + GLOBAL_RESET_OUT => global_reset_i, + SLAVE_ACTIVE_OUT => slave_active_i, + SLAVE_ACTIVE_IN => slave_active_i, + TX_PLL_LOL_IN => tx_pll_lol_all_i, + TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, + TX_CLK_AVAIL_OUT => tx_clk_avail_i, + TX_PCS_RST_IN => tx_pcs_rst_i, + SYNC_TX_PLL_IN => sync_tx_quad_i, + LINK_TX_READY_IN => link_tx_ready_i, + DESTROY_LINK_IN => x"0", --SFP Connection - SD_PRSNT_N_IN => SFP_MOD0(1), - SD_LOS_IN => SFP_LOS(1), - SD_TXDIS_OUT => SFP_TX_DIS(1), + SD_PRSNT_N_IN(0) => '1', + SD_PRSNT_N_IN(1) => '1', + SD_PRSNT_N_IN(2) => '1', + SD_PRSNT_N_IN(3) => SFP_MOD0(1), + SD_LOS_IN(0) => '1', + SD_LOS_IN(1) => '1', + SD_LOS_IN(2) => '1', + SD_LOS_IN(3) => SFP_LOS(1), + SD_TXDIS_OUT(0) => open, + SD_TXDIS_OUT(1) => open, + SD_TXDIS_OUT(2) => open, + SD_TXDIS_OUT(3) => SFP_TX_DIS(1), --Control Interface BUS_RX => bussci2_rx, BUS_TX => bussci2_tx, -- Status and control port STAT_DEBUG => open, - CTRL_DEBUG => open + CTRL_DEBUG => open, + DEBUG_OUT => debug_i ); --------------------------------------------------------------------------- --- PCSD Uplink when no GbE is used +-- PCSC not used --------------------------------------------------------------------------- -gen_PCSD : if INCLUDE_GBE = c_NO generate - THE_MEDIA_PCSD : entity work.med_ecp3_sfp_sync - generic map( - SERDES_NUM => 0, - IS_SYNC_SLAVE => c_NO - ) - port map( - CLK_REF_FULL => clk_full_osc, - CLK_INTERNAL_FULL => clk_full_osc, - SYSCLK => clk_sys, - RESET => reset_i, - CLEAR => clear_i, - --Internal Connection - MEDIA_MED2INT => med2int(5), - MEDIA_INT2MED => int2med(5), - --Sync operation - RX_DLM => open, - RX_DLM_WORD => open, - TX_DLM => open, - TX_DLM_WORD => open, - --SFP Connection - SD_PRSNT_N_IN => SFP_MOD0(0), - SD_LOS_IN => SFP_LOS(0), - SD_TXDIS_OUT => SFP_TX_DIS(0), - --Control Interface - BUS_RX => bussci4_rx, - BUS_TX => bussci4_tx, - -- Status and control port - STAT_DEBUG => open, - CTRL_DEBUG => open - ); -end generate; + + tx_pll_lol_qd_c_i <= '0'; + + bussci3_tx.data <= (others => '0'); + bussci3_tx.ack <= '0'; + bussci3_tx.nack <= '0'; + bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys); + +--------------------------------------------------------------------------- +-- PCSD not used +--------------------------------------------------------------------------- + + tx_pll_lol_qd_d_i <= '0'; + + bussci4_tx.data <= (others => '0'); + bussci4_tx.ack <= '0'; + bussci4_tx.nack <= '0'; + bussci4_tx.unknown <= bussci4_rx.read or bussci4_rx.write when rising_edge(clk_sys); + +--------------------------------------------------------------------------- +-- TX reset +--------------------------------------------------------------------------- + THE_MAIN_TX_RST: main_tx_reset_RS + port map ( + CLEAR => '0', + CLK_REF => clk_full_osc, + TX_PLL_LOL_QD_A_IN => tx_pll_lol_qd_a_i, + TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i, + TX_PLL_LOL_QD_C_IN => tx_pll_lol_qd_c_i, + TX_PLL_LOL_QD_D_IN => tx_pll_lol_qd_d_i, + TX_PLL_LOL_OUT => tx_pll_lol_all_i, + TX_CLOCK_AVAIL_IN => tx_clk_avail_i, + TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i, + SYNC_TX_QUAD_OUT => sync_tx_quad_i, + LINK_TX_READY_OUT => link_tx_ready_i, + STATE_OUT => tx_reset_state + ); --------------------------------------------------------------------------- -- TrbNet Downlink --------------------------------------------------------------------------- -THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_4 --PCSA +THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_all_RS --PCSA generic map( - IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), - IS_USED => (c_YES, c_YES, c_YES, c_YES) + IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER), + IS_WAP_ZERO => 1 ) port map( - CLK_REF_FULL => clk_full_osc, - CLK_INTERNAL_FULL => clk_full_osc, - SYSCLK => clk_sys, - RESET => reset_i, - CLEAR => clear_i, - --Internal Connection - MEDIA_MED2INT(0 to 3) => med2int(0 to 3), - MEDIA_INT2MED(0 to 3) => int2med(0 to 3), - --Sync operation - RX_DLM => open, - RX_DLM_WORD => open, - TX_DLM => open, - TX_DLM_WORD => open, + -- Clocks and reset + CLK_REF_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + -- Media Interface TX/RX + MEDIA_MED2INT(0) => med2int(0), + MEDIA_MED2INT(1) => med2int(1), + MEDIA_MED2INT(2) => med2int(2), + MEDIA_MED2INT(3) => med2int(3), + MEDIA_INT2MED(0) => int2med(0), + MEDIA_INT2MED(1) => int2med(1), + MEDIA_INT2MED(2) => int2med(2), + MEDIA_INT2MED(3) => int2med(3), + -- komma operation + RX_DLM_OUT => open, + RX_DLM_WORD_OUT => open, + TX_DLM_IN => rx_dlm_i, + TX_DLM_WORD_IN => x"00", + RX_RST_OUT => open, + RX_RST_WORD_OUT => open, + TX_RST_IN => '0', + TX_RST_WORD_IN => x"00", + -- sync operation + WORD_SYNC_IN => word_sync_i, + WORD_SYNC_OUT => open, + MASTER_CLK_IN => master_clk_i, + MASTER_CLK_OUT => open, + QUAD_RST_IN => global_reset_i, + GLOBAL_RESET_OUT => open, + SLAVE_ACTIVE_OUT => open, + SLAVE_ACTIVE_IN => slave_active_i, + TX_PLL_LOL_IN => tx_pll_lol_all_i, + TX_PLL_LOL_OUT => tx_pll_lol_qd_a_i, + TX_CLK_AVAIL_OUT => open, + TX_PCS_RST_IN => tx_pcs_rst_i, + SYNC_TX_PLL_IN => sync_tx_quad_i, + LINK_TX_READY_IN => link_tx_ready_i, + DESTROY_LINK_IN => x"0", --SFP Connection - SD_PRSNT_N_IN => backplane_rx_present(3 downto 0), - SD_LOS_IN => backplane_rx_present(3 downto 0), - SD_TXDIS_OUT => backplane_tx_present(3 downto 0), + SD_PRSNT_N_IN(0) => backplane_rx_present(0), + SD_PRSNT_N_IN(1) => backplane_rx_present(1), + SD_PRSNT_N_IN(2) => backplane_rx_present(2), + SD_PRSNT_N_IN(3) => backplane_rx_present(3), + SD_LOS_IN(0) => backplane_rx_present(0), + SD_LOS_IN(1) => backplane_rx_present(1), + SD_LOS_IN(2) => backplane_rx_present(2), + SD_LOS_IN(3) => backplane_rx_present(3), + SD_TXDIS_OUT(0) => backplane_tx_present(0), + SD_TXDIS_OUT(1) => backplane_tx_present(1), + SD_TXDIS_OUT(2) => backplane_tx_present(2), + SD_TXDIS_OUT(3) => backplane_tx_present(3), --Control Interface - BUS_RX => bussci1_rx, - BUS_TX => bussci1_tx, + BUS_RX => bussci1_rx, + BUS_TX => bussci1_tx, -- Status and control port - STAT_DEBUG => med_stat_debug(63 downto 0), - CTRL_DEBUG => open + STAT_DEBUG => open, + CTRL_DEBUG => open, + DEBUG_OUT => open ); - GEN_READY_SIGNALS : for i in 0 to 4 generate backplane_rx_present(i) <= BACK_SLAVE_READY(i); BACK_MASTER_READY(i) <= backplane_tx_present(i) or SFP_LOS(1); @@ -652,7 +739,7 @@ end generate; SPI_MISO_IN => spi_miso, SPI_CLK_OUT => spi_clk, --Header - HEADER_IO => HDR_IO, + HEADER_IO => open, --HDR_IO, --LCD LCD_DATA_IN => lcd_data, --ADC @@ -702,20 +789,20 @@ end generate; -- LED --------------------------------------------------------------------------- --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) - LED_GREEN <= debug_clock_reset(0); - LED_ORANGE <= debug_clock_reset(1); - LED_RED <= not sed_error_i; - LED_YELLOW <= debug_clock_reset(2); + LED_GREEN <= not debug_i(24 + 3); -- LFD --debug_clock_reset(0); + LED_ORANGE <= not debug_i(24 + 2); -- LHD --debug_clock_reset(1); + LED_RED <= not debug_i(24 + 1); -- LRR --not sed_error_i; + LED_YELLOW <= not debug_i(24 + 0); -- LTR --debug_clock_reset(2); LED_WHITE <= led; - LED_SFP_GREEN(1) <= not med2int(4).stat_op(9); --SFP Link Status - LED_SFP_RED(1) <= not (med2int(4).stat_op(10) or med2int(4).stat_op(11)); --SFP RX/TX + LED_SFP_GREEN(1) <= not med2int(4).stat_op(9); --SFP Link Status + LED_SFP_RED(1) <= not (med2int(4).stat_op(10) or med2int(4).stat_op(11)); --SFP RX/TX gen_led_nogbe : if INCLUDE_GBE = c_NO generate - LED_SFP_GREEN(0) <= not med2int(5).stat_op(9); --SFP Link Status - LED_SFP_RED(0) <= not (med2int(5).stat_op(10) or med2int(5).stat_op(11)); --SFP RX/TX + LED_SFP_GREEN(0) <= not '0'; --SFP Link Status + LED_SFP_RED(0) <= not '0'; --SFP RX/TX end generate; gen_led_gbe : if INCLUDE_GBE = c_YES generate - LED_SFP_GREEN(0) <= '1'; - LED_SFP_RED(0) <= '1'; + LED_SFP_GREEN(0) <= not '0'; + LED_SFP_RED(0) <= not '0'; end generate; --------------------------------------------------------------------------- -- LCD Data to display @@ -748,17 +835,9 @@ end generate; end process; led(0) <= time_counter(26) and time_counter(16); - led(1) <= not (clear_i or reset_i); + led(1) <= not (reset_i); --- TEST_LINE(0) <= med2int(4).stat_op(13); --- TEST_LINE(1) <= med2int(4).stat_op(15); --- TEST_LINE(2) <= clear_i; --- TEST_LINE(3) <= reset_i; --- TEST_LINE(4) <= med2int(4).dataready; --- TEST_LINE(5) <= int2med(4).dataready; --- TEST_LINE(6) <= med2int(2).dataready; --- TEST_LINE(7) <= int2med(2).dataready; - TEST_LINE <= (others => '0'); +-- TEST_LINE <= (others => '0'); end architecture;