From: Adrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Date: Thu, 18 Jun 2020 09:51:36 +0000 (+0200)
Subject: fixed the reset to a more stable and well known solution. -> Gives some Setup Time... 
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5854324519e77dec637a63a35f8f52347357ed09;p=dirich.git

fixed the reset to a more stable and well known solution. -> Gives some Setup Time Problmes. To be checked!
---

diff --git a/combiner_cts/combiner.vhd b/combiner_cts/combiner.vhd
index 8f6010c..69a55f3 100644
--- a/combiner_cts/combiner.vhd
+++ b/combiner_cts/combiner.vhd
@@ -235,6 +235,10 @@ architecture arch of combiner is
   signal test_LED          : std_logic_vector(1 downto 0);
   
   signal reset_cnt         : unsigned(31 downto 0) := (others => '0');
+  
+  signal reset_via_cri_long, reset_via_cri_timer, last_reset_via_cri_long, make_reset : std_logic;
+  signal reset_via_cri : std_logic := '0';
+  signal last_cri_resetPulse : std_logic;
 
   component trb_net16_cri_interface is
     port(
@@ -270,7 +274,7 @@ begin
 THE_CLOCK_RESET :  entity work.clock_reset_handler
   port map(
     CLOCK_IN        => CLOCK_PCLK,
-    RESET_FROM_NET  => int2med(0).ctrl_op(15),--med2int(INTERFACE_NUM).stat_op(13),
+    RESET_FROM_NET  => make_reset,--med2int(INTERFACE_NUM).stat_op(13),
     CLOCK_SELECT_IN => CLOCK_SELECT_IN,
     
     BUS_RX          => bustc_rx,
@@ -287,6 +291,29 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
     DEBUG_OUT       => debug_clock_reset
     );
 
+  
+  CRI_RESET_PULSE_PROC : process begin
+    wait until rising_edge(clk_sys);
+    last_cri_resetPulse <= med2int(INTERFACE_NUM).stat_op(13);
+    reset_via_cri       <= last_cri_resetPulse and not med2int(INTERFACE_NUM).stat_op(13);
+  end process;
+  
+  
+  --reset_via_cri <= med2int(INTERFACE_NUM).stat_op(13);
+  
+  proc_make_reset : process begin
+    wait until rising_edge(clk_sys);
+    if( reset_via_cri = '1') then
+      reset_via_cri_long <= '1';
+      reset_via_cri_timer <= '1';
+    end if;
+    if timer.tick_us = '1' then
+      reset_via_cri_timer <= '0';
+      reset_via_cri_long  <= reset_via_cri_timer;
+    end if;
+    last_reset_via_cri_long <= reset_via_cri_long;
+    make_reset <= last_reset_via_cri_long and not reset_via_cri_long;
+  end process;      
 ---------------------------------------------------------------------------
 -- TrbNet Uplink
 ---------------------------------------------------------------------------
@@ -597,7 +624,7 @@ back_slave_ready_i <= BACK_SLAVE_READY;
       TIMER_TICKS_OUT(0)  => timer.tick_us,
       TIMER_TICKS_OUT(1)  => timer.tick_ms,
       TEMPERATURE_OUT     => timer.temperature,
-      EXTERNAL_SEND_RESET => med2int(INTERFACE_NUM).stat_op(13),--reset_via_gbe,
+      EXTERNAL_SEND_RESET => reset_via_cri,
 
       REGIO_ADDR_OUT            => ctrlbus_rx.addr,
       REGIO_READ_ENABLE_OUT     => ctrlbus_rx.read,