From: Cahit Date: Wed, 9 Apr 2014 15:41:57 +0000 (+0200) Subject: history for rd/wr fsm states created X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=59c1e408ee82eb13b7ef5406ddf3bfd878f589f9;p=trb3.git history for rd/wr fsm states created --- diff --git a/hadesstart/trb3_periph_hadesstart.vhd b/hadesstart/trb3_periph_hadesstart.vhd index 0ffed00..09f1a2c 100644 --- a/hadesstart/trb3_periph_hadesstart.vhd +++ b/hadesstart/trb3_periph_hadesstart.vhd @@ -816,7 +816,7 @@ THE_SED : entity work.sedcheck THE_TDC : TDC generic map ( CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels - STATUS_REG_NR => 20, -- Number of status regs + STATUS_REG_NR => 22, -- Number of status regs CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr TDC_VERSION => x"160", -- TDC version number DEBUG => c_YES, diff --git a/tdc_releases/tdc_v1.6/Readout.vhd b/tdc_releases/tdc_v1.6/Readout.vhd index 6b615d6..578e15d 100644 --- a/tdc_releases/tdc_v1.6/Readout.vhd +++ b/tdc_releases/tdc_v1.6/Readout.vhd @@ -5,7 +5,7 @@ -- File : Readout.vhd -- Author : cugur@gsi.de -- Created : 2012-10-25 --- Last update: 2014-03-16 +-- Last update: 2014-04-09 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -246,7 +246,11 @@ architecture behavioral of Readout is signal ch_full_i : std_logic; signal ch_almost_full_i : std_logic; signal rd_fsm_debug : std_logic_vector(3 downto 0); + signal rd_fsm_debug_reg : std_logic_vector(3 downto 0); + signal history_rd_fsm : std_logic_vector(31 downto 0) := (others => '0'); signal wr_fsm_debug : std_logic_vector(3 downto 0); + signal wr_fsm_debug_reg : std_logic_vector(3 downto 0); + signal history_wr_fsm : std_logic_vector(31 downto 0) := (others => '0'); signal status_registers_bus_i : std_logic_vector(31 downto 0); begin -- behavioral @@ -925,6 +929,25 @@ begin -- behavioral end if; end process Statistics_Finished_Number; + HistoryReadDebug : process (CLK_100) + begin + if rising_edge(CLK_100) then + if rd_fsm_debug_reg /= rd_fsm_debug then + history_rd_fsm <= history_rd_fsm(27 downto 0) & rd_fsm_debug; + end if; + rd_fsm_debug_reg <= rd_fsm_debug; + end if; + end process HistoryReadDebug; + + HistoryWriteDebug : process (CLK_100) + begin + if rising_edge(CLK_100) then + if wr_fsm_debug_reg /= wr_fsm_debug then + history_wr_fsm <= history_wr_fsm(27 downto 0) & wr_fsm_debug; + end if; + wr_fsm_debug_reg <= wr_fsm_debug; + end if; + end process HistoryWriteDebug; ------------------------------------------------------------------------------- -- STATUS REGISTERS BUS @@ -959,6 +982,9 @@ begin -- behavioral STATUS_REGISTERS_BUS_OUT(17)(23 downto 0) <= std_logic_vector(timeout_number); STATUS_REGISTERS_BUS_OUT(18)(23 downto 0) <= std_logic_vector(finished_number); + STATUS_REGISTERS_BUS_OUT(19) <= history_rd_fsm; + STATUS_REGISTERS_BUS_OUT(20) <= history_wr_fsm; + FILL_BUS1 : for i in 4 to 18 generate STATUS_REGISTERS_BUS_OUT(i)(31 downto 24) <= (others => '0'); end generate FILL_BUS1; diff --git a/tdc_releases/tdc_v1.6/TDC.vhd b/tdc_releases/tdc_v1.6/TDC.vhd index d1246ba..58b8d3e 100644 --- a/tdc_releases/tdc_v1.6/TDC.vhd +++ b/tdc_releases/tdc_v1.6/TDC.vhd @@ -205,8 +205,10 @@ begin -- Reset signals reset_tdc_i <= RESET when rising_edge(CLK_TDC); reset_tdc <= reset_tdc_i when rising_edge(CLK_TDC); - reset_rdo_i <= RESET when rising_edge(CLK_READOUT); - reset_rdo <= reset_rdo_i when rising_edge(CLK_READOUT); + + --reset_rdo_i <= RESET when rising_edge(CLK_READOUT); + --reset_rdo <= reset_rdo_i when rising_edge(CLK_READOUT); + reset_rdo <= RESET; -- Hit for calibration generation Calibration_Pulses : process (HIT_CALIBRATION)