From: local account Date: Thu, 27 Oct 2016 15:13:12 +0000 (+0200) Subject: Implemented SPI and changed to testboard X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5a0f38e6d24f125b2d4740a402805ae2909040f2;p=dirich.git Implemented SPI and changed to testboard --- diff --git a/code/spi_slave.vhd b/code/spi_slave.vhd new file mode 100644 index 0000000..f234756 --- /dev/null +++ b/code/spi_slave.vhd @@ -0,0 +1,154 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; + + +entity spi_slave is + port( + CLK : in std_logic; + + SPI_CLK : in std_logic; + SPI_CS : in std_logic; + SPI_IN : in std_logic; + SPI_OUT : out std_logic; + + DATA_OUT : out std_logic_vector(15 downto 0); + DATA_IN : in std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(7 downto 0); + WRITE_OUT : out std_logic; + READ_OUT : out std_logic; + READY_IN : in std_logic; + + DEBUG : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture SPI_Slave_arch of spi_slave is +signal spi_clk_last : std_logic; +signal spi_clk_reg : std_logic; +signal spi_cs_reg : std_logic; +signal spi_in_reg : std_logic; + +signal operation_i : std_logic; +signal data_write : std_logic_vector(15 downto 0); +signal data_in_i : std_logic_vector(15 downto 0); +signal addr_i : std_logic_vector(7 downto 0); +signal last_input : std_logic; +signal input : std_logic_vector(31 downto 0); + +signal next_output : std_logic; +signal output_data : std_logic_vector (31 downto 0); + +signal bitcnt : integer range 0 to 31 := 31; + +type state_t is (IDLE, WAIT_FOR_CMD, GET_DATA, PREPARE_OUTPUT, WRITE_DATA, WAIT_FINISH); +signal state : state_t; + +signal buf_SPI_OUT : std_logic; + +begin + +spi_clk_last <= spi_clk_reg when rising_edge(CLK); +spi_clk_reg <= SPI_CLK when rising_edge(CLK); +spi_cs_reg <= SPI_CS when rising_edge(CLK); +spi_in_reg <= SPI_IN when rising_edge(CLK); + +DATA_OUT <= data_write; + +PROC_OUTPUT : process begin + wait until rising_edge(CLK); + next_output <= output_data(bitcnt); + if spi_clk_reg = '0' and spi_clk_last = '1' then + SPI_OUT <= last_input; + if operation_i = '0' and bitcnt <= 15 then + SPI_OUT <= next_output; + end if; + end if; +end process; + +PROC_INPUT_SHIFT : process begin + wait until rising_edge(CLK); + if spi_cs_reg = '1' then + bitcnt <= 31; + else + if spi_clk_reg = '1' and spi_clk_last = '0' then + if bitcnt /= 0 then + bitcnt <= bitcnt - 1; + else + bitcnt <= 31; + end if; + last_input <= spi_in_reg; + input(bitcnt) <= spi_in_reg; + end if; + end if; +end process; + +PROC_GEN_SIGNALS : process begin + wait until rising_edge(CLK); + --write_i <= (others => '0'); + READ_OUT <= '0'; + WRITE_OUT <= '0'; + case state is + when IDLE => + --operation_i <= x"0"; + if spi_cs_reg = '0' then + state <= WAIT_FOR_CMD; + end if; + + when WAIT_FOR_CMD => + if bitcnt = 22 then + operation_i <= input(23); + if (input(23) = '0') then + READ_OUT <= '1'; + else + WRITE_OUT <= '1'; + end if; + ADDR_OUT <= input(31 downto 24); + state <= GET_DATA; + end if; + + when GET_DATA => + state <= PREPARE_OUTPUT; + + when PREPARE_OUTPUT => + if READY_IN = '1' then + output_data(15 downto 0) <= DATA_IN; + end if; + state <= WRITE_DATA; + + when WRITE_DATA => + if bitcnt = 31 then + if operation_i = '1' then + WRITE_OUT <= '1'; + data_write <= input(15 downto 0); + --write_i(to_integer(unsigned(input(31 downto 28)))) <= '1'; + end if; + state <= WAIT_FINISH; + end if; + + when WAIT_FINISH => + WRITE_OUT <= '0'; + --if spi_cs_reg = '1' then + state <= IDLE; + --end if; + + end case; + + if spi_cs_reg = '1' then + state <= IDLE; + operation_i <= '0'; + end if; +end process; + +DEBUG(0) <= spi_clk_reg; +DEBUG(1) <= spi_cs_reg; +DEBUG(2) <= spi_in_reg; +DEBUG(3) <= buf_SPI_OUT; +DEBUG(7 downto 4) <= std_logic_vector(to_unsigned(bitcnt,4)); +DEBUG(14 downto 8) <= input(30 downto 24); +--DEBUG_OUT(15) <= write_i(4); + +end; \ No newline at end of file diff --git a/pinout/thresholds.lpf b/pinout/thresholds.lpf new file mode 100644 index 0000000..8c6a5a2 --- /dev/null +++ b/pinout/thresholds.lpf @@ -0,0 +1,42 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +#LOCATE COMP "rstn" SITE "B3" ; +LOCATE COMP "LED[0]" SITE "H11" ; +LOCATE COMP "LED[1]" SITE "J13" ; +LOCATE COMP "LED[2]" SITE "J11" ; +LOCATE COMP "LED[3]" SITE "L12" ; +LOCATE COMP "LED[4]" SITE "K11" ; +LOCATE COMP "LED[5]" SITE "L13" ; +LOCATE COMP "LED[6]" SITE "N15" ; +LOCATE COMP "LED[7]" SITE "P16" ; +#LOCATE COMP "DIPSW[0]" SITE "N2" ; +#LOCATE COMP "DIPSW[1]" SITE "P1" ; +#LOCATE COMP "DIPSW[2]" SITE "M3" ; +#LOCATE COMP "DIPSW[3]" SITE "N1" ; +#LOCATE COMP "clk_x1" SITE "C8" ; +#FREQUENCY PORT "clk_x1" 12.000000 MHz ; +#IOBUF PORT "clk_x1" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +#IOBUF PORT "DIPSW[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +#IOBUF PORT "DIPSW[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +#IOBUF PORT "DIPSW[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +#IOBUF PORT "DIPSW[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +#IOBUF PORT "rstn" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "LED[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "LED[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "LED[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "LED[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "LED[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "LED[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "LED[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "LED[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +SYSCONFIG MCCLK_FREQ=133 MASTER_SPI_PORT=DISABLE CONFIGURATION=CFG ; + +LOCATE COMP "MISO_OUT" SITE "A4"; +LOCATE COMP "MOSI_IN" SITE "B4"; +LOCATE COMP "SCLK_IN" SITE "B5"; +LOCATE COMP "CS_IN" SITE "B6"; + +IOBUF PORT "MISO_OUT" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "MOSI_IN" PULLMODE=DOWN IO_TYPE=LVCMOS33; +IOBUF PORT "SCLK_IN" PULLMODE=DOWN IO_TYPE=LVCMOS33; +IOBUF PORT "CS_IN" PULLMODE=DOWN IO_TYPE=LVCMOS33; \ No newline at end of file diff --git a/thresholds/config_compile_gsi.pl b/thresholds/config_compile_gsi.pl new file mode 100644 index 0000000..a356297 --- /dev/null +++ b/thresholds/config_compile_gsi.pl @@ -0,0 +1,26 @@ +Familyname => 'MachXO3LF', +Devicename => 'LCMXO3LF-6900C', +Package => 'CABGA256', +Speedgrade => '5', + +TOPNAME => "thresholds", +lm_license_file_for_synplify => "27000\@lxcad01.gsi.de", +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/opt/lattice/diamond/3.6_x64', +synplify_path => '/opt/synplicity/K-2015.09', +#synplify_command => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", +synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp", + +nodelist_file => 'nodelist_frankfurt.txt', + + +#Include only necessary lpf files +#pinout_file => '', #name of pin-out file, if not equal TOPNAME +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used +make_jed => 1, diff --git a/thresholds/thresholds.prj b/thresholds/thresholds.prj index d3897b3..34f9f15 100644 --- a/thresholds/thresholds.prj +++ b/thresholds/thresholds.prj @@ -4,20 +4,18 @@ #project files -add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesis/vhdl/machxo3lf.vhd" +#add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesis/vhdl/machxo3lf.vhd" #add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" -add_file -vhdl -lib work "../../logicbox/code/uart_sctrl.vhd" +add_file -vhdl -lib work "../../dirich/code/spi_slave.vhd" add_file -vhdl -lib work "../../logicbox/code/sedcheck.vhd" add_file -vhdl -lib work "../../mdcfee/code/pwm.vhd" -add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" -add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" -add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd" -add_file -vhdl -lib work "../../logicbox/cores/efb.vhd" -add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v" -add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v" +#add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd" +#add_file -vhdl -lib work "../../logicbox/cores/efb.vhd" +#add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v" +#add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v" add_file -vhdl -lib work "thresholds.vhd" @@ -37,8 +35,8 @@ set_option -job par_1 -add par #device options set_option -technology MACHXO3LF -set_option -part LCMXO3LF_4300E -set_option -package UWG81CTR +set_option -part LCMXO3LF_6900C +set_option -package BG256C set_option -speed_grade -5 set_option -part_companion "" diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd index 33a5c59..f219a07 100644 --- a/thresholds/thresholds.vhd +++ b/thresholds/thresholds.vhd @@ -10,28 +10,28 @@ use work.trb_net_std.all; entity thresholds is port( - CLK : in std_logic; + --CLK : in std_logic; OUTPUT : out std_logic_vector(15 downto 0); - TX_IN : in std_logic; - RX_OUT : out std_logic --- MISO_OUT : out std_logic; --- MOSI_IN : in std_logic; --- SCLK_IN : in std_logic; --- CS_IN : in std_logic + MISO_OUT : out std_logic; + MOSI_IN : in std_logic; + SCLK_IN : in std_logic; + CS_IN : in std_logic; + + LED : out std_logic_vector(7 downto 0) ); end entity; architecture arch of thresholds is signal clk_osc, clk_i : std_logic; - signal uart_rx_data : std_logic_vector(31 downto 0); - signal uart_tx_data : std_logic_vector(31 downto 0); - signal uart_addr : std_logic_vector(7 downto 0); + signal spi_rx_data : std_logic_vector(15 downto 0); + signal spi_tx_data : std_logic_vector(15 downto 0); + signal spi_addr : std_logic_vector(7 downto 0); signal bus_read : std_logic := '0'; signal bus_write : std_logic := '0'; signal bus_ready : std_logic; - signal uart_busy : std_logic; + signal spi_busy : std_logic; signal sed_error : std_logic; signal sed_debug : std_logic_vector(31 downto 0); @@ -58,7 +58,8 @@ architecture arch of thresholds is signal flash_go : std_logic; signal flash_busy : std_logic; signal flash_err : std_logic; - + + signal dummy_register : std_logic_vector(15 downto 0); component OSCH generic (NOM_FREQ: string := "33.25"); @@ -90,7 +91,7 @@ architecture arch of thresholds is begin - +LED <= dummy_register(7 downto 0); --------------------------------------------------------------------------- -- Clock --------------------------------------------------------------------------- @@ -107,45 +108,49 @@ clk_i <= clk_osc; --------------------------------------------------------------------------- -- UART --------------------------------------------------------------------------- -THE_UART : entity work.uart_sctrl - generic map( - CLOCK_SPEED => 133000000 - ) +THE_SPI : entity work.spi_slave port map( CLK => clk_i, - RESET => '0', - UART_RX => TX_IN, - UART_TX => RX_OUT, - - DATA_OUT => uart_rx_data, - DATA_IN => uart_tx_data, - ADDR_OUT => uart_addr, + SPI_CLK => SCLK_IN, + SPI_CS => CS_IN , + SPI_IN => MOSI_IN, + SPI_OUT => MISO_OUT, + + DATA_OUT => spi_rx_data, + DATA_IN => spi_tx_data, + ADDR_OUT => spi_addr, WRITE_OUT => bus_write, READ_OUT => bus_read, READY_IN => bus_ready, DEBUG => open ); - - + + PROC_REGS : process begin wait until rising_edge(clk_i); bus_ready <= '0'; pwm_write_i<= '0'; if bus_read = '1' then bus_ready <= '1'; - case uart_addr is - when x"ee" => uart_tx_data <= sed_debug; + case spi_addr is + when x"ee" => spi_tx_data <= sed_debug(15 downto 0); + when x"ef" => spi_tx_data <= sed_debug(31 downto 16); + + when x"e4" => spi_tx_data <= dummy_register; + end case; elsif bus_write = '1' then - if uart_addr < x"10" then - pwm_data_i <= uart_rx_data(15 downto 0); - pwm_addr_i <= uart_addr(4 downto 0); + if spi_addr < x"10" then + pwm_data_i <= spi_rx_data(15 downto 0); + pwm_addr_i <= spi_addr(4 downto 0); pwm_write_i<= '1'; else - case uart_addr is --- when x"10" => reg <= uart_rx_data; - when x"ee" => controlsed_i <= uart_rx_data(3 downto 0); + case spi_addr is +-- when x"10" => reg <= spi_rx_data; + when x"ee" => controlsed_i <= spi_rx_data(3 downto 0); + + when x"e4" => dummy_register <= spi_rx_data ; end case; end if; end if; @@ -182,43 +187,43 @@ THE_PWM_GEN : entity work.pwm_generator -- Flash Controller --------------------------------------------------------------------------- -THE_FLASH_RAM : entity work.flashram - port map( - DataInA => ram_data_i, - AddressA => ram_addr_i, - ClockA => clk_i, - ClockEnA => '1', - WrA => ram_write_i, - ResetA => '0', - QA => ram_data_o, - - DataInB => flashram_data_i, - AddressB => flashram_addr_i, - ClockB => clk_i, - ClockEnB => flashram_cen_i, - WrB => flashram_write_i, - ResetB => flashram_reset, - QB => flashram_data_o - ); - - - -THE_FLASH : UFM_WB - port map( - clk_i => clk_i, - rst_n => '1', - cmd => flash_command, - ufm_page => flash_page, - GO => flash_go, - BUSY => flash_busy, - ERR => flash_err, - mem_clk => open, - mem_we => flashram_write_i, - mem_ce => flashram_cen_i, - mem_addr => flashram_addr_i, - mem_wr_data => flashram_data_i, - mem_rd_data => flashram_data_o - ); +-- THE_FLASH_RAM : entity work.flashram +-- port map( +-- DataInA => ram_data_i, +-- AddressA => ram_addr_i, +-- ClockA => clk_i, +-- ClockEnA => '1', +-- WrA => ram_write_i, +-- ResetA => '0', +-- QA => ram_data_o, +-- +-- DataInB => flashram_data_i, +-- AddressB => flashram_addr_i, +-- ClockB => clk_i, +-- ClockEnB => flashram_cen_i, +-- WrB => flashram_write_i, +-- ResetB => flashram_reset, +-- QB => flashram_data_o +-- ); +-- +-- +-- +-- THE_FLASH : UFM_WB +-- port map( +-- clk_i => clk_i, +-- rst_n => '1', +-- cmd => flash_command, +-- ufm_page => flash_page, +-- GO => flash_go, +-- BUSY => flash_busy, +-- ERR => flash_err, +-- mem_clk => open, +-- mem_we => flashram_write_i, +-- mem_ce => flashram_cen_i, +-- mem_addr => flashram_addr_i, +-- mem_wr_data => flashram_data_i, +-- mem_rd_data => flashram_data_o +-- ); end architecture;