From: local account <adrian@lxhadeb07.gsi.de>
Date: Thu, 8 Mar 2018 16:16:33 +0000 (+0100)
Subject: pwm with 133MHz
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5a151f578821bee871a4f6022ad62123ed6c2559;p=dirich.git

pwm with 133MHz
---

diff --git a/thresholds/thresholds.prj b/thresholds/thresholds.prj
index c68aaaa..f992814 100644
--- a/thresholds/thresholds.prj
+++ b/thresholds/thresholds.prj
@@ -17,6 +17,7 @@ add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB_16bit.v"
 
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/generic_flash_ctrl.vhd"
 add_file -vhdl -lib work "thresholds.vhd"
+add_file -vhdl -lib work "../cores/pll_in133_out33_133_66.vhd"
 
 
 
diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd
index d06996f..f4df69a 100644
--- a/thresholds/thresholds.vhd
+++ b/thresholds/thresholds.vhd
@@ -26,7 +26,7 @@ architecture arch of thresholds is
   type ram_t is array (15 downto 0) of std_logic_vector(15 downto 0);
   signal ram_data : ram_t := (others =>("0000000000100001"));
   
-  signal clk_osc, clk_i : std_logic;
+  signal clk_i, clk_osc, clk_33,clk_66 : std_logic;
 
   signal spi_rx_data : std_logic_vector(15 downto 0);
   signal spi_tx_data : std_logic_vector(15 downto 0);
@@ -72,21 +72,31 @@ begin
 -- Clock
 ---------------------------------------------------------------------------
 clk_source: OSCH
-  generic map ( NOM_FREQ => "33.25" )
+  generic map ( NOM_FREQ => "133.0" )
   port map (
     STDBY    => '0',
     OSC      => clk_osc,
     SEDSTDBY => open
   );
 
-clk_i <= clk_osc;  
-  
+--clk_i <= clk_osc;  
+
+
+THE_PLL : entity work.pll_in133_out33_133_66
+  port map (
+     CLKI => clk_osc,
+     CLKOP => clk_i, --133
+     CLKOS => clk_33, --33
+     CLKOS2=> clk_66  --66
+  );  
+
+
 ---------------------------------------------------------------------------
 -- SPI
 ---------------------------------------------------------------------------
 THE_SPI : entity work.spi_slave
   port map(
-    CLK       => clk_i,
+    CLK       => clk_33,
 
     SPI_CLK   => SCLK_IN,
     SPI_CS    => CS_IN ,
@@ -113,8 +123,8 @@ THE_SPI : entity work.spi_slave
 THE_FLASH_CONTROLLER : entity generic_flash_ctrl
   port map(
 
-    CLK_f => clk_i,
-    CLK_l => clk_i,
+    CLK_f => clk_33,
+    CLK_l => clk_33,
     RESET => '0',
     
     SPI_DATA_IN   => spi_data_out,
@@ -136,7 +146,7 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl
   );  
 
 PROC_REGS : process begin
-  wait until rising_edge(clk_i);
+  wait until rising_edge(clk_33);
   bus_ready     <= '0';
   pwm_write     <= '0';
   
@@ -180,7 +190,7 @@ THE_SED : entity work.sedcheck
     DEV_DENSITY =>"4300L"
     )
   port map(
-    CLK        => clk_i,
+    CLK        => clk_33,
     ERROR_OUT  => sed_error,
     
     CONTROL_IN => controlsed_i,