From: hadeshyp Date: Wed, 11 Jul 2007 14:50:07 +0000 (+0000) Subject: updating trb_net_med_8bit_fast.vhd and components, Jan X-Git-Tag: oldGBE~728 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5a20c0157b68afd4a6540b2c915ced68c6663f3e;p=trbnet.git updating trb_net_med_8bit_fast.vhd and components, Jan --- diff --git a/trb_net_18_to_16_converter.vhd b/trb_net_18_to_16_converter.vhd index 070ffdf..a062c28 100644 --- a/trb_net_18_to_16_converter.vhd +++ b/trb_net_18_to_16_converter.vhd @@ -112,7 +112,7 @@ begin ----------------------------------------------------------- -next_buf_D18_READ_OUT <= dbuf18_next_read_out or dbuf18_comb_read_in; +next_buf_D18_READ_OUT <= dbuf18_next_read_out ;--and not D18_PACKET4; D18_READ_OUT <= buf_D18_READ_OUT; D18to16 : process(buffer_dbuf18_comb_data_in, dbuf18_comb_data_in, last_D18_PACKET4, @@ -133,11 +133,11 @@ D18_READ_OUT <= buf_D18_READ_OUT; if newdata = '1' and D18_PACKET_NUM_IN /= "00" then dbuf18_comb_data_in(7 downto 0) <= D18_DATA_IN(15 downto 8); else - dbuf18_comb_data_in(7 downto 0) <= (others => '0'); + dbuf18_comb_data_in(7 downto 0) <= D18_DATA_IN(15 downto 8);--(others => '0'); end if; if newdata = '1' or last_D18_PACKET4 = '1' then - dbuf18_comb_data_in(15 downto 8) <= buffer_dbuf18_comb_data_in; + dbuf18_comb_data_in(15 downto 8) <= buffer_dbuf18_comb_data_in(7 downto 0); if last_D18_PACKET4 = '0' then dbuf18_comb_data_in(17 downto 16) <= D18_PACKET_NUM_IN - 1; else @@ -188,7 +188,7 @@ D18_READ_OUT <= buf_D18_READ_OUT; CLK_EN => CLK_EN, COMB_DATAREADY_IN => dbuf18_comb_dataready_in, COMB_next_READ_OUT => dbuf18_next_read_out, - COMB_READ_IN => dbuf18_comb_read_in, + COMB_READ_IN => '1', COMB_DATA_IN => dbuf18_comb_data_in, -- Port to synchronous output. SYN_DATAREADY_OUT => D16_DATAREADY_OUT, @@ -201,16 +201,7 @@ D18_READ_OUT <= buf_D18_READ_OUT; D16_DATA_OUT <= buf_D16_DATA_OUT(15 downto 0); D16_PACKET_NUM_OUT <= buf_D16_DATA_OUT(17 downto 16); - dbuf18_read_in_gen : process(CLK, RESET) - begin - if RESET = '1' then - dbuf18_comb_read_in <= '0'; - elsif rising_edge(CLK) then - dbuf18_comb_read_in <= dbuf18_next_read_out; - else - dbuf18_comb_read_in <= dbuf18_comb_read_in; - end if; - end process; + ----------------------------------------------------------- diff --git a/trb_net_55_to_18_converter.vhd b/trb_net_55_to_18_converter.vhd index ed1b11f..305eb9b 100644 --- a/trb_net_55_to_18_converter.vhd +++ b/trb_net_55_to_18_converter.vhd @@ -1,3 +1,8 @@ +--this is a converter from 64/55 Bit to 18 Bit format. +--It's just a quick hack and should not be used in the final network +--for example, no packet number check is implemented and one cycle is wasted + + LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; @@ -121,18 +126,20 @@ begin end case; end process; - D18to55_fsm_reg : process(CLK, RESET) + D18to55_fsm_reg : process(CLK) begin - if RESET = '1' then - buf_D55_DATA_OUT <= (others => '0'); - D18to55_state <= IDLE; - buf_D55_DATAREADY_OUT <= '0'; - buf_D18_READ_OUT <= '0'; - elsif rising_edge(CLK) then - buf_D55_DATA_OUT <= next_D55_DATA_OUT; - D18to55_state <= next_D18to55_state; - buf_D55_DATAREADY_OUT <= next_D55_DATAREADY_OUT; - buf_D18_READ_OUT <= next_D18_READ_OUT; + if rising_edge(CLK) then + if RESET = '1' then + buf_D55_DATA_OUT <= (others => '0'); + D18to55_state <= IDLE; + buf_D55_DATAREADY_OUT <= '0'; + buf_D18_READ_OUT <= '0'; + else + buf_D55_DATA_OUT <= next_D55_DATA_OUT; + D18to55_state <= next_D18to55_state; + buf_D55_DATAREADY_OUT <= next_D55_DATAREADY_OUT; + buf_D18_READ_OUT <= next_D18_READ_OUT; + end if; else buf_D55_DATA_OUT <= buf_D55_DATA_OUT; D18to55_state <= D18to55_state; @@ -217,22 +224,24 @@ D18_READ_OUT <= buf_D18_READ_OUT; end process; - D55to18_fsm_reg : process(CLK, RESET) + D55to18_fsm_reg : process(CLK) begin - if RESET = '1' then - buf_D18_DATA_OUT <= (others => '0'); - buf_D55_DATA_IN <= (others => '0'); - buf_D55_READ_OUT <= '0'; - buf_D18_DATAREADY_OUT <= '0'; - buf_D18_PACKET_NUM_OUT <= "00"; - D55to18_state <= IDLE; - elsif rising_edge(CLK) then - buf_D18_DATA_OUT <= next_D18_DATA_OUT; - buf_D18_DATAREADY_OUT <= next_D18_DATAREADY_OUT; - buf_D55_READ_OUT <= next_D55_READ_OUT; - buf_D55_DATA_IN <= next_buf_D55_DATA_IN; - buf_D18_PACKET_NUM_OUT <= next_D18_PACKET_NUM_OUT; - D55to18_state <= next_D55to18_state; + if rising_edge(CLK) then + if RESET = '1' then + buf_D18_DATA_OUT <= (others => '0'); + buf_D55_DATA_IN <= (others => '0'); + buf_D55_READ_OUT <= '0'; + buf_D18_DATAREADY_OUT <= '0'; + buf_D18_PACKET_NUM_OUT <= "00"; + D55to18_state <= IDLE; + else + buf_D18_DATA_OUT <= next_D18_DATA_OUT; + buf_D18_DATAREADY_OUT <= next_D18_DATAREADY_OUT; + buf_D55_READ_OUT <= next_D55_READ_OUT; + buf_D55_DATA_IN <= next_buf_D55_DATA_IN; + buf_D18_PACKET_NUM_OUT <= next_D18_PACKET_NUM_OUT; + D55to18_state <= next_D55to18_state; + end if; else buf_D18_DATA_OUT <= buf_D18_DATA_OUT; buf_D18_DATAREADY_OUT <= buf_D18_DATAREADY_OUT; diff --git a/trb_net_med_8bit_fast.vhd b/trb_net_med_8bit_fast.vhd index 20d78a9..e3d6153 100644 --- a/trb_net_med_8bit_fast.vhd +++ b/trb_net_med_8bit_fast.vhd @@ -2,17 +2,52 @@ --with 8Bit data width plus 4 control Bits. --data is repacked to have 8 spare Bits in the end of each word instead on the --beginning. These Bits may be used for data integrity check later. ---CLK_LVDS is the clock used for transmission. Must be twice the normal CLK! +--The remaining four Bits on the LVDS cable are free to use at moment but should +--be reserved. ------------------------------------------------- --format on LVDS: 0-7 Data --- 8-11 not used, maybe for debugging +-- 8-11 free -- 12 first packet indicator -- 13 transmission clock --- 14 transmission carrier --- 15 transmission parity(0-7) +-- 14 carrier +-- 15 parity(0-7) ------------------------------------------------- +--Please check the timing report for setup/hold-errors on the receiving ports +--In case of an error, adjust the PHASE_SHIFT of the DCM. A change of one unit +--results in a shift of (CLK_PERIOD/256) +--If the timing seems to be correct but the trbnet trb_net doesn't react, try +--shifting the clock by 180 degrees. + + +-- +-- Constraints for timing on hadcom dev board: +-- NET "LVDS_IN<13>" TNM_NET = LVDS_IN_CLK_GRP; +-- TIMESPEC "TS_LVDS_IN" = PERIOD LVDS_IN_CLK_GRP 10 ns HIGH 50 %; +-- INST "LVDS_IN<*>" TNM = "IN_DDR"; +-- INST "LVDS_OUT<*>" TNM = "OUT_DDR"; +-- INST lvds1/buf_MED_IN_fal* TNM = "falling_reg"; +-- TIMEGRP "OUT_DDR" OFFSET = OUT 8 ns AFTER "CLK_IN"; +-- TIMEGRP "IN_DDR" OFFSET = IN -7 ns VALID 1 BEFORE "LVDS_IN<13>"; +-- TIMEGRP "IN_DDR" OFFSET = IN -2 ns VALID 1 BEFORE "LVDS_IN<13>" TIMEGRP "falling_reg"; + + +--Constraints for timing on acromag: +-- #Constraints for LVDS +-- NET "IO59_29P" TNM_NET = LVDS_IN_CLK_GRP; +-- TIMESPEC "TS_LVDS_IN" = PERIOD LVDS_IN_CLK_GRP 10 ns HIGH 50 %; +-- +-- INST "io*_*p" TNM = "IN_DDR"; +-- INST "io*_*n" TNM = "OUT_DDR"; +-- INST trbnetendpoint1/lvds1/buf_MED_IN_fal* TNM = "falling_reg"; +-- +-- TIMEGRP "IN_DDR" OFFSET = IN -7 ns VALID 1 ns BEFORE "IO59_29P"; +-- TIMEGRP "IN_DDR" OFFSET = IN -2 ns VALID 1 ns BEFORE "IO59_29P" TIMEGRP "falling_reg"; +-- TIMEGRP "OUT_DDR" OFFSET = OUT 6.7 ns AFTER "FPGA_CLK"; + + + LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; @@ -27,7 +62,6 @@ entity trb_net_med_8bit_fast is port( -- Misc CLK : in std_logic; - CLK_LVDS : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; @@ -57,23 +91,32 @@ entity trb_net_med_8bit_fast is MED_PARITY_IN: in STD_LOGIC; -- Status and control port => this never can hurt - STAT: out STD_LOGIC_VECTOR (31 downto 0); - --STAT(0): Busy reading from media - --STAT(1): Busy writing to media - --STAT(31 downto 28): packets_in (mod 16) - --STAT(27 downto 24): packets_out (mod 16) - --STAT(11 downto 8): INT2MED state - --STAT(15 downto 12): MED2INT state - - CTRL: in STD_LOGIC_VECTOR (31 downto 0) - --CTRL(24..31) -> lvds-data(63 downto 56) via lvds - --once for each packet + STAT: out STD_LOGIC_VECTOR(31 downto 0); + --31-16 show the current lvds data output (two times eight bit) + CTRL: in STD_LOGIC_VECTOR (31 downto 0) ); end entity; architecture trb_net_med_8bit_fast_arch of trb_net_med_8bit_fast is +component dualdatarate_flipflop + generic( + WIDTH : integer := 1 + ); + port( + C0 : in std_logic; + C1 : in std_logic; + CE : in std_logic; + CLR : in std_logic; + D0 : in std_logic_vector(WIDTH-1 downto 0); + D1 : in std_logic_vector(WIDTH-1 downto 0); + PRE : in std_logic; + Q : out std_logic_vector(WIDTH-1 downto 0) + ); +end component; + + component trb_net_fifo_16bit_bram_dualport port (read_clock_in: IN std_logic; write_clock_in: IN std_logic; @@ -118,38 +161,39 @@ component trb_net_18_to_16_converter D16_PACKET_NUM_IN: in STD_LOGIC_VECTOR(1 downto 0) ); end component; -component DCM + +--component DCM +---- +-- generic ( +-- DFS_FREQUENCY_MODE : string := "LOW"; +-- CLKFX_DIVIDE : integer := 4; -- Min 1 Max 32 (25MHz 3/4 M/D) +-- CLKFX_MULTIPLY : integer := 2 ; -- Min 2 Max 32 (60MHz 20/11 M/D) +---- CLKFX_MULTIPLY : integer := 3 ; -- Min 2 Max 32 (63MHz 19/10 M/D) +-- CLKIN_PERIOD : real := 10.0 ; -- 30.30ns +-- STARTUP_WAIT : boolean := FALSE +-- ); -- - generic ( - DFS_FREQUENCY_MODE : string := "LOW"; - CLKFX_DIVIDE : integer := 4; -- Min 1 Max 32 (25MHz 3/4 M/D) - CLKFX_MULTIPLY : integer := 2 ; -- Min 2 Max 32 (60MHz 20/11 M/D) --- CLKFX_MULTIPLY : integer := 3 ; -- Min 2 Max 32 (63MHz 19/10 M/D) - CLKIN_PERIOD : real := 10.0 ; -- 30.30ns - STARTUP_WAIT : boolean := FALSE - ); - - port ( CLKIN : in std_logic; - CLKFB : in std_logic; - DSSEN : in std_logic; - PSINCDEC : in std_logic; - PSEN : in std_logic; - PSCLK : in std_logic; - RST : in std_logic; - CLK0 : out std_logic; - CLK90 : out std_logic; - CLK180 : out std_logic; - CLK270 : out std_logic; - CLK2X : out std_logic; - CLK2X180 : out std_logic; - CLKDV : out std_logic; - CLKFX : out std_logic; - CLKFX180 : out std_logic; - LOCKED : out std_logic; - PSDONE : out std_logic; - STATUS : out std_logic_vector(7 downto 0) - ); -end component; +-- port ( CLKIN : in std_logic; +-- CLKFB : in std_logic; +-- DSSEN : in std_logic; +-- PSINCDEC : in std_logic; +-- PSEN : in std_logic; +-- PSCLK : in std_logic; +-- RST : in std_logic; +-- CLK0 : out std_logic; +-- CLK90 : out std_logic; +-- CLK180 : out std_logic; +-- CLK270 : out std_logic; +-- CLK2X : out std_logic; +-- CLK2X180 : out std_logic; +-- CLKDV : out std_logic; +-- CLKFX : out std_logic; +-- CLKFX180 : out std_logic; +-- LOCKED : out std_logic; +-- PSDONE : out std_logic; +-- STATUS : out std_logic_vector(7 downto 0) +-- ); +--end component; component trb_net_sbuf generic (DATA_WIDTH : integer := 16; VERSION: integer := 0); @@ -172,55 +216,61 @@ end component; ); END component; + component FDDRCPE + port ( + Q : out STD_ULOGIC; + C0 : in STD_ULOGIC; + C1 : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLR : in STD_ULOGIC; + D0 : in STD_ULOGIC; + D1 : in STD_ULOGIC; + PRE : in STD_ULOGIC); + end component; + signal CLK_TRANS : std_logic; signal fifo_data_in, next_fifo_data_in : std_logic_vector(17 downto 0); -signal next_next_fifo_data_in, buf_next_fifo_data_in : std_logic_vector(7 downto 0); +--signal next_next_fifo_data_in : std_logic_vector(7 downto 0); signal fifo_data_out : std_logic_vector(17 downto 0); signal fifo_full_out, fifo_empty_out : std_logic; signal fifo_status_out : std_logic_vector(3 downto 0); signal fifo_write_enable, next_fifo_write_enable : std_logic; signal fifo_read_enable, last_fifo_read_enable : std_logic; --signal fifo_data_buffer : std_logic_vector(15 downto 0); -signal next_packet_in_state, packet_in_state : std_logic; - +signal packet_in_state : std_logic; -signal buf_MED_PARITY_IN, buf_MED_CARRIER_IN : std_logic; -signal buf_MED_DATA_IN : std_logic_vector(12 downto 0); -signal buf_med_transmission_clk_in : std_logic; -signal buf_MED_PARITY_OUT, next_MED_PARITY_OUT : std_logic; -signal buf_MED_CARRIER_OUT, next_MED_CARRIER_OUT : std_logic; -signal buf_MED_TRANSMISSION_CLK_OUT, next_MED_TRANSMISSION_CLK_OUT : std_logic; -signal buf_MED_DATA_OUT, next_MED_DATA_OUT : std_logic_vector(12 downto 0); -signal data_valid, next_data_valid : std_logic; ---signal next_recv_data, recv_data : std_logic_vector(15 downto 0); +signal buf_MED_PARITY_OUT : std_logic; +signal buf_MED_CARRIER_OUT : std_logic; +signal buf_MED_TRANSMISSION_CLK_OUT : std_logic; +signal buf_MED_TRANSMISSION_CLK_IN : std_logic; +signal buf_MED_DATA_OUT : std_logic_vector(12 downto 0); +signal buf_MED_IN_fal : std_logic_vector(15 downto 0); +signal buf_MED_IN : std_logic_vector(31 downto 0); signal buf_INT_DATA_OUT : std_logic_vector(17 downto 0); -signal next_INT_DATAREADY_OUT, buf_INT_DATAREADY_OUT : std_logic; +signal buf_INT_DATAREADY_OUT : std_logic; signal next_int_packet_nr_out, buf_int_packet_nr_out : std_logic_vector(1 downto 0); -signal buf_INT_READ_OUT : std_logic; signal next_send_data_byte1, send_data_byte1 : std_logic_vector(7 downto 0); signal next_send_data_byte2, send_data_byte2 : std_logic_vector(7 downto 0); signal next_send_data_byte1_parity, send_data_byte1_parity : std_logic; signal next_send_data_byte2_parity, send_data_byte2_parity : std_logic; signal next_send_dataready, send_dataready : std_logic; -signal next_send_dataready1, send_dataready1 : std_logic; signal next_send_packet1, send_packet1 : std_logic; -signal next_fifo_data_ready, fifo_data_ready : std_logic; +signal fifo_data_ready : std_logic; ---signal recv_state, next_recv_state : std_logic_vector(1 downto 0); - -signal validbit, next_validbit : std_logic; signal buf_int_error_out, next_INT_ERROR_OUT : std_logic_vector(2 downto 0); signal CONV_DATAREADY_OUT : std_logic; signal CONV_DATA_OUT : std_logic_vector(15 downto 0); signal CONV_READ_IN: std_logic; -signal CONV_PACKET_NR_IN, CONV_PACKET_NR_OUT: std_logic_vector(1 downto 0); -signal CLK0_Out, FB_CLK, CLK2X_Out : std_logic; +signal CONV_PACKET_NR_OUT: std_logic_vector(1 downto 0); +signal FB_CLK, CLK_FB_Out, CLK_RECV_Out : std_logic; signal sbuff_status : std_logic; signal sbuff_next_read_out : std_logic; signal buf_comb_data_in : std_logic_vector(17 downto 0); + +signal DCM_LOCKED, RESET_RECV : std_logic; begin ----------------------------------------------------------------------- @@ -232,7 +282,7 @@ begin write_clock_in => CLK_TRANS, read_enable_in => fifo_read_enable, write_enable_in => fifo_write_enable, - fifo_gsr_in => RESET, + fifo_gsr_in => RESET_RECV, write_data_in => fifo_data_in, read_data_out => fifo_data_out, full_out => fifo_full_out, @@ -242,12 +292,6 @@ begin --- --- CONV_DATAREADY_OUT <= INT_DATAREADY_IN; --- CONV_DATA_OUT <= INT_DATA_IN; --- CONV_PACKET_NR_OUT <= INT_PACKET_NR_IN; --- INT_READ_OUT <= CONV_READ_IN; - CONV16to18 : trb_net_18_to_16_converter generic map( VERSION => 0 @@ -285,131 +329,115 @@ CONV16to18 : trb_net_18_to_16_converter -- Getting clock from LVDS ----------------------------------------------------------------------- -CLK_TRANS <= buf_MED_TRANSMISSION_CLK_IN; +-- CLK_TRANS <= not MED_TRANSMISSION_CLK_IN; +-- DCM_LOCKED <= '1'; - U4_BUFG: BUFG - port map ( - I => MED_TRANSMISSION_CLK_IN, - O => buf_MED_TRANSMISSION_CLK_IN - ); --- --- U_DCM: DCM --- generic map( --- CLKFX_DIVIDE => 1, -- Min 1 Max 32 --- CLKFX_MULTIPLY => 2, -- Min 2 Max 32 --- CLKIN_PERIOD => 20.20, -- 30.30ns --- STARTUP_WAIT => FALSE --- ) --- port map ( --- CLKIN => buf_MED_TRANSMISSION_CLK_IN, --- CLKFB => FB_CLK, --- DSSEN => '0', --- PSINCDEC => '0', --- PSEN => '0', --- PSCLK => '0', --- RST => RESET, --- CLK0 => CLK0_Out, -- for feedback --- CLK2X => CLK2X_Out --- ); --- --- -- BUFG Instantiation for CLKFX --- U0_BUFG: BUFG --- port map ( --- I => CLK2X_Out, --- O => CLK_TRANS --- ); --- -- BUFG Instantiation for CLK0 --- U1_BUFG: BUFG +-- U5_BUFG: BUFG -- port map ( --- I => CLK0_Out, --- O => FB_CLK +-- I => MED_TRANSMISSION_CLK_IN, +-- O => buf_MED_TRANSMISSION_CLK_IN -- ); +--the inverted clock is not really necessary,but helps sorting the data! + +U_DCM_RECV: DCM + generic map( + CLKIN_PERIOD => 10.00, -- 30.30ns + STARTUP_WAIT => FALSE, + DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", + PHASE_SHIFT => 30, + CLKOUT_PHASE_SHIFT => "FIXED" + ) + port map ( + CLKIN => MED_TRANSMISSION_CLK_IN, + CLKFB => FB_CLK, + DSSEN => '0', + PSINCDEC => '0', + PSEN => '0', + PSCLK => '0', + RST => RESET, + CLK0 => CLK_FB_Out, -- for feedback + CLK180=> CLK_RECV_Out, + LOCKED => DCM_LOCKED + ); +-- +U3_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); +U4_BUFG: BUFG port map (I => CLK_RECV_Out, O => CLK_TRANS); +--CLK_TRANS <= FB_CLK; ----------------------------------------------------------------------- -- Preparing incoming data for fifo ----------------------------------------------------------------------- - - ---BUG: No parity check for last part of packet, failure is passed to next packet! - - recv : process(packet_in_state, buf_MED_DATA_IN, buf_MED_CARRIER_IN, buf_MED_PARITY_IN, - data_valid, fifo_data_in) - --variable data_valid : std_logic; + recv : process(buf_MED_IN) begin - next_data_valid <= (buf_MED_PARITY_IN xnor xor_all(buf_MED_DATA_IN(7 downto 0))) - and (packet_in_state or data_valid); - next_fifo_write_enable <= buf_MED_CARRIER_IN AND NOT packet_in_state; - next_fifo_data_in(17) <= data_valid; - next_fifo_data_in(16) <= buf_MED_DATA_IN(12); - next_fifo_data_in(7 downto 0) <= fifo_data_in(7 downto 0); - next_fifo_data_in(15 downto 8) <= fifo_data_in(7 downto 0); - next_packet_in_state <= packet_in_state; - - if buf_MED_CARRIER_IN = '1' then - next_packet_in_state <= not packet_in_state; - next_fifo_data_in(7 downto 0) <= buf_MED_data_in(7 downto 0); - end if; + next_fifo_data_in(7 downto 0) <= buf_MED_IN(7 downto 0); + next_fifo_data_in(15 downto 8) <= buf_MED_IN(23 downto 16); + next_fifo_data_in(17) <= ((buf_MED_IN(15) xnor xor_all(buf_MED_IN(7 downto 0))) or not buf_MED_IN(14)) and + ((buf_MED_IN(31) xnor xor_all(buf_MED_IN(23 downto 16))) or not buf_MED_IN(30)); + --parity check + next_fifo_data_in(16) <= buf_MED_IN(12); --first packet + next_fifo_write_enable <= buf_MED_IN(14); --carrier end process; - recv_reg : process(CLK_TRANS, RESET) + + recv_reg : process(CLK_TRANS, RESET_RECV) begin - if RESET = '1' then + if RESET_RECV = '1' then fifo_write_enable <= '0'; - fifo_data_in <= (others => '0'); - packet_in_state <= '0'; + fifo_data_in(15 downto 0) <= (others => '0'); elsif rising_edge(CLK_TRANS) then - data_valid <= next_data_valid; fifo_write_enable <= next_fifo_write_enable; fifo_data_in <= next_fifo_data_in; - packet_in_state <= next_packet_in_state; else - data_valid <= data_valid; fifo_write_enable <= fifo_write_enable; fifo_data_in <= fifo_data_in; - packet_in_state <= packet_in_state; end if; end process; ----------------------------------------------------------------------- -- Reading data from LVDS ----------------------------------------------------------------------- --- --- --- -- buf_MED_PARITY_IN <= MED_PARITY_IN; --- -- buf_MED_CARRIER_IN <= MED_CARRIER_IN; --- -- buf_MED_DATA_IN <= MED_DATA_IN; --- - lvds_reg : process(CLK_TRANS, RESET) + + lvds_reg_rising : process(CLK_TRANS, RESET_RECV) begin - if RESET = '1' then - buf_MED_CARRIER_IN <= '0'; - buf_MED_PARITY_IN <= '0'; - buf_MED_DATA_IN(11 downto 0) <= (others => '0'); --12 is part of a shift register! + if RESET_RECV = '1' then + buf_MED_IN(31 downto 0) <= (others => '0'); elsif rising_edge(CLK_TRANS) then - buf_MED_CARRIER_IN <= MED_CARRIER_IN; - buf_MED_PARITY_IN <= MED_PARITY_IN; - buf_MED_DATA_IN <= MED_DATA_IN; + buf_MED_IN(14) <= MED_CARRIER_IN; + buf_MED_IN(15) <= MED_PARITY_IN; + buf_MED_IN(13) <= '0'; + buf_MED_IN(12 downto 0) <= MED_DATA_IN; + buf_MED_IN(31 downto 16) <= buf_MED_IN_fal; else - buf_MED_CARRIER_IN <= buf_MED_CARRIER_IN; - buf_MED_PARITY_IN <= buf_MED_PARITY_IN; - buf_MED_DATA_IN <= buf_MED_DATA_IN; + buf_MED_IN <= buf_MED_IN; end if; end process; - + lvds_reg_falling : process(CLK_TRANS, RESET_RECV) + begin + if RESET_RECV = '1' then + buf_MED_IN_fal(15 downto 0) <= (others => '0'); + elsif falling_edge(CLK_TRANS) then + buf_MED_IN_fal(14) <= MED_CARRIER_IN; + buf_MED_IN_fal(15) <= MED_PARITY_IN; + buf_MED_IN_fal(13) <= '1'; + buf_MED_IN_fal(12 downto 0) <= MED_DATA_IN; + else + buf_MED_IN_fal <= buf_MED_IN_fal; + end if; + end process; ----------------------------------------------------------------------- -- Reading data from fifo, offering to INT ----------------------------------------------------------------------- process(sbuff_next_read_out, fifo_empty_out, last_fifo_read_enable, - fifo_data_out, buf_int_packet_nr_out) + fifo_data_out, buf_int_packet_nr_out, DCM_LOCKED) begin fifo_read_enable <= sbuff_next_read_out and not fifo_empty_out; - + next_int_error_out <= ERROR_OK; if last_fifo_read_enable = '1' and fifo_data_out(16) = '1' then next_int_packet_nr_out <= "00"; @@ -421,7 +449,7 @@ CLK_TRANS <= buf_MED_TRANSMISSION_CLK_IN; if last_fifo_read_enable = '1' then --next_int_data_out <= fifo_data_out(15 downto 0); - next_int_dataready_out <= '1'; + --next_int_dataready_out <= '1'; if fifo_data_out(17) = '0' then next_int_error_out <= ERROR_FATAL; @@ -432,6 +460,9 @@ CLK_TRANS <= buf_MED_TRANSMISSION_CLK_IN; next_int_error_out <= ERROR_ENCOD; end if; end if; + if DCM_LOCKED = '0' then --without a locked clock -> no transmission possible + next_int_error_out <= ERROR_NC; + end if; end process; process(CLK,RESET) @@ -483,17 +514,19 @@ INT_ERROR_OUT <= buf_int_error_out; -- Sending data ----------------------------------------------------------------------- -CONV_READ_IN <= '1'; +CONV_READ_IN <= DCM_LOCKED; +RESET_RECV <= RESET or not DCM_LOCKED; + process(CONV_DATAREADY_OUT, CONV_DATA_OUT, CONV_PACKET_NR_OUT, CONV_READ_IN, send_data_byte1, send_data_byte2, send_packet1) begin next_send_dataready <= '0'; - next_send_data_byte1 <= send_data_byte1; - next_send_data_byte2 <= send_data_byte2; - next_send_data_byte1_parity <= '0'; - next_send_data_byte2_parity <= '0'; + next_send_data_byte1 <= (others => '0'); --send_data_byte1; + next_send_data_byte2 <= (others => '0'); --send_data_byte2; + next_send_data_byte1_parity <= '0'; --send_data_byte1_parity; + next_send_data_byte2_parity <= '0'; --send_data_byte2_parity; next_send_packet1 <= '0'; if CONV_DATAREADY_OUT = '1' and CONV_READ_IN = '1' then if CONV_PACKET_NR_OUT = "00" and send_packet1 = '0' then @@ -519,12 +552,12 @@ CONV_READ_IN <= '1'; send_dataready <= '0'; send_packet1 <= '0'; elsif rising_edge(CLK) then - send_data_byte1 <= next_send_data_byte1; - send_data_byte2 <= next_send_data_byte2; - send_data_byte1_parity <= next_send_data_byte1_parity; - send_data_byte2_parity <= next_send_data_byte2_parity; - send_dataready <= next_send_dataready; - send_packet1 <= next_send_packet1; + send_data_byte1 <= next_send_data_byte1 after 1 ns; + send_data_byte2 <= next_send_data_byte2 after 1 ns; + send_data_byte1_parity <= next_send_data_byte1_parity after 1 ns; + send_data_byte2_parity <= next_send_data_byte2_parity after 1 ns; + send_dataready <= next_send_dataready after 1 ns; + send_packet1 <= next_send_packet1 after 1 ns; else send_data_byte1 <= send_data_byte1; send_data_byte2 <= send_data_byte2; @@ -534,66 +567,90 @@ CONV_READ_IN <= '1'; send_packet1 <= send_packet1; end if; end process; - - process(send_dataready, send_data_byte1, send_data_byte2, - send_dataready1, send_data_byte1_parity, send_data_byte2_parity, - send_packet1, buf_INT_DATAREADY_OUT, INT_READ_IN, data_valid) - begin - next_MED_DATA_OUT(9 downto 8) <= (others => '0'); - next_MED_DATA_OUT(12) <= send_packet1; - next_MED_DATA_OUT(11) <= buf_INT_DATAREADY_OUT and INT_READ_IN; - next_MED_DATA_OUT(10) <= data_valid; - - - if send_dataready1 = '1' then - next_MED_DATA_OUT(7 downto 0) <= send_data_byte2; - next_MED_PARITY_OUT <= send_data_byte2_parity; - next_MED_CARRIER_OUT <= '1'; - next_send_dataready1 <= '0'; - elsif send_dataready = '1' then - next_MED_DATA_OUT(7 downto 0) <= send_data_byte1; - next_MED_PARITY_OUT <= send_data_byte1_parity; - next_MED_CARRIER_OUT <= '1'; - next_send_dataready1 <= '1'; - else - next_MED_DATA_OUT(7 downto 0) <= (others => '0'); - next_MED_CARRIER_OUT <= '0'; - next_MED_PARITY_OUT <= '0'; - next_send_dataready1 <= '0'; - end if; - end process; - - process(CLK_LVDS, RESET) + +ddr_ff_dat : dualdatarate_flipflop + generic map( + WIDTH => 8 + ) + port map( + Q => buf_MED_DATA_OUT(7 downto 0), + C0 => CLK, + C1 => not CLK, + CE => '1', + CLR => '0', + D0 => send_data_byte2, + D1 => send_data_byte1, + PRE => '0' + ); + +ddr_ff_parity : dualdatarate_flipflop + generic map( + WIDTH => 1 + ) + port map( + Q(0) => buf_MED_PARITY_OUT, + C0 => CLK, + C1 => not CLK, + CE => '1', + CLR => '0', + D0(0) => send_data_byte2_parity, + D1(0) => send_data_byte1_parity, + PRE => '0' + ); + +ddr_ff_clk : dualdatarate_flipflop + generic map( + WIDTH => 1 + ) + port map( + Q(0) => buf_MED_TRANSMISSION_CLK_OUT, + C0 => CLK, + C1 => not CLK, + CE => '1', + CLR => '0', + D0(0) => '1', + D1(0) => '0', + PRE => '0' + ); + + process(CLK, RESET) begin if RESET = '1' then - buf_MED_DATA_OUT <= (others => '0'); + buf_MED_DATA_OUT(12) <= '0'; buf_MED_CARRIER_OUT <= '0'; - buf_MED_PARITY_OUT <= '0'; - send_dataready1 <= '0'; - elsif falling_edge(CLK_LVDS) then - buf_MED_DATA_OUT <= next_MED_DATA_OUT; - buf_MED_CARRIER_OUT <= next_MED_CARRIER_OUT; - buf_MED_PARITY_OUT <= next_MED_PARITY_OUT; - send_dataready1 <= next_send_dataready1; + elsif falling_edge(CLK) then + buf_MED_DATA_OUT(12) <= send_packet1; + buf_MED_CARRIER_OUT <= send_dataready; else - buf_MED_DATA_OUT <= buf_MED_DATA_OUT; + buf_MED_DATA_OUT(12) <= buf_MED_DATA_OUT(12); buf_MED_CARRIER_OUT <= buf_MED_CARRIER_OUT; - buf_MED_PARITY_OUT <= buf_MED_PARITY_OUT; - send_dataready1 <= send_dataready1; end if; end process; - + + +----------------------------------------------------------------------- +-- Output generation +----------------------------------------------------------------------- +STAT(23 downto 16) <= send_data_byte1; +STAT(31 downto 24) <= send_data_byte2; +STAT(15 downto 0) <= (others => '0'); + MED_PARITY_OUT <= buf_MED_PARITY_OUT; MED_CARRIER_OUT <= buf_MED_CARRIER_OUT; -MED_TRANSMISSION_CLK_OUT <= CLK_LVDS; -MED_DATA_OUT(7 downto 0) <= buf_MED_DATA_OUT(7 downto 0); +MED_TRANSMISSION_CLK_OUT <= buf_MED_TRANSMISSION_CLK_OUT; +MED_DATA_OUT(9 downto 0) <= buf_MED_DATA_OUT(9 downto 0); +MED_DATA_OUT(12) <= buf_MED_DATA_OUT(12); -MED_DATA_OUT(12 downto 8) <= buf_MED_DATA_OUT(12 downto 8); +--MED_DATA_OUT(8) <= '0'; --MED_DATA_OUT(12) <= buf_MED_DATA_OUT(12); --MED_DATA_OUT(9 downto 8) <= buf_int_packet_nr_out; --MED_DATA_OUT(11 downto 10) <= CONV_PACKET_NR_OUT; --MED_DATA_OUT(9) <= CLK_TRANS; --MED_DATA_OUT(8) <= buf_MED_TRANSMISSION_CLK_IN; +MED_DATA_OUT(10) <= fifo_data_in(0); +MED_DATA_OUT(11) <= fifo_data_in(17); +-- MED_DATA_OUT(10) <= CLK_TRANS; +-- MED_DATA_OUT(11) <= fifo_write_enable; end architecture; diff --git a/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd b/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd index fa43ecf..9f62d18 100644 --- a/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd +++ b/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd @@ -90,6 +90,7 @@ component MUXCY_L S: IN std_logic; LO: OUT std_logic); end component; +attribute BOX_TYPE of MUXCY_L : component is "BLACK_BOX"; component RAMB16_S18_S18 port ( @@ -112,6 +113,8 @@ component RAMB16_S18_S18 DOPA: OUT std_logic_vector(1 downto 0); DOPB: OUT std_logic_vector(1 downto 0)); end component; +attribute BOX_TYPE of RAMB16_S18_S18 : component is "BLACK_BOX"; + BEGIN read_enable <= read_enable_in;