From: hadaq <hadaq>
Date: Fri, 4 Nov 2011 15:03:39 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5ae9b765b5fe32e3aebdb06003376fe5634bc9cc;p=trb3.git

*** empty log message ***
---

diff --git a/base/cores/FIFO_32x512_NOreg.vhd b/base/cores/FIFO_32x512_NOreg.vhd
deleted file mode 100644
index 46a96be..0000000
--- a/base/cores/FIFO_32x512_NOreg.vhd
+++ /dev/null
@@ -1,1193 +0,0 @@
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module  Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -rdata_width 32 -no_enable -pe -1 -pf -1 -e 
-
--- Fri Nov  4 12:24:03 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity FIFO_32x512_NOreg is
-    port (
-        Data: in  std_logic_vector(31 downto 0); 
-        WrClock: in  std_logic; 
-        RdClock: in  std_logic; 
-        WrEn: in  std_logic; 
-        RdEn: in  std_logic; 
-        Reset: in  std_logic; 
-        RPReset: in  std_logic; 
-        Q: out  std_logic_vector(31 downto 0); 
-        Empty: out  std_logic; 
-        Full: out  std_logic);
-end FIFO_32x512_NOreg;
-
-architecture Structure of FIFO_32x512_NOreg is
-
-    -- internal signal declarations
-    signal invout_1: std_logic;
-    signal invout_0: std_logic;
-    signal w_g2b_xor_cluster_1: std_logic;
-    signal r_g2b_xor_cluster_1: std_logic;
-    signal w_gdata_0: std_logic;
-    signal w_gdata_1: std_logic;
-    signal w_gdata_2: std_logic;
-    signal w_gdata_3: std_logic;
-    signal w_gdata_4: std_logic;
-    signal w_gdata_5: std_logic;
-    signal w_gdata_6: std_logic;
-    signal w_gdata_7: std_logic;
-    signal w_gdata_8: std_logic;
-    signal wptr_0: std_logic;
-    signal wptr_1: std_logic;
-    signal wptr_2: std_logic;
-    signal wptr_3: std_logic;
-    signal wptr_4: std_logic;
-    signal wptr_5: std_logic;
-    signal wptr_6: std_logic;
-    signal wptr_7: std_logic;
-    signal wptr_8: std_logic;
-    signal wptr_9: std_logic;
-    signal r_gdata_0: std_logic;
-    signal r_gdata_1: std_logic;
-    signal r_gdata_2: std_logic;
-    signal r_gdata_3: std_logic;
-    signal r_gdata_4: std_logic;
-    signal r_gdata_5: std_logic;
-    signal r_gdata_6: std_logic;
-    signal r_gdata_7: std_logic;
-    signal r_gdata_8: std_logic;
-    signal rptr_0: std_logic;
-    signal rptr_1: std_logic;
-    signal rptr_2: std_logic;
-    signal rptr_3: std_logic;
-    signal rptr_4: std_logic;
-    signal rptr_5: std_logic;
-    signal rptr_6: std_logic;
-    signal rptr_7: std_logic;
-    signal rptr_8: std_logic;
-    signal rptr_9: std_logic;
-    signal w_gcount_0: std_logic;
-    signal w_gcount_1: std_logic;
-    signal w_gcount_2: std_logic;
-    signal w_gcount_3: std_logic;
-    signal w_gcount_4: std_logic;
-    signal w_gcount_5: std_logic;
-    signal w_gcount_6: std_logic;
-    signal w_gcount_7: std_logic;
-    signal w_gcount_8: std_logic;
-    signal w_gcount_9: std_logic;
-    signal r_gcount_0: std_logic;
-    signal r_gcount_1: std_logic;
-    signal r_gcount_2: std_logic;
-    signal r_gcount_3: std_logic;
-    signal r_gcount_4: std_logic;
-    signal r_gcount_5: std_logic;
-    signal r_gcount_6: std_logic;
-    signal r_gcount_7: std_logic;
-    signal r_gcount_8: std_logic;
-    signal r_gcount_9: std_logic;
-    signal w_gcount_r20: std_logic;
-    signal w_gcount_r0: std_logic;
-    signal w_gcount_r21: std_logic;
-    signal w_gcount_r1: std_logic;
-    signal w_gcount_r22: std_logic;
-    signal w_gcount_r2: std_logic;
-    signal w_gcount_r23: std_logic;
-    signal w_gcount_r3: std_logic;
-    signal w_gcount_r24: std_logic;
-    signal w_gcount_r4: std_logic;
-    signal w_gcount_r25: std_logic;
-    signal w_gcount_r5: std_logic;
-    signal w_gcount_r26: std_logic;
-    signal w_gcount_r6: std_logic;
-    signal w_gcount_r27: std_logic;
-    signal w_gcount_r7: std_logic;
-    signal w_gcount_r28: std_logic;
-    signal w_gcount_r8: std_logic;
-    signal w_gcount_r29: std_logic;
-    signal w_gcount_r9: std_logic;
-    signal r_gcount_w20: std_logic;
-    signal r_gcount_w0: std_logic;
-    signal r_gcount_w21: std_logic;
-    signal r_gcount_w1: std_logic;
-    signal r_gcount_w22: std_logic;
-    signal r_gcount_w2: std_logic;
-    signal r_gcount_w23: std_logic;
-    signal r_gcount_w3: std_logic;
-    signal r_gcount_w24: std_logic;
-    signal r_gcount_w4: std_logic;
-    signal r_gcount_w25: std_logic;
-    signal r_gcount_w5: std_logic;
-    signal r_gcount_w26: std_logic;
-    signal r_gcount_w6: std_logic;
-    signal r_gcount_w27: std_logic;
-    signal r_gcount_w7: std_logic;
-    signal r_gcount_w28: std_logic;
-    signal r_gcount_w8: std_logic;
-    signal r_gcount_w29: std_logic;
-    signal r_gcount_w9: std_logic;
-    signal empty_i: std_logic;
-    signal rRst: std_logic;
-    signal full_i: std_logic;
-    signal iwcount_0: std_logic;
-    signal iwcount_1: std_logic;
-    signal w_gctr_ci: std_logic;
-    signal iwcount_2: std_logic;
-    signal iwcount_3: std_logic;
-    signal co0: std_logic;
-    signal iwcount_4: std_logic;
-    signal iwcount_5: std_logic;
-    signal co1: std_logic;
-    signal iwcount_6: std_logic;
-    signal iwcount_7: std_logic;
-    signal co2: std_logic;
-    signal iwcount_8: std_logic;
-    signal iwcount_9: std_logic;
-    signal co4: std_logic;
-    signal wcount_9: std_logic;
-    signal co3: std_logic;
-    signal scuba_vhi: std_logic;
-    signal ircount_0: std_logic;
-    signal ircount_1: std_logic;
-    signal r_gctr_ci: std_logic;
-    signal ircount_2: std_logic;
-    signal ircount_3: std_logic;
-    signal co0_1: std_logic;
-    signal ircount_4: std_logic;
-    signal ircount_5: std_logic;
-    signal co1_1: std_logic;
-    signal ircount_6: std_logic;
-    signal ircount_7: std_logic;
-    signal co2_1: std_logic;
-    signal ircount_8: std_logic;
-    signal ircount_9: std_logic;
-    signal co4_1: std_logic;
-    signal rcount_9: std_logic;
-    signal co3_1: std_logic;
-    signal rden_i: std_logic;
-    signal cmp_ci: std_logic;
-    signal wcount_r0: std_logic;
-    signal wcount_r1: std_logic;
-    signal rcount_0: std_logic;
-    signal rcount_1: std_logic;
-    signal co0_2: std_logic;
-    signal wcount_r2: std_logic;
-    signal wcount_r3: std_logic;
-    signal rcount_2: std_logic;
-    signal rcount_3: std_logic;
-    signal co1_2: std_logic;
-    signal wcount_r4: std_logic;
-    signal wcount_r5: std_logic;
-    signal rcount_4: std_logic;
-    signal rcount_5: std_logic;
-    signal co2_2: std_logic;
-    signal w_g2b_xor_cluster_0: std_logic;
-    signal wcount_r7: std_logic;
-    signal rcount_6: std_logic;
-    signal rcount_7: std_logic;
-    signal co3_2: std_logic;
-    signal wcount_r8: std_logic;
-    signal empty_cmp_clr: std_logic;
-    signal rcount_8: std_logic;
-    signal empty_cmp_set: std_logic;
-    signal empty_d: std_logic;
-    signal empty_d_c: std_logic;
-    signal wren_i: std_logic;
-    signal cmp_ci_1: std_logic;
-    signal rcount_w0: std_logic;
-    signal rcount_w1: std_logic;
-    signal wcount_0: std_logic;
-    signal wcount_1: std_logic;
-    signal co0_3: std_logic;
-    signal rcount_w2: std_logic;
-    signal rcount_w3: std_logic;
-    signal wcount_2: std_logic;
-    signal wcount_3: std_logic;
-    signal co1_3: std_logic;
-    signal rcount_w4: std_logic;
-    signal rcount_w5: std_logic;
-    signal wcount_4: std_logic;
-    signal wcount_5: std_logic;
-    signal co2_3: std_logic;
-    signal r_g2b_xor_cluster_0: std_logic;
-    signal rcount_w7: std_logic;
-    signal wcount_6: std_logic;
-    signal wcount_7: std_logic;
-    signal co3_3: std_logic;
-    signal rcount_w8: std_logic;
-    signal full_cmp_clr: std_logic;
-    signal wcount_8: std_logic;
-    signal full_cmp_set: std_logic;
-    signal full_d: std_logic;
-    signal full_d_c: std_logic;
-    signal scuba_vlo: std_logic;
-
-    -- local component declarations
-    component AGEB2
-        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
-            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
-    end component;
-    component AND2
-        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
-    end component;
-    component CU2
-        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
-            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
-    end component;
-    component FADD2B
-        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
-            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
-            S0: out  std_logic; S1: out  std_logic);
-    end component;
-    component FD1P3BX
-        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
-            PD: in  std_logic; Q: out  std_logic);
-    end component;
-    component FD1P3DX
-        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
-            CD: in  std_logic; Q: out  std_logic);
-    end component;
-    component FD1S3BX
-        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
-            Q: out  std_logic);
-    end component;
-    component FD1S3DX
-        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
-            Q: out  std_logic);
-    end component;
-    component INV
-        port (A: in  std_logic; Z: out  std_logic);
-    end component;
-    component OR2
-        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
-    end component;
-    component ROM16X1A
-        generic (INITVAL : in std_logic_vector(15 downto 0));
-        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
-            AD0: in  std_logic; DO0: out  std_logic);
-    end component;
-    component VHI
-        port (Z: out  std_logic);
-    end component;
-    component VLO
-        port (Z: out  std_logic);
-    end component;
-    component XOR2
-        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
-    end component;
-    component PDPW16KC
-        generic (GSR : in String; CSDECODE_R : in String; 
-                CSDECODE_W : in String; REGMODE : in String; 
-                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
-        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
-            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
-            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
-            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
-            DI12: in  std_logic; DI13: in  std_logic; 
-            DI14: in  std_logic; DI15: in  std_logic; 
-            DI16: in  std_logic; DI17: in  std_logic; 
-            DI18: in  std_logic; DI19: in  std_logic; 
-            DI20: in  std_logic; DI21: in  std_logic; 
-            DI22: in  std_logic; DI23: in  std_logic; 
-            DI24: in  std_logic; DI25: in  std_logic; 
-            DI26: in  std_logic; DI27: in  std_logic; 
-            DI28: in  std_logic; DI29: in  std_logic; 
-            DI30: in  std_logic; DI31: in  std_logic; 
-            DI32: in  std_logic; DI33: in  std_logic; 
-            DI34: in  std_logic; DI35: in  std_logic; 
-            ADW0: in  std_logic; ADW1: in  std_logic; 
-            ADW2: in  std_logic; ADW3: in  std_logic; 
-            ADW4: in  std_logic; ADW5: in  std_logic; 
-            ADW6: in  std_logic; ADW7: in  std_logic; 
-            ADW8: in  std_logic; BE0: in  std_logic; BE1: in  std_logic; 
-            BE2: in  std_logic; BE3: in  std_logic; CEW: in  std_logic; 
-            CLKW: in  std_logic; CSW0: in  std_logic; 
-            CSW1: in  std_logic; CSW2: in  std_logic; 
-            ADR0: in  std_logic; ADR1: in  std_logic; 
-            ADR2: in  std_logic; ADR3: in  std_logic; 
-            ADR4: in  std_logic; ADR5: in  std_logic; 
-            ADR6: in  std_logic; ADR7: in  std_logic; 
-            ADR8: in  std_logic; ADR9: in  std_logic; 
-            ADR10: in  std_logic; ADR11: in  std_logic; 
-            ADR12: in  std_logic; ADR13: in  std_logic; 
-            CER: in  std_logic; CLKR: in  std_logic; CSR0: in  std_logic; 
-            CSR1: in  std_logic; CSR2: in  std_logic; RST: in  std_logic; 
-            DO0: out  std_logic; DO1: out  std_logic; 
-            DO2: out  std_logic; DO3: out  std_logic; 
-            DO4: out  std_logic; DO5: out  std_logic; 
-            DO6: out  std_logic; DO7: out  std_logic; 
-            DO8: out  std_logic; DO9: out  std_logic; 
-            DO10: out  std_logic; DO11: out  std_logic; 
-            DO12: out  std_logic; DO13: out  std_logic; 
-            DO14: out  std_logic; DO15: out  std_logic; 
-            DO16: out  std_logic; DO17: out  std_logic; 
-            DO18: out  std_logic; DO19: out  std_logic; 
-            DO20: out  std_logic; DO21: out  std_logic; 
-            DO22: out  std_logic; DO23: out  std_logic; 
-            DO24: out  std_logic; DO25: out  std_logic; 
-            DO26: out  std_logic; DO27: out  std_logic; 
-            DO28: out  std_logic; DO29: out  std_logic; 
-            DO30: out  std_logic; DO31: out  std_logic; 
-            DO32: out  std_logic; DO33: out  std_logic; 
-            DO34: out  std_logic; DO35: out  std_logic);
-    end component;
-    attribute MEM_LPC_FILE : string; 
-    attribute MEM_INIT_FILE : string; 
-    attribute RESETMODE : string; 
-    attribute GSR : string; 
-    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_32x512_NOreg.lpc";
-    attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
-    attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
-    attribute GSR of FF_101 : label is "ENABLED";
-    attribute GSR of FF_100 : label is "ENABLED";
-    attribute GSR of FF_99 : label is "ENABLED";
-    attribute GSR of FF_98 : label is "ENABLED";
-    attribute GSR of FF_97 : label is "ENABLED";
-    attribute GSR of FF_96 : label is "ENABLED";
-    attribute GSR of FF_95 : label is "ENABLED";
-    attribute GSR of FF_94 : label is "ENABLED";
-    attribute GSR of FF_93 : label is "ENABLED";
-    attribute GSR of FF_92 : label is "ENABLED";
-    attribute GSR of FF_91 : label is "ENABLED";
-    attribute GSR of FF_90 : label is "ENABLED";
-    attribute GSR of FF_89 : label is "ENABLED";
-    attribute GSR of FF_88 : label is "ENABLED";
-    attribute GSR of FF_87 : label is "ENABLED";
-    attribute GSR of FF_86 : label is "ENABLED";
-    attribute GSR of FF_85 : label is "ENABLED";
-    attribute GSR of FF_84 : label is "ENABLED";
-    attribute GSR of FF_83 : label is "ENABLED";
-    attribute GSR of FF_82 : label is "ENABLED";
-    attribute GSR of FF_81 : label is "ENABLED";
-    attribute GSR of FF_80 : label is "ENABLED";
-    attribute GSR of FF_79 : label is "ENABLED";
-    attribute GSR of FF_78 : label is "ENABLED";
-    attribute GSR of FF_77 : label is "ENABLED";
-    attribute GSR of FF_76 : label is "ENABLED";
-    attribute GSR of FF_75 : label is "ENABLED";
-    attribute GSR of FF_74 : label is "ENABLED";
-    attribute GSR of FF_73 : label is "ENABLED";
-    attribute GSR of FF_72 : label is "ENABLED";
-    attribute GSR of FF_71 : label is "ENABLED";
-    attribute GSR of FF_70 : label is "ENABLED";
-    attribute GSR of FF_69 : label is "ENABLED";
-    attribute GSR of FF_68 : label is "ENABLED";
-    attribute GSR of FF_67 : label is "ENABLED";
-    attribute GSR of FF_66 : label is "ENABLED";
-    attribute GSR of FF_65 : label is "ENABLED";
-    attribute GSR of FF_64 : label is "ENABLED";
-    attribute GSR of FF_63 : label is "ENABLED";
-    attribute GSR of FF_62 : label is "ENABLED";
-    attribute GSR of FF_61 : label is "ENABLED";
-    attribute GSR of FF_60 : label is "ENABLED";
-    attribute GSR of FF_59 : label is "ENABLED";
-    attribute GSR of FF_58 : label is "ENABLED";
-    attribute GSR of FF_57 : label is "ENABLED";
-    attribute GSR of FF_56 : label is "ENABLED";
-    attribute GSR of FF_55 : label is "ENABLED";
-    attribute GSR of FF_54 : label is "ENABLED";
-    attribute GSR of FF_53 : label is "ENABLED";
-    attribute GSR of FF_52 : label is "ENABLED";
-    attribute GSR of FF_51 : label is "ENABLED";
-    attribute GSR of FF_50 : label is "ENABLED";
-    attribute GSR of FF_49 : label is "ENABLED";
-    attribute GSR of FF_48 : label is "ENABLED";
-    attribute GSR of FF_47 : label is "ENABLED";
-    attribute GSR of FF_46 : label is "ENABLED";
-    attribute GSR of FF_45 : label is "ENABLED";
-    attribute GSR of FF_44 : label is "ENABLED";
-    attribute GSR of FF_43 : label is "ENABLED";
-    attribute GSR of FF_42 : label is "ENABLED";
-    attribute GSR of FF_41 : label is "ENABLED";
-    attribute GSR of FF_40 : label is "ENABLED";
-    attribute GSR of FF_39 : label is "ENABLED";
-    attribute GSR of FF_38 : label is "ENABLED";
-    attribute GSR of FF_37 : label is "ENABLED";
-    attribute GSR of FF_36 : label is "ENABLED";
-    attribute GSR of FF_35 : label is "ENABLED";
-    attribute GSR of FF_34 : label is "ENABLED";
-    attribute GSR of FF_33 : label is "ENABLED";
-    attribute GSR of FF_32 : label is "ENABLED";
-    attribute GSR of FF_31 : label is "ENABLED";
-    attribute GSR of FF_30 : label is "ENABLED";
-    attribute GSR of FF_29 : label is "ENABLED";
-    attribute GSR of FF_28 : label is "ENABLED";
-    attribute GSR of FF_27 : label is "ENABLED";
-    attribute GSR of FF_26 : label is "ENABLED";
-    attribute GSR of FF_25 : label is "ENABLED";
-    attribute GSR of FF_24 : label is "ENABLED";
-    attribute GSR of FF_23 : label is "ENABLED";
-    attribute GSR of FF_22 : label is "ENABLED";
-    attribute GSR of FF_21 : label is "ENABLED";
-    attribute GSR of FF_20 : label is "ENABLED";
-    attribute GSR of FF_19 : label is "ENABLED";
-    attribute GSR of FF_18 : label is "ENABLED";
-    attribute GSR of FF_17 : label is "ENABLED";
-    attribute GSR of FF_16 : label is "ENABLED";
-    attribute GSR of FF_15 : label is "ENABLED";
-    attribute GSR of FF_14 : label is "ENABLED";
-    attribute GSR of FF_13 : label is "ENABLED";
-    attribute GSR of FF_12 : label is "ENABLED";
-    attribute GSR of FF_11 : label is "ENABLED";
-    attribute GSR of FF_10 : label is "ENABLED";
-    attribute GSR of FF_9 : label is "ENABLED";
-    attribute GSR of FF_8 : label is "ENABLED";
-    attribute GSR of FF_7 : label is "ENABLED";
-    attribute GSR of FF_6 : label is "ENABLED";
-    attribute GSR of FF_5 : label is "ENABLED";
-    attribute GSR of FF_4 : label is "ENABLED";
-    attribute GSR of FF_3 : label is "ENABLED";
-    attribute GSR of FF_2 : label is "ENABLED";
-    attribute GSR of FF_1 : label is "ENABLED";
-    attribute GSR of FF_0 : label is "ENABLED";
-    attribute syn_keep : boolean;
-
-begin
-    -- component instantiation statements
-    AND2_t20: AND2
-        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
-    INV_1: INV
-        port map (A=>full_i, Z=>invout_1);
-
-    AND2_t19: AND2
-        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
-    INV_0: INV
-        port map (A=>empty_i, Z=>invout_0);
-
-    OR2_t18: OR2
-        port map (A=>Reset, B=>RPReset, Z=>rRst);
-
-    XOR2_t17: XOR2
-        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
-    XOR2_t16: XOR2
-        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
-    XOR2_t15: XOR2
-        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
-    XOR2_t14: XOR2
-        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
-    XOR2_t13: XOR2
-        port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
-    XOR2_t12: XOR2
-        port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
-    XOR2_t11: XOR2
-        port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
-    XOR2_t10: XOR2
-        port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
-    XOR2_t9: XOR2
-        port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
-    XOR2_t8: XOR2
-        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
-    XOR2_t7: XOR2
-        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
-    XOR2_t6: XOR2
-        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
-    XOR2_t5: XOR2
-        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
-    XOR2_t4: XOR2
-        port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
-    XOR2_t3: XOR2
-        port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
-    XOR2_t2: XOR2
-        port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
-    XOR2_t1: XOR2
-        port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
-    XOR2_t0: XOR2
-        port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
-    LUT4_23: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, 
-            AD1=>w_gcount_r28, AD0=>w_gcount_r29, 
-            DO0=>w_g2b_xor_cluster_0);
-
-    LUT4_22: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, 
-            AD1=>w_gcount_r24, AD0=>w_gcount_r25, 
-            DO0=>w_g2b_xor_cluster_1);
-
-    LUT4_21: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, 
-            AD0=>scuba_vlo, DO0=>wcount_r8);
-
-    LUT4_20: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, 
-            AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
-
-    LUT4_19: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, 
-            AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
-    LUT4_18: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, 
-            AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
-
-    LUT4_17: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, 
-            AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
-
-    LUT4_16: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
-            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
-
-    LUT4_15: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
-            AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
-
-    LUT4_14: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
-            AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
-
-    LUT4_13: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, 
-            AD1=>r_gcount_w28, AD0=>r_gcount_w29, 
-            DO0=>r_g2b_xor_cluster_0);
-
-    LUT4_12: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, 
-            AD1=>r_gcount_w24, AD0=>r_gcount_w25, 
-            DO0=>r_g2b_xor_cluster_1);
-
-    LUT4_11: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, 
-            AD0=>scuba_vlo, DO0=>rcount_w8);
-
-    LUT4_10: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, 
-            AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
-
-    LUT4_9: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, 
-            AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
-
-    LUT4_8: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, 
-            AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
-
-    LUT4_7: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, 
-            AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
-
-    LUT4_6: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
-            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
-
-    LUT4_5: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
-            AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
-
-    LUT4_4: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
-            AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
-
-    LUT4_3: ROM16X1A
-        generic map (initval=> X"0410")
-        port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
-            AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
-    LUT4_2: ROM16X1A
-        generic map (initval=> X"1004")
-        port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
-            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
-    LUT4_1: ROM16X1A
-        generic map (initval=> X"0140")
-        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
-            AD0=>scuba_vlo, DO0=>full_cmp_set);
-
-    LUT4_0: ROM16X1A
-        generic map (initval=> X"4001")
-        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
-            AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
-    pdp_ram_0_0_0: PDPW16KC
-        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
-        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
-        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
-            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
-            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
-            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
-            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
-            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
-            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
-            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
-            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
-            DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, 
-            DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, 
-            ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, 
-            ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, 
-            ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, 
-            BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, 
-            CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, 
-            ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, 
-            ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, 
-            ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, 
-            ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, 
-            CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, 
-            RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), 
-            DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), 
-            DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), 
-            DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, DO17=>open, 
-            DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), 
-            DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), 
-            DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), 
-            DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
-
-    FF_101: FD1P3BX
-        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
-            Q=>wcount_0);
-
-    FF_100: FD1P3DX
-        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_1);
-
-    FF_99: FD1P3DX
-        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_2);
-
-    FF_98: FD1P3DX
-        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_3);
-
-    FF_97: FD1P3DX
-        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_4);
-
-    FF_96: FD1P3DX
-        port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_5);
-
-    FF_95: FD1P3DX
-        port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_6);
-
-    FF_94: FD1P3DX
-        port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_7);
-
-    FF_93: FD1P3DX
-        port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_8);
-
-    FF_92: FD1P3DX
-        port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_9);
-
-    FF_91: FD1P3DX
-        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_0);
-
-    FF_90: FD1P3DX
-        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_1);
-
-    FF_89: FD1P3DX
-        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_2);
-
-    FF_88: FD1P3DX
-        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_3);
-
-    FF_87: FD1P3DX
-        port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_4);
-
-    FF_86: FD1P3DX
-        port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_5);
-
-    FF_85: FD1P3DX
-        port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_6);
-
-    FF_84: FD1P3DX
-        port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_7);
-
-    FF_83: FD1P3DX
-        port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_8);
-
-    FF_82: FD1P3DX
-        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_9);
-
-    FF_81: FD1P3DX
-        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_0);
-
-    FF_80: FD1P3DX
-        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_1);
-
-    FF_79: FD1P3DX
-        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_2);
-
-    FF_78: FD1P3DX
-        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_3);
-
-    FF_77: FD1P3DX
-        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_4);
-
-    FF_76: FD1P3DX
-        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_5);
-
-    FF_75: FD1P3DX
-        port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_6);
-
-    FF_74: FD1P3DX
-        port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_7);
-
-    FF_73: FD1P3DX
-        port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_8);
-
-    FF_72: FD1P3DX
-        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_9);
-
-    FF_71: FD1P3BX
-        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
-            Q=>rcount_0);
-
-    FF_70: FD1P3DX
-        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_1);
-
-    FF_69: FD1P3DX
-        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_2);
-
-    FF_68: FD1P3DX
-        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_3);
-
-    FF_67: FD1P3DX
-        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_4);
-
-    FF_66: FD1P3DX
-        port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_5);
-
-    FF_65: FD1P3DX
-        port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_6);
-
-    FF_64: FD1P3DX
-        port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_7);
-
-    FF_63: FD1P3DX
-        port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_8);
-
-    FF_62: FD1P3DX
-        port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_9);
-
-    FF_61: FD1P3DX
-        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_0);
-
-    FF_60: FD1P3DX
-        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_1);
-
-    FF_59: FD1P3DX
-        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_2);
-
-    FF_58: FD1P3DX
-        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_3);
-
-    FF_57: FD1P3DX
-        port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_4);
-
-    FF_56: FD1P3DX
-        port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_5);
-
-    FF_55: FD1P3DX
-        port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_6);
-
-    FF_54: FD1P3DX
-        port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_7);
-
-    FF_53: FD1P3DX
-        port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_8);
-
-    FF_52: FD1P3DX
-        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_9);
-
-    FF_51: FD1P3DX
-        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_0);
-
-    FF_50: FD1P3DX
-        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_1);
-
-    FF_49: FD1P3DX
-        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_2);
-
-    FF_48: FD1P3DX
-        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_3);
-
-    FF_47: FD1P3DX
-        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_4);
-
-    FF_46: FD1P3DX
-        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_5);
-
-    FF_45: FD1P3DX
-        port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_6);
-
-    FF_44: FD1P3DX
-        port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_7);
-
-    FF_43: FD1P3DX
-        port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_8);
-
-    FF_42: FD1P3DX
-        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_9);
-
-    FF_41: FD1S3DX
-        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
-    FF_40: FD1S3DX
-        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
-    FF_39: FD1S3DX
-        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
-    FF_38: FD1S3DX
-        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
-    FF_37: FD1S3DX
-        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
-    FF_36: FD1S3DX
-        port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
-    FF_35: FD1S3DX
-        port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
-    FF_34: FD1S3DX
-        port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
-    FF_33: FD1S3DX
-        port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
-    FF_32: FD1S3DX
-        port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
-    FF_31: FD1S3DX
-        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
-    FF_30: FD1S3DX
-        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
-    FF_29: FD1S3DX
-        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
-    FF_28: FD1S3DX
-        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
-    FF_27: FD1S3DX
-        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
-    FF_26: FD1S3DX
-        port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
-    FF_25: FD1S3DX
-        port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
-    FF_24: FD1S3DX
-        port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
-    FF_23: FD1S3DX
-        port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
-    FF_22: FD1S3DX
-        port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
-    FF_21: FD1S3DX
-        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r20);
-
-    FF_20: FD1S3DX
-        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r21);
-
-    FF_19: FD1S3DX
-        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r22);
-
-    FF_18: FD1S3DX
-        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r23);
-
-    FF_17: FD1S3DX
-        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r24);
-
-    FF_16: FD1S3DX
-        port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r25);
-
-    FF_15: FD1S3DX
-        port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r26);
-
-    FF_14: FD1S3DX
-        port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r27);
-
-    FF_13: FD1S3DX
-        port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r28);
-
-    FF_12: FD1S3DX
-        port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r29);
-
-    FF_11: FD1S3DX
-        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
-    FF_10: FD1S3DX
-        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
-    FF_9: FD1S3DX
-        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
-    FF_8: FD1S3DX
-        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
-    FF_7: FD1S3DX
-        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
-    FF_6: FD1S3DX
-        port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
-    FF_5: FD1S3DX
-        port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
-    FF_4: FD1S3DX
-        port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
-    FF_3: FD1S3DX
-        port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
-    FF_2: FD1S3DX
-        port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
-    FF_1: FD1S3BX
-        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
-    FF_0: FD1S3DX
-        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
-    w_gctr_cia: FADD2B
-        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
-            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
-            S1=>open);
-
-    w_gctr_0: CU2
-        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
-            NC0=>iwcount_0, NC1=>iwcount_1);
-
-    w_gctr_1: CU2
-        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
-            NC0=>iwcount_2, NC1=>iwcount_3);
-
-    w_gctr_2: CU2
-        port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, 
-            NC0=>iwcount_4, NC1=>iwcount_5);
-
-    w_gctr_3: CU2
-        port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, 
-            NC0=>iwcount_6, NC1=>iwcount_7);
-
-    w_gctr_4: CU2
-        port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, 
-            NC0=>iwcount_8, NC1=>iwcount_9);
-
-    scuba_vhi_inst: VHI
-        port map (Z=>scuba_vhi);
-
-    r_gctr_cia: FADD2B
-        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
-            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
-            S1=>open);
-
-    r_gctr_0: CU2
-        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
-            NC0=>ircount_0, NC1=>ircount_1);
-
-    r_gctr_1: CU2
-        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
-            NC0=>ircount_2, NC1=>ircount_3);
-
-    r_gctr_2: CU2
-        port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, 
-            NC0=>ircount_4, NC1=>ircount_5);
-
-    r_gctr_3: CU2
-        port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, 
-            NC0=>ircount_6, NC1=>ircount_7);
-
-    r_gctr_4: CU2
-        port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, 
-            NC0=>ircount_8, NC1=>ircount_9);
-
-    empty_cmp_ci_a: FADD2B
-        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
-            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
-    empty_cmp_0: AGEB2
-        port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, 
-            B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
-    empty_cmp_1: AGEB2
-        port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, 
-            B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
-    empty_cmp_2: AGEB2
-        port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, 
-            B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
-    empty_cmp_3: AGEB2
-        port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, 
-            B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
-    empty_cmp_4: AGEB2
-        port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, 
-            B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
-
-    a0: FADD2B
-        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
-            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
-            S1=>open);
-
-    full_cmp_ci_a: FADD2B
-        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
-            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
-    full_cmp_0: AGEB2
-        port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, 
-            B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
-    full_cmp_1: AGEB2
-        port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, 
-            B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
-    full_cmp_2: AGEB2
-        port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, 
-            B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
-    full_cmp_3: AGEB2
-        port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, 
-            B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
-    full_cmp_4: AGEB2
-        port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, 
-            B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
-
-    scuba_vlo_inst: VLO
-        port map (Z=>scuba_vlo);
-
-    a1: FADD2B
-        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
-            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
-            S1=>open);
-
-    Empty <= empty_i;
-    Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of FIFO_32x512_NOreg is
-    for Structure
-        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
-        for all:AND2 use entity ecp3.AND2(V); end for;
-        for all:CU2 use entity ecp3.CU2(V); end for;
-        for all:FADD2B use entity ecp3.FADD2B(V); end for;
-        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
-        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
-        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
-        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
-        for all:INV use entity ecp3.INV(V); end for;
-        for all:OR2 use entity ecp3.OR2(V); end for;
-        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
-        for all:VHI use entity ecp3.VHI(V); end for;
-        for all:VLO use entity ecp3.VLO(V); end for;
-        for all:XOR2 use entity ecp3.XOR2(V); end for;
-        for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
-    end for;
-end Structure_CON;
-
--- synopsys translate_on
diff --git a/base/cores/bit_sync.vhd b/base/cores/bit_sync.vhd
deleted file mode 100644
index ab8ee6c..0000000
--- a/base/cores/bit_sync.vhd
+++ /dev/null
@@ -1,61 +0,0 @@
---synchronizes a single bit to a different clock domain
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-entity bit_sync is
-  generic(
-    DEPTH : integer := 3
-    );
-  port(
-    RESET : in  std_logic;  --Reset is neceessary to avoid optimization to shift register
-    CLK0  : in  std_logic;              --clock for first FF
-    CLK1  : in  std_logic;              --Clock for other FF
-    D_IN  : in  std_logic;  --Data input
-    D_OUT : out std_logic   --Data output
-    );
-end entity;
-
-architecture behavioral of bit_sync is
-
-  signal sync_q : std_logic_vector(DEPTH downto 0);
-
-  attribute syn_preserve           : boolean;
-  attribute syn_keep               : boolean;
-  attribute syn_keep of sync_q     : signal is true;
-  attribute syn_preserve of sync_q : signal is true;
-
-
-begin
-  sync_q(0) <= D_IN;
-  D_OUT     <= sync_q(DEPTH);
-
-  process(CLK0)
-  begin
-    if rising_edge(CLK0) then
-      if RESET = '1' then
-        sync_q(1) <= '0';
-      else
-        sync_q(1) <= sync_q(0);
-      end if;
-    end if;
-  end process;
-
-  gen_others : if DEPTH > 1 generate
-    gen_flipflops : for i in 2 to DEPTH generate
-      process(CLK1)
-      begin
-        if rising_edge(CLK1) then
-          if RESET = '1' then
-            sync_q(i) <= '0';
-          else
-            sync_q(i) <= sync_q(i-1);
-          end if;
-        end if;
-      end process;
-    end generate;
-  end generate;
-
-end architecture;
diff --git a/base/cores/edge_to_pulse_fast.vhd b/base/cores/edge_to_pulse_fast.vhd
deleted file mode 100644
index 46ab00c..0000000
--- a/base/cores/edge_to_pulse_fast.vhd
+++ /dev/null
@@ -1,61 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_arith.all;
-
-entity edge_to_pulse_fast is
-  port (
-    RESET     : in  std_logic;
-    CLK       : in  std_logic;
-    SIGNAL_IN : in  std_logic;
-    PULSE_OUT : out std_logic
-    );
-end edge_to_pulse_fast;
-
-architecture edge_to_pulse_fast of edge_to_pulse_fast is
-
-  signal clk_i    : std_logic;
-  signal rst_i    : std_logic;
-  signal signal_i : std_logic;
-  signal pulse_i  : std_logic;
-
-  signal signal_reg : std_logic;
-
-begin
-
-  clk_i    <= CLK;
-  rst_i    <= RESET;
-  signal_i <= SIGNAL_IN;
-
-  -- purpose: The SIGNAL_IN is delay by 1 clock cycle
-  Register_Signal_in : process (clk_i, rst_i)
-  begin
-    if rising_edge(clk_i) then
-      if rst_i = '1' then
-        signal_reg <= '0';
-      else
-        signal_reg <= signal_i;
-      end if;
-    end if;
-  end process Register_Signal_in;
-
-  -- purpose: Detection of the rising edge of the SIGNAL_IN
-  Detect_Rising_Edge : process (signal_i, signal_reg)
-  begin
-    pulse_i <= signal_i and not(signal_reg);
-  end process Detect_Rising_Edge;
-
-  -- purpose: The pulse is registered after the AND gate
-  Clock_Pulse_Out : process (clk_i, rst_i)
-  begin
-    if rising_edge(clk_i) then
-      if rst_i = '1' then
-        PULSE_OUT <= '0';
-      else
-        PULSE_OUT <= pulse_i;
-      end if;
-    end if;
-  end process Clock_Pulse_Out;
-
-end edge_to_pulse_fast;
diff --git a/base/cores/f_divider.vhd b/base/cores/f_divider.vhd
deleted file mode 100644
index 59eb530..0000000
--- a/base/cores/f_divider.vhd
+++ /dev/null
@@ -1,179 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_arith.all;
-use IEEE.STD_LOGIC_unsigned.all;
-
-
-entity f_divider is
-
-  generic(
-    cnt : integer := 4000  -- Der Teiler teilt durch "cnt" , wenn Test = 0  ist.  --
-    );
-
-  port (
-    clk     : in  std_logic;
-    ena_cnt : in  std_logic;
-    f_div   : out std_logic
-    );
-
-end f_divider;
-
-
-
-architecture arch_f_divider of f_divider is
-
-  function How_many_Bits (int : integer) return integer is
-    variable i, tmp           : integer;
-  begin
-    tmp   := int;
-    i     := 0;
-    while tmp > 0 loop
-      tmp := tmp / 2;
-      i   := i + 1;
-    end loop;
-    return i;
-  end How_many_bits;
-
-
-  --+          
-  --| Wie Breit muss der Teiler sein, um durch "cnt" teilen zu können?                                                  |
-  --+          
-  constant c_counter_width : integer := How_many_Bits(cnt - 2);
-
-  --+                                   ---------------------------------------------------------------------------------------------+
-  --| Des Zähler "s_counter" muss ein Bit breiter definiert werden, als zur Abarbeitung des "cnt"       |
-  --| nötig wäre. Dieses Bit wird beim Zählerunterlauf '1'. Der Zählerablauf wird dadurch ohne  |
-  --| Komparator erkannt, er steht als getaktetes physikalisches Signal zur Verfügung.                  |
-  --+                                   ---------------------------------------------------------------------------------------------+
-  signal s_counter : std_logic_vector(c_counter_width downto 0) := conv_std_logic_vector(0, c_counter_width+1);
-
-  --+                                   ---------------------------------------------------------------------------------------------+
-  --| Teiler muss mit einen um -2 geringeren Wert geladen werden. Da das Neuladen erst durch dem        |
-  --| Unterlauf Zählers erfolgt. D.h. die Null und minus Eins werden mitgezählt.                                        |
-  --+                                   ---------------------------------------------------------------------------------------------+
-  constant c_ld_value : integer := cnt - 2;
-
-begin
-  p_f_divider : process (clk)
-  begin
-    if clk'event and clk = '1' then
-      if s_counter(s_counter'high) = '1' then  -- Bei underflow wird neu geladen  --
-        s_counter   <= conv_std_logic_vector(c_ld_value, s_counter'length);
-      elsif ena_cnt = '1' then
-        if s_counter(s_counter'high) = '0' then  -- Kein underflow erreicht weiter  --
-          s_counter <= s_counter - 1;  -- subtrahieren.  --
-        end if;
-      end if;
-    end if;
-  end process p_f_divider;
-
-  f_div <= s_counter(s_counter'high);
-
-end arch_f_divider;
-
-
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-
---library synplify;
---use synplify.attributes.all;
-
-
-entity edge_to_pulse is
-
-  port (
-    clock     : in  std_logic;
-    en_clk    : in  std_logic;
-    signal_in : in  std_logic;
-    pulse     : out std_logic);
-
-end edge_to_pulse;
-
-architecture arch_edge_to_pulse of edge_to_pulse is
---  signal signal_sync               : std_logic;
---  signal old_sync                  : std_logic;
-  signal pulse_fsm                 : std_logic;
-  type state is (idle, high, wait_for_low);  -- state
-  signal current_state, next_state : state;
-
-begin  -- arch_edge_to_pulse
-
-  fsm : process (clock)
-  begin  -- process fsm
-    if rising_edge(clock) then          -- rising clock edge
-      if en_clk = '1' then
-        current_state <= next_state;
---        signal_sync   <= signal_in;
-        pulse         <= pulse_fsm;
-      end if;
-    end if;
-  end process fsm;
-
-
-  fsm_comb : process (current_state, signal_in)
-  begin  -- process fsm_comb
-    case current_state is
-      when idle         =>
-        pulse_fsm    <= '0';
-        if signal_in = '1' then
-          next_state <= high;
-        else
-          next_state <= idle;
-        end if;
---
-      when high         =>
-        pulse_fsm    <= '1';
-        next_state   <= wait_for_low;
--- when wait_for_low_1 =>
--- pulse <= '1';
--- next_state <= wait_for_low;
---
-      when wait_for_low =>
-        pulse_fsm    <= '0';
-        if signal_in = '0' then
-          next_state <= idle;
-        else
-          next_state <= wait_for_low;
-        end if;
---
-      when others       =>
-        pulse_fsm    <= '0';
-        next_state   <= idle;
-    end case;
-  end process fsm_comb;
-
-
-end arch_edge_to_pulse;
-
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-package support is
-
-  component f_divider
-    generic (
-      cnt     :     integer);
-    port (
-      clk     : in  std_logic;
-      ena_cnt : in  std_logic;
-      f_div   : out std_logic);
-  end component;
-
-  component edge_to_pulse
-    port (
-      clock     : in  std_logic;
-      en_clk    : in  std_logic;
-      signal_in : in  std_logic;
-      pulse     : out std_logic);
-  end component;
-  
-
-end support;
-
diff --git a/base/cores/signal_sync.vhd b/base/cores/signal_sync.vhd
deleted file mode 100644
index b0e5971..0000000
--- a/base/cores/signal_sync.vhd
+++ /dev/null
@@ -1,62 +0,0 @@
---synchronizes a signal to a different clock domain
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-entity signal_sync is
-  generic(
-    WIDTH : integer := 1;               --
-    DEPTH : integer := 3
-    );
-  port(
-    RESET : in  std_logic;  --Reset is neceessary to avoid optimization to shift register
-    CLK0  : in  std_logic;              --clock for first FF
-    CLK1  : in  std_logic;              --Clock for other FF
-    D_IN  : in  std_logic_vector(WIDTH-1 downto 0);  --Data input
-    D_OUT : out std_logic_vector(WIDTH-1 downto 0)   --Data output
-    );
-end entity;
-
-architecture behavioral of signal_sync is
-
-  signal sync_q : std_logic_vector((DEPTH+1)*WIDTH-1 downto 0);
-
-  attribute syn_preserve           : boolean;
-  attribute syn_keep               : boolean;
-  attribute syn_keep of sync_q     : signal is true;
-  attribute syn_preserve of sync_q : signal is true;
-
-
-begin
-  sync_q(WIDTH-1 downto 0) <= D_IN;
-  D_OUT                    <= sync_q((DEPTH+1)*WIDTH-1 downto DEPTH*WIDTH);
-
-  process(CLK0)
-  begin
-    if rising_edge(CLK0) then
-      if RESET = '1' then
-        sync_q(2*WIDTH-1 downto WIDTH) <= (others => '0');
-      else
-        sync_q(2*WIDTH-1 downto WIDTH) <= sync_q(WIDTH-1 downto 0);
-      end if;
-    end if;
-  end process;
-
-  gen_others : if DEPTH > 1 generate
-    gen_flipflops : for i in 2 to DEPTH generate
-      process(CLK1)
-      begin
-        if rising_edge(CLK1) then
-          if RESET = '1' then
-            sync_q((i+1)*WIDTH-1 downto i*WIDTH) <= (others => '0');
-          else
-            sync_q((i+1)*WIDTH-1 downto i*WIDTH) <= sync_q(i*WIDTH-1 downto (i-1)*WIDTH);
-          end if;
-        end if;
-      end process;
-    end generate;
-  end generate;
-
-end architecture;
diff --git a/base/cores/up_counter.vhd b/base/cores/up_counter.vhd
deleted file mode 100644
index 67c88d1..0000000
--- a/base/cores/up_counter.vhd
+++ /dev/null
@@ -1,39 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-entity up_counter is
-
-  generic (
-    NUMBER_OF_BITS :     positive);
-  port (
-    CLK            : in  std_logic;
-    RESET          : in  std_logic;
-    COUNT_OUT      : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
-    UP_IN          : in  std_logic);
-
-end up_counter;
-
-architecture up_counter of up_counter is
-
-signal counter: std_logic_vector (NUMBER_OF_BITS-1 downto 0);
-
-begin
-
-  COUNTER_PROC : process (CLK, RESET)
-  begin
-    if rising_edge(clk) then
-      if RESET = '1' then
-        counter <= (others => '0');
-      elsif UP_IN = '1' then
-        counter <= counter + 1;
-      else
-        counter <= counter;
-      end if;
-    end if;
-  end process COUNTER_PROC;
-
-  COUNT_OUT <= counter;
-
-end up_counter;
diff --git a/base/trb3_periph.prj b/base/trb3_periph.prj
index c70935e..9709709 100644
--- a/base/trb3_periph.prj
+++ b/base/trb3_periph.prj
@@ -137,19 +137,3 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.v
 
 add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
 add_file -vhdl -lib "work" "./trb3_periph.vhd"
-
-add_file -vhdl -lib "work" "../base/tdc_source_files/TDC.vhd"
-add_file -vhdl -lib "work" "../base/tdc_source_files/Adder_320.vhd"
-add_file -vhdl -lib "work" "../base/tdc_source_files/Channel_320.vhd"
-add_file -vhdl -lib "work" "../base/tdc_source_files/Encoder_320_Bit.vhd"
-add_file -vhdl -lib "work" "../base/cores/FIFO_32x512_NOreg.vhd"
-add_file -vhdl -lib "work" "../base/tdc_source_files/ROM_FIFO.vhd"
-add_file -vhdl -lib "work" "../base/cores/bit_sync.vhd"
-add_file -vhdl -lib "work" "../base/cores/edge_to_pulse_fast.vhd"
-add_file -vhdl -lib "work" "../base/cores/up_counter.vhd"
-
-
-
-
-
-
diff --git a/base/trb3_periph.vhd b/base/trb3_periph.vhd
index 7993618..f76e786 100644
--- a/base/trb3_periph.vhd
+++ b/base/trb3_periph.vhd
@@ -556,27 +556,4 @@ begin
     time_counter <= time_counter + 1;
   end process;
 
--------------------------------------------------------------------------------
--- TDC
--------------------------------------------------------------------------------
-
-  THE_TDC : TDC
-    generic map (
-      CHANNEL_NUMBER => 8)              -- Number of TDC channels
-    port map (
-      RESET             => reset_i,
-      CLK_TDC           => CLK_PCLK_LEFT,  -- Clock used for the time measurement
-      CLK_READOUT       => clk_100_i,   -- Clock for the readout
-      HIT_IN            => DQUL(7 downto 0),     -- Channel start signals
-      TRIGGER_IN        => trg_timing_valid_i,   -- Readout trigger
-      TRIGGER_WIN_IN    => x"00640000",  -- Trigger window register relative to
-                                         -- the trigger (post edge & pre edge)
-      DATA_OUT          => fee_data_i,  -- Data to readout
-      TRB_WR_CLK_OUT    => open,        -- Readout clk (maybe not necessary
-                                        -- in trb3)
-      DATA_VALID_OUT    => fee_data_write_i,     -- Data valid signal
-      DATA_FINISHED_OUT => fee_data_finished_i,  -- Readout finished signal
-      READY_OUT         => fee_trg_release_i,    -- Ready for the next trigger
-      TDC_DEBUG_00      => open);       -- Debug
-
 end architecture;
diff --git a/base/trb3_periph_constraints.lpf b/base/trb3_periph_constraints.lpf
index 957482f..aa9e43b 100644
--- a/base/trb3_periph_constraints.lpf
+++ b/base/trb3_periph_constraints.lpf
@@ -29,393 +29,3 @@ REGION "MEDIA_UPLINK" "R102C95D" 13 25;
 LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
 
 # REGION "REGION_ENDPOINT" "" ;
-
-
-
-
-#################################################################
-# TDC Constraints
-#################################################################
-##############################################################################
-##			     REGION DECLERATION                             ##
-##############################################################################
-REGION "Region_0" "R9C2D" 28 63 DEVSIZE;
-REGION "Region_1" "R37C2D" 21 63 DEVSIZE;
-REGION "Region_2" "R59C2D" 22 63 DEVSIZE;
-REGION "Region_3" "R81C2D" 24 63 DEVSIZE;
-REGION "Region_4" "R9C65D" 24 63 DEVSIZE;
-REGION "Region_5" "R33C65D" 24 63 DEVSIZE;
-REGION "Region_6" "R57C65D" 24 63 DEVSIZE;
-REGION "Region_7" "R81C65D" 24 63 DEVSIZE;
-##############################################################################
-##	            DELAY LINE and HIT BUFFER PLACEMENTS                    ##
-##############################################################################
-UGROUP "FC_0" BBOX 1 54 
-	BLKNAME TDC_INST/GEN_Channels_0_Channels/FC;
-LOCATE UGROUP "FC_0" SITE "R17C5D" ;
-UGROUP "hit_0" 
-	BLKNAME TDC_INST/GEN_Channels_0_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_0" SITE "R18C7D" ;
-#
-UGROUP "FC_1" BBOX 1 54 
-	BLKNAME TDC_INST/GEN_Channels_1_Channels/FC;
-LOCATE UGROUP "FC_1" SITE "R20C5D" ;
-UGROUP "hit_1" 
-	BLKNAME TDC_INST/GEN_Channels_1_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_1" SITE "R21C7D" ;
-#
-UGROUP "FC_2" BBOX 1 54 
-	BLKNAME TDC_INST/GEN_Channels_2_Channels/FC;
-LOCATE UGROUP "FC_2" SITE "R31C5D" ;
-UGROUP "hit_2" 
-	BLKNAME TDC_INST/GEN_Channels_2_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_2" SITE "R32C7D" ;
-#
-UGROUP "FC_3" BBOX 1 54 
-	BLKNAME TDC_INST/GEN_Channels_3_Channels/FC;
-LOCATE UGROUP "FC_3" SITE "R42C5D" ;
-UGROUP "hit_3" 
-	BLKNAME TDC_INST/GEN_Channels_3_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_3" SITE "R43C7D" ;
-#
-UGROUP "FC_4" BBOX 1 54 
-	BLKNAME TDC_INST/GEN_Channels_4_Channels/FC;
-LOCATE UGROUP "FC_4" SITE "R44C5D" ;
-UGROUP "hit_4" 
-	BLKNAME TDC_INST/GEN_Channels_4_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_4" SITE "R45C7D" ;
-#
-UGROUP "FC_5" BBOX 1 54 
-	BLKNAME TDC_INST/GEN_Channels_5_Channels/FC;
-LOCATE UGROUP "FC_5" SITE "R53C5D" ;
-UGROUP "hit_5" 
-	BLKNAME TDC_INST/GEN_Channels_5_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_5" SITE "R54C7D" ;
-#
-UGROUP "FC_6" BBOX 1 54 
-	BLKNAME TDC_INST/GEN_Channels_6_Channels/FC;
-LOCATE UGROUP "FC_6" SITE "R60C5D" ;
-UGROUP "hit_6" 
-	BLKNAME TDC_INST/GEN_Channels_6_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_6" SITE "R61C7D" ;
-#
-UGROUP "FC_7" BBOX 1 54 
-	BLKNAME TDC_INST/GEN_Channels_7_Channels/FC;
-LOCATE UGROUP "FC_7" SITE "R73C5D" ;
-UGROUP "hit_7" 
-	BLKNAME TDC_INST/GEN_Channels_7_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_7" SITE "R74C7D" ;
-#
-MAXDELAY NET "TDC_INST/GEN_Channels_0_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "TDC_INST/GEN_Channels_1_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "TDC_INST/GEN_Channels_2_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "TDC_INST/GEN_Channels_3_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "TDC_INST/GEN_Channels_4_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "TDC_INST/GEN_Channels_5_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "TDC_INST/GEN_Channels_6_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "TDC_INST/GEN_Channels_7_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-#MAXDELAY NET "TDC_INST/GEN_Channels_8_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-#MAXDELAY NET "TDC_INST/GEN_Channels_9_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-#MAXDELAY NET "TDC_INST/GEN_Channels_10_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-#MAXDELAY NET "TDC_INST/GEN_Channels_11_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-#MAXDELAY NET "TDC_INST/GEN_Channels_12_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-#MAXDELAY NET "TDC_INST/GEN_Channels_13_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-#MAXDELAY NET "TDC_INST/GEN_Channels_14_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-#MAXDELAY NET "TDC_INST/GEN_Channels_15_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-##############################################################################
-##			     CHANNEL PLACEMENTS                             ##
-##############################################################################
-UGROUP "Encoder_0" 
-	BLKNAME TDC_INST/GEN_Channels_0_Channels/Encoder;
-LOCATE UGROUP "Encoder_0" REGION "Region_0" ;
-UGROUP "FIFO_0" 
-	BLKNAME TDC_INST/GEN_Channels_0_Channels/FIFO;
-LOCATE UGROUP "FIFO_0" REGION "Region_0" ;
-UGROUP "Encoder_1" 
-	BLKNAME TDC_INST/GEN_Channels_1_Channels/Encoder;
-LOCATE UGROUP "Encoder_1" REGION "Region_0" ;
-UGROUP "FIFO_1" 
-	BLKNAME TDC_INST/GEN_Channels_1_Channels/FIFO;
-LOCATE UGROUP "FIFO_1" REGION "Region_0" ;
-UGROUP "Encoder_2" 
-	BLKNAME TDC_INST/GEN_Channels_2_Channels/Encoder;
-LOCATE UGROUP "Encoder_2" REGION "Region_0" ;
-UGROUP "FIFO_2" 
-	BLKNAME TDC_INST/GEN_Channels_2_Channels/FIFO;
-LOCATE UGROUP "FIFO_2" REGION "Region_0" ;
-UGROUP "Encoder_3" 
-	BLKNAME TDC_INST/GEN_Channels_3_Channels/Encoder;
-LOCATE UGROUP "Encoder_3" REGION "Region_1" ;
-UGROUP "FIFO_3" 
-	BLKNAME TDC_INST/GEN_Channels_3_Channels/FIFO;
-LOCATE UGROUP "FIFO_3" REGION "Region_1" ;
-UGROUP "Encoder_4" 
-	BLKNAME TDC_INST/GEN_Channels_4_Channels/Encoder;
-LOCATE UGROUP "Encoder_4" REGION "Region_1" ;
-UGROUP "FIFO_4" 
-	BLKNAME TDC_INST/GEN_Channels_4_Channels/FIFO;
-LOCATE UGROUP "FIFO_4" REGION "Region_1" ;
-UGROUP "Encoder_5" 
-	BLKNAME TDC_INST/GEN_Channels_5_Channels/Encoder;
-LOCATE UGROUP "Encoder_5" REGION "Region_1" ;
-UGROUP "FIFO_5" 
-	BLKNAME TDC_INST/GEN_Channels_5_Channels/FIFO;
-LOCATE UGROUP "FIFO_5" REGION "Region_1" ;
-UGROUP "Encoder_6" 
-	BLKNAME TDC_INST/GEN_Channels_6_Channels/Encoder;
-LOCATE UGROUP "Encoder_6" REGION "Region_2" ;
-UGROUP "FIFO_6" 
-	BLKNAME TDC_INST/GEN_Channels_6_Channels/FIFO;
-LOCATE UGROUP "FIFO_6" REGION "Region_2" ;
-UGROUP "Encoder_7" 
-	BLKNAME TDC_INST/GEN_Channels_7_Channels/Encoder;
-LOCATE UGROUP "Encoder_7" REGION "Region_2" ;
-UGROUP "FIFO_7" 
-	BLKNAME TDC_INST/GEN_Channels_7_Channels/FIFO;
-LOCATE UGROUP "FIFO_7" REGION "Region_2" ;
-
-
-
-
-#UGROUP "Channel_0" BBOX 8 52 
-#	BLKNAME TDC_INST/GEN_Channels_0_Channels;
-#LOCATE UGROUP "Channel_0" REGION "Region_0" ;
-#UGROUP "Channel_1" BBOX 8 52 
-#	BLKNAME TDC_INST/GEN_Channels_1_Channels;
-#LOCATE UGROUP "Channel_1" REGION "Region_0" ;
-#UGROUP "Channel_2" BBOX 8 52 
-#	BLKNAME TDC_INST/GEN_Channels_2_Channels;
-#LOCATE UGROUP "Channel_2" REGION "Region_0" ;
-#UGROUP "Channel_3" BBOX 8 52 
-#	BLKNAME TDC_INST/GEN_Channels_3_Channels;
-#LOCATE UGROUP "Channel_3" REGION "Region_1" ;
-#UGROUP "Channel_4" BBOX 8 52 
-#	BLKNAME TDC_INST/GEN_Channels_4_Channels;
-#LOCATE UGROUP "Channel_4" REGION "Region_1" ;
-#UGROUP "Channel_5" BBOX 8 52 
-#	BLKNAME TDC_INST/GEN_Channels_5_Channels;
-#LOCATE UGROUP "Channel_5" REGION "Region_1" ;
-#UGROUP "Channel_6" BBOX 8 52 
-#	BLKNAME TDC_INST/GEN_Channels_6_Channels;
-#LOCATE UGROUP "Channel_6" REGION "Region_2" ;
-#UGROUP "Channel_7" BBOX 8 52 
-#	BLKNAME TDC_INST/GEN_Channels_7_Channels;
-#LOCATE UGROUP "Channel_7" REGION "Region_2" ;
-##############################################################################
-#UGROUP "FC_8" BBOX 1 54 
-#	BLKNAME GEN_FC_8_FC;
-#LOCATE UGROUP "FC_8" SITE "R60C9D" ;
-#UGROUP "FC_9" BBOX 1 54 
-#	BLKNAME GEN_FC_9_FC;
-#LOCATE UGROUP "FC_9" SITE "R65C9D" ;
-#UGROUP "FC_10" BBOX 1 54 
-#	BLKNAME GEN_FC_10_FC;
-#LOCATE UGROUP "FC_10" SITE "R71C9D" ;
-#UGROUP "FC_11" BBOX 1 54 
-#	BLKNAME GEN_FC_11_FC;
-#LOCATE UGROUP "FC_11" SITE "R78C9D" ;
-#UGROUP "FC_12" BBOX 1 54 
-#	BLKNAME GEN_FC_12_FC;
-#LOCATE UGROUP "FC_12" SITE "R83C9D" ;
-#UGROUP "FC_13" BBOX 1 54 
-#	BLKNAME GEN_FC_13_FC;
-#LOCATE UGROUP "FC_13" SITE "R89C9D" ;
-#UGROUP "FC_14" BBOX 1 54 
-#	BLKNAME GEN_FC_14_FC;
-#LOCATE UGROUP "FC_14" SITE "R96C9D" ;
-#UGROUP "FC_15" BBOX 1 54 
-#	BLKNAME GEN_FC_15_FC;
-#LOCATE UGROUP "FC_15" SITE "R101C9D" ;
-#UGROUP "FC_16" BBOX 1 54 
-#	BLKNAME GEN_FC_16_FC;
-#LOCATE UGROUP "FC_16" SITE "R12C72D" ;
-#UGROUP "FC_17" BBOX 1 54 
-#	BLKNAME GEN_FC_17_FC;
-#LOCATE UGROUP "FC_17" SITE "R17C72D" ;
-#UGROUP "FC_18" BBOX 1 54 
-#	BLKNAME GEN_FC_18_FC;
-#LOCATE UGROUP "FC_18" SITE "R24C72D" ;
-#UGROUP "FC_19" BBOX 1 54 
-#	BLKNAME GEN_FC_19_FC;
-#LOCATE UGROUP "FC_19" SITE "R29C72D" ;
-#UGROUP "FC_20" BBOX 1 54 
-#	BLKNAME GEN_FC_20_FC;
-#LOCATE UGROUP "FC_20" SITE "R35C72D" ;
-#UGROUP "FC_21" BBOX 1 54 
-#	BLKNAME GEN_FC_21_FC;
-#LOCATE UGROUP "FC_21" SITE "R42C72D" ;
-#UGROUP "FC_22" BBOX 1 54 
-#	BLKNAME GEN_FC_22_FC;
-#LOCATE UGROUP "FC_22" SITE "R47C72D" ;
-#UGROUP "FC_23" BBOX 1 54 
-#	BLKNAME GEN_FC_23_FC;
-#LOCATE UGROUP "FC_23" SITE "R53C72D" ;
-#UGROUP "FC_24" BBOX 1 54 
-#	BLKNAME GEN_FC_24_FC;
-#LOCATE UGROUP "FC_24" SITE "R60C72D" ;
-#UGROUP "FC_25" BBOX 1 54 
-#	BLKNAME GEN_FC_25_FC;
-#LOCATE UGROUP "FC_25" SITE "R65C72D" ;
-#UGROUP "FC_26" BBOX 1 54 
-#	BLKNAME GEN_FC_26_FC;
-#LOCATE UGROUP "FC_26" SITE "R71C72D" ;
-#UGROUP "FC_27" BBOX 1 54 
-#	BLKNAME GEN_FC_27_FC;
-#LOCATE UGROUP "FC_27" SITE "R78C72D" ;
-#UGROUP "FC_28" BBOX 1 54 
-#	BLKNAME GEN_FC_28_FC;
-#LOCATE UGROUP "FC_28" SITE "R83C72D" ;
-#UGROUP "FC_29" BBOX 1 54 
-#	BLKNAME GEN_FC_29_FC;
-#LOCATE UGROUP "FC_29" SITE "R89C72D" ;
-#UGROUP "FC_30" BBOX 1 54 
-#	BLKNAME GEN_FC_30_FC;
-#LOCATE UGROUP "FC_30" SITE "R96C72D" ;
-#UGROUP "FC_31" BBOX 1 54 
-#	BLKNAME GEN_FC_31_FC;
-#LOCATE UGROUP "FC_31" SITE "R101C72D" ;
-############## Placement of the 48 Tapped-Delay-Lines ##########################
-#UGROUP "FC_0" BBOX 1 48 
-#BLKNAME GEN_FC_0_FC;
-#LOCATE UGROUP "FC_0" SITE "R12C9D" ;
-#UGROUP "FC_1" BBOX 1 48 
-#BLKNAME GEN_FC_1_FC;
-#LOCATE UGROUP "FC_1" SITE "R14C9D" ;
-#UGROUP "FC_2" BBOX 1 48 
-#BLKNAME GEN_FC_2_FC;
-#LOCATE UGROUP "FC_2" SITE "R18C9D" ;
-#UGROUP "FC_3" BBOX 1 48 
-#BLKNAME GEN_FC_3_FC;
-#LOCATE UGROUP "FC_3" SITE "R22C9D" ;
-#UGROUP "FC_4" BBOX 1 48 
-#BLKNAME GEN_FC_4_FC;
-#LOCATE UGROUP "FC_4" SITE "R26C9D" ;
-#UGROUP "FC_5" BBOX 1 48 
-#BLKNAME GEN_FC_5_FC;
-#LOCATE UGROUP "FC_5" SITE "R31C9D" ;
-#UGROUP "FC_6" BBOX 1 48 
-#BLKNAME GEN_FC_6_FC;
-#LOCATE UGROUP "FC_6" SITE "R35C9D" ;
-#UGROUP "FC_7" BBOX 1 48 
-#BLKNAME GEN_FC_7_FC;
-#LOCATE UGROUP "FC_7" SITE "R40C9D" ;
-#UGROUP "FC_8" BBOX 1 48 
-#BLKNAME GEN_FC_8_FC;
-#LOCATE UGROUP "FC_8" SITE "R44C9D" ;
-#UGROUP "FC_9" BBOX 1 48 
-#BLKNAME GEN_FC_9_FC;
-#LOCATE UGROUP "FC_9" SITE "R48C9D" ;
-#UGROUP "FC_10" BBOX 1 48 
-#BLKNAME GEN_FC_10_FC;
-#LOCATE UGROUP "FC_10" SITE "R51C9D" ;
-#UGROUP "FC_11" BBOX 1 48 
-#BLKNAME GEN_FC_11_FC;
-#LOCATE UGROUP "FC_11" SITE "R53C9D" ;
-#UGROUP "FC_12" BBOX 1 48 
-#BLKNAME GEN_FC_12_FC;
-#LOCATE UGROUP "FC_12" SITE "R57C9D" ;
-#UGROUP "FC_13" BBOX 1 48 
-#BLKNAME GEN_FC_13_FC;
-#LOCATE UGROUP "FC_13" SITE "R62C9D" ;
-#UGROUP "FC_14" BBOX 1 48 
-#BLKNAME GEN_FC_14_FC;
-#LOCATE UGROUP "FC_14" SITE "R66C9D" ;
-#UGROUP "FC_15" BBOX 1 48 
-#BLKNAME GEN_FC_15_FC;
-#LOCATE UGROUP "FC_15" SITE "R71C9D" ;
-#UGROUP "FC_16" BBOX 1 48 
-#BLKNAME GEN_FC_16_FC;
-#LOCATE UGROUP "FC_16" SITE "R75C9D" ;
-#UGROUP "FC_17" BBOX 1 48 
-#BLKNAME GEN_FC_17_FC;
-#LOCATE UGROUP "FC_17" SITE "R80C9D" ;
-#UGROUP "FC_18" BBOX 1 48 
-#BLKNAME GEN_FC_18_FC;
-#LOCATE UGROUP "FC_18" SITE "R84C9D" ;
-#UGROUP "FC_19" BBOX 1 48 
-#BLKNAME GEN_FC_19_FC;
-#LOCATE UGROUP "FC_19" SITE "R87C9D" ;
-#UGROUP "FC_20" BBOX 1 48 
-#BLKNAME GEN_FC_20_FC;
-#LOCATE UGROUP "FC_20" SITE "R91C9D" ;
-#UGROUP "FC_21" BBOX 1 48 
-#BLKNAME GEN_FC_21_FC;
-#LOCATE UGROUP "FC_21" SITE "R93C9D" ;
-#UGROUP "FC_22" BBOX 1 48 
-#BLKNAME GEN_FC_22_FC;
-#LOCATE UGROUP "FC_22" SITE "R98C9D" ;
-#UGROUP "FC_23" BBOX 1 48 
-#BLKNAME GEN_FC_23_FC;
-#LOCATE UGROUP "FC_23" SITE "R102C9D" ;
-#UGROUP "FC_24" BBOX 1 48 
-#BLKNAME GEN_FC_24_FC;
-#LOCATE UGROUP "FC_24" SITE "R9C72D" ;
-#UGROUP "FC_25" BBOX 1 48 
-#BLKNAME GEN_FC_25_FC;
-#LOCATE UGROUP "FC_25" SITE "R14C72D" ;
-#UGROUP "FC_26" BBOX 1 48 
-#BLKNAME GEN_FC_26_FC;
-#LOCATE UGROUP "FC_26" SITE "R18C72D" ;
-#UGROUP "FC_27" BBOX 1 48 
-#BLKNAME GEN_FC_27_FC;
-#LOCATE UGROUP "FC_27" SITE "R22C72D" ;
-#UGROUP "FC_28" BBOX 1 48 
-#BLKNAME GEN_FC_28_FC;
-#LOCATE UGROUP "FC_28" SITE "R26C72D" ;
-#UGROUP "FC_29" BBOX 1 48 
-#BLKNAME GEN_FC_29_FC;
-#LOCATE UGROUP "FC_29" SITE "R31C72D" ;
-#UGROUP "FC_30" BBOX 1 48 
-#BLKNAME GEN_FC_30_FC;
-#LOCATE UGROUP "FC_30" SITE "R35C72D" ;
-#UGROUP "FC_31" BBOX 1 48 
-#BLKNAME GEN_FC_31_FC;
-#LOCATE UGROUP "FC_31" SITE "R40C72D" ;
-#UGROUP "FC_32" BBOX 1 48 
-#BLKNAME GEN_FC_32_FC;
-#LOCATE UGROUP "FC_32" SITE "R44C72D" ;
-#UGROUP "FC_33" BBOX 1 48 
-#BLKNAME GEN_FC_33_FC;
-#LOCATE UGROUP "FC_33" SITE "R48C72D" ;
-#UGROUP "FC_34" BBOX 1 48 
-#BLKNAME GEN_FC_34_FC;
-#LOCATE UGROUP "FC_34" SITE "R51C72D" ;
-#UGROUP "FC_35" BBOX 1 48 
-#BLKNAME GEN_FC_35_FC;
-#LOCATE UGROUP "FC_35" SITE "R53C72D" ;
-#UGROUP "FC_36" BBOX 1 48 
-#BLKNAME GEN_FC_36_FC;
-#LOCATE UGROUP "FC_36" SITE "R57C72D" ;
-#UGROUP "FC_37" BBOX 1 48 
-#BLKNAME GEN_FC_37_FC;
-#LOCATE UGROUP "FC_37" SITE "R62C72D" ;
-#UGROUP "FC_38" BBOX 1 48 
-#BLKNAME GEN_FC_38_FC;
-#LOCATE UGROUP "FC_38" SITE "R66C72D" ;
-#UGROUP "FC_39" BBOX 1 48 
-#BLKNAME GEN_FC_39_FC;
-#LOCATE UGROUP "FC_39" SITE "R71C72D" ;
-#UGROUP "FC_40" BBOX 1 48 
-#BLKNAME GEN_FC_40_FC;
-#LOCATE UGROUP "FC_40" SITE "R75C72D" ;
-#UGROUP "FC_41" BBOX 1 48 
-#BLKNAME GEN_FC_41_FC;
-#LOCATE UGROUP "FC_41" SITE "R80C72D" ;
-#UGROUP "FC_42" BBOX 1 48 
-#BLKNAME GEN_FC_42_FC;
-#LOCATE UGROUP "FC_42" SITE "R84C72D" ;
-#UGROUP "FC_43" BBOX 1 48 
-#BLKNAME GEN_FC_43_FC;
-#LOCATE UGROUP "FC_43" SITE "R87C72D" ;
-#UGROUP "FC_44" BBOX 1 48 
-#BLKNAME GEN_FC_44_FC;
-#LOCATE UGROUP "FC_44" SITE "R91C72D" ;
-#UGROUP "FC_45" BBOX 1 48 
-#BLKNAME GEN_FC_45_FC;
-#LOCATE UGROUP "FC_45" SITE "R93C72D" ;
-#UGROUP "FC_46" BBOX 1 48 
-#BLKNAME GEN_FC_46_FC;
-#LOCATE UGROUP "FC_46" SITE "R98C72D" ;
-#UGROUP "FC_47" BBOX 1 48 
-#BLKNAME GEN_FC_47_FC;
-#LOCATE UGROUP "FC_47" SITE "R102C72D" ;