From: Andreas Neiser Date: Thu, 28 May 2015 13:24:42 +0000 (+0200) Subject: Add dqsinput 6x5, add 4x5 ipx file X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5b152cce5bf6254068b44d9589f68fe9187fc4fd;p=trb3.git Add dqsinput 6x5, add 4x5 ipx file --- diff --git a/base/cores/dqsinput_4x5.ipx b/base/cores/dqsinput_4x5.ipx new file mode 100644 index 0000000..47044de --- /dev/null +++ b/base/cores/dqsinput_4x5.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/base/cores/dqsinput_6x5.ipx b/base/cores/dqsinput_6x5.ipx new file mode 100644 index 0000000..1fa8506 --- /dev/null +++ b/base/cores/dqsinput_6x5.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/base/cores/dqsinput_6x5.lpc b/base/cores/dqsinput_6x5.lpc new file mode 100644 index 0000000..ac96247 --- /dev/null +++ b/base/cores/dqsinput_6x5.lpc @@ -0,0 +1,62 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DDR_GENERIC +CoreRevision=5.4 +ModuleName=dqsinput_6x5 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=05/28/2015 +Time=15:23:10 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +mode=Receive +trioddr=0 +io_type=LVDS25 +num_int=6 +width=5 +freq_in=200 +bandwidth=2000 +aligned=Centered +pre-configuration=DISABLED +mode2=Receive +trioddr2=0 +io_type2=LVDS25 +freq_in2=200 +gear=2x +aligned2=Centered +num_int2=6 +width2=5 +Interface=GDDRX2_RX.DQS.Centered +Delay=Bypass +Number=6 +dqs1=5 +dqs2=5 +dqs3=5 +dqs4=5 +dqs5=5 +dqs6=5 +dqs7= +dqs8= +val= +Phase=TRDLLB/DLLDELB +Divider=CLKDIVB +Multiplier=2 +PllFreq=100 diff --git a/base/cores/dqsinput_6x5.vhd b/base/cores/dqsinput_6x5.vhd new file mode 100644 index 0000000..097f7ae --- /dev/null +++ b/base/cores/dqsinput_6x5.vhd @@ -0,0 +1,1095 @@ +-- VHDL netlist generated by SCUBA Diamond_2.2_Production (99) +-- Module Version: 5.4 +--/home/soft/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n dqsinput_6x5 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 200 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -dqs 3 5 -dqs 4 5 -dqs 5 5 -dqs 6 5 -e + +-- Thu May 28 15:23:10 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity dqsinput_6x5 is + port ( + clk_0: in std_logic; + clk_1: in std_logic; + clk_2: in std_logic; + clk_3: in std_logic; + clk_4: in std_logic; + clk_5: in std_logic; + clkdiv_reset: in std_logic; + eclk: in std_logic; + reset_0: in std_logic; + reset_1: in std_logic; + reset_2: in std_logic; + reset_3: in std_logic; + reset_4: in std_logic; + reset_5: in std_logic; + sclk: out std_logic; + datain_0: in std_logic_vector(4 downto 0); + datain_1: in std_logic_vector(4 downto 0); + datain_2: in std_logic_vector(4 downto 0); + datain_3: in std_logic_vector(4 downto 0); + datain_4: in std_logic_vector(4 downto 0); + datain_5: in std_logic_vector(4 downto 0); + q_0: out std_logic_vector(19 downto 0); + q_1: out std_logic_vector(19 downto 0); + q_2: out std_logic_vector(19 downto 0); + q_3: out std_logic_vector(19 downto 0); + q_4: out std_logic_vector(19 downto 0); + q_5: out std_logic_vector(19 downto 0)); + attribute dont_touch : boolean; + attribute dont_touch of dqsinput_6x5 : entity is true; +end dqsinput_6x5; + +architecture Structure of dqsinput_6x5 is + + -- internal signal declarations + signal datain_5i_t4: std_logic; + signal datain_5i_t3: std_logic; + signal datain_5i_t2: std_logic; + signal datain_5i_t1: std_logic; + signal datain_5i_t0: std_logic; + signal buf_datain_5i4: std_logic; + signal buf_datain_5i3: std_logic; + signal buf_datain_5i2: std_logic; + signal buf_datain_5i1: std_logic; + signal buf_datain_5i0: std_logic; + signal datain_4i_t4: std_logic; + signal datain_4i_t3: std_logic; + signal datain_4i_t2: std_logic; + signal datain_4i_t1: std_logic; + signal datain_4i_t0: std_logic; + signal buf_datain_4i4: std_logic; + signal buf_datain_4i3: std_logic; + signal buf_datain_4i2: std_logic; + signal buf_datain_4i1: std_logic; + signal buf_datain_4i0: std_logic; + signal datain_3i_t4: std_logic; + signal datain_3i_t3: std_logic; + signal datain_3i_t2: std_logic; + signal datain_3i_t1: std_logic; + signal datain_3i_t0: std_logic; + signal buf_datain_3i4: std_logic; + signal buf_datain_3i3: std_logic; + signal buf_datain_3i2: std_logic; + signal buf_datain_3i1: std_logic; + signal buf_datain_3i0: std_logic; + signal datain_2i_t4: std_logic; + signal datain_2i_t3: std_logic; + signal datain_2i_t2: std_logic; + signal datain_2i_t1: std_logic; + signal datain_2i_t0: std_logic; + signal buf_datain_2i4: std_logic; + signal buf_datain_2i3: std_logic; + signal buf_datain_2i2: std_logic; + signal buf_datain_2i1: std_logic; + signal buf_datain_2i0: std_logic; + signal datain_1i_t4: std_logic; + signal datain_1i_t3: std_logic; + signal datain_1i_t2: std_logic; + signal datain_1i_t1: std_logic; + signal datain_1i_t0: std_logic; + signal buf_datain_1i4: std_logic; + signal buf_datain_1i3: std_logic; + signal buf_datain_1i2: std_logic; + signal buf_datain_1i1: std_logic; + signal buf_datain_1i0: std_logic; + signal datain_0i_t4: std_logic; + signal datain_0i_t3: std_logic; + signal datain_0i_t2: std_logic; + signal datain_0i_t1: std_logic; + signal datain_0i_t0: std_logic; + signal buf_datain_0i4: std_logic; + signal buf_datain_0i3: std_logic; + signal buf_datain_0i2: std_logic; + signal buf_datain_0i1: std_logic; + signal buf_datain_0i0: std_logic; + signal qb129: std_logic; + signal qa129: std_logic; + signal qb029: std_logic; + signal qa029: std_logic; + signal datain_t29: std_logic; + signal qb128: std_logic; + signal qa128: std_logic; + signal qb028: std_logic; + signal qa028: std_logic; + signal datain_t28: std_logic; + signal qb127: std_logic; + signal qa127: std_logic; + signal qb027: std_logic; + signal qa027: std_logic; + signal datain_t27: std_logic; + signal qb126: std_logic; + signal qa126: std_logic; + signal qb026: std_logic; + signal qa026: std_logic; + signal datain_t26: std_logic; + signal qb125: std_logic; + signal qa125: std_logic; + signal qb025: std_logic; + signal qa025: std_logic; + signal datain_t25: std_logic; + signal qb124: std_logic; + signal qa124: std_logic; + signal qb024: std_logic; + signal qa024: std_logic; + signal datain_t24: std_logic; + signal qb123: std_logic; + signal qa123: std_logic; + signal qb023: std_logic; + signal qa023: std_logic; + signal datain_t23: std_logic; + signal qb122: std_logic; + signal qa122: std_logic; + signal qb022: std_logic; + signal qa022: std_logic; + signal datain_t22: std_logic; + signal qb121: std_logic; + signal qa121: std_logic; + signal qb021: std_logic; + signal qa021: std_logic; + signal datain_t21: std_logic; + signal qb120: std_logic; + signal qa120: std_logic; + signal qb020: std_logic; + signal qa020: std_logic; + signal datain_t20: std_logic; + signal qb119: std_logic; + signal qa119: std_logic; + signal qb019: std_logic; + signal qa019: std_logic; + signal datain_t19: std_logic; + signal qb118: std_logic; + signal qa118: std_logic; + signal qb018: std_logic; + signal qa018: std_logic; + signal datain_t18: std_logic; + signal qb117: std_logic; + signal qa117: std_logic; + signal qb017: std_logic; + signal qa017: std_logic; + signal datain_t17: std_logic; + signal qb116: std_logic; + signal qa116: std_logic; + signal qb016: std_logic; + signal qa016: std_logic; + signal datain_t16: std_logic; + signal qb115: std_logic; + signal qa115: std_logic; + signal qb015: std_logic; + signal qa015: std_logic; + signal datain_t15: std_logic; + signal qb114: std_logic; + signal qa114: std_logic; + signal qb014: std_logic; + signal qa014: std_logic; + signal datain_t14: std_logic; + signal qb113: std_logic; + signal qa113: std_logic; + signal qb013: std_logic; + signal qa013: std_logic; + signal datain_t13: std_logic; + signal qb112: std_logic; + signal qa112: std_logic; + signal qb012: std_logic; + signal qa012: std_logic; + signal datain_t12: std_logic; + signal qb111: std_logic; + signal qa111: std_logic; + signal qb011: std_logic; + signal qa011: std_logic; + signal datain_t11: std_logic; + signal qb110: std_logic; + signal qa110: std_logic; + signal qb010: std_logic; + signal qa010: std_logic; + signal datain_t10: std_logic; + signal qb19: std_logic; + signal qa19: std_logic; + signal qb09: std_logic; + signal qa09: std_logic; + signal datain_t9: std_logic; + signal qb18: std_logic; + signal qa18: std_logic; + signal qb08: std_logic; + signal qa08: std_logic; + signal datain_t8: std_logic; + signal qb17: std_logic; + signal qa17: std_logic; + signal qb07: std_logic; + signal qa07: std_logic; + signal datain_t7: std_logic; + signal qb16: std_logic; + signal qa16: std_logic; + signal qb06: std_logic; + signal qa06: std_logic; + signal datain_t6: std_logic; + signal qb15: std_logic; + signal qa15: std_logic; + signal qb05: std_logic; + signal qa05: std_logic; + signal datain_t5: std_logic; + signal qb14: std_logic; + signal qa14: std_logic; + signal qb04: std_logic; + signal qa04: std_logic; + signal datain_t4: std_logic; + signal qb13: std_logic; + signal qa13: std_logic; + signal qb03: std_logic; + signal qa03: std_logic; + signal datain_t3: std_logic; + signal qb12: std_logic; + signal qa12: std_logic; + signal qb02: std_logic; + signal qa02: std_logic; + signal datain_t2: std_logic; + signal qb11: std_logic; + signal qa11: std_logic; + signal qb01: std_logic; + signal qa01: std_logic; + signal datain_t1: std_logic; + signal qb10: std_logic; + signal qa10: std_logic; + signal qb00: std_logic; + signal qa00: std_logic; + signal datain_t0: std_logic; + signal dqclk15: std_logic; + signal dqclk05: std_logic; + signal eclkdqsr5: std_logic; + signal ddrlat5: std_logic; + signal datavalid5: std_logic; + signal prmbdet5: std_logic; + signal ddrclkpol5: std_logic; + signal dqsw5: std_logic; + signal dqclk14: std_logic; + signal dqclk04: std_logic; + signal eclkdqsr4: std_logic; + signal ddrlat4: std_logic; + signal datavalid4: std_logic; + signal prmbdet4: std_logic; + signal ddrclkpol4: std_logic; + signal dqsw4: std_logic; + signal dqclk13: std_logic; + signal dqclk03: std_logic; + signal eclkdqsr3: std_logic; + signal ddrlat3: std_logic; + signal datavalid3: std_logic; + signal prmbdet3: std_logic; + signal ddrclkpol3: std_logic; + signal dqsw3: std_logic; + signal dqclk12: std_logic; + signal dqclk02: std_logic; + signal eclkdqsr2: std_logic; + signal ddrlat2: std_logic; + signal datavalid2: std_logic; + signal prmbdet2: std_logic; + signal ddrclkpol2: std_logic; + signal dqsw2: std_logic; + signal dqclk11: std_logic; + signal dqclk01: std_logic; + signal eclkdqsr1: std_logic; + signal ddrlat1: std_logic; + signal datavalid1: std_logic; + signal prmbdet1: std_logic; + signal ddrclkpol1: std_logic; + signal dqsw1: std_logic; + signal dqclk10: std_logic; + signal dqclk00: std_logic; + signal eclkdqsr0: std_logic; + signal ddrlat0: std_logic; + signal datavalid0: std_logic; + signal prmbdet0: std_logic; + signal ddrclkpol0: std_logic; + signal dqsw0: std_logic; + signal scuba_vlo: std_logic; + signal dqsdel: std_logic; + signal dqsdll_lock: std_logic; + signal dqsdll_uddcntln: std_logic; + signal dqsdll_reset: std_logic; + signal clkos: std_logic; + signal cdiv8: std_logic; + signal cdiv4: std_logic; + signal cdiv1: std_logic; + signal scuba_vhi: std_logic; + signal clkok: std_logic; + signal buf_clk_5: std_logic; + signal buf_clk_4: std_logic; + signal buf_clk_3: std_logic; + signal buf_clk_2: std_logic; + signal buf_clk_1: std_logic; + signal buf_clk_0: std_logic; + signal sclk_t: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component IB + port (I: in std_logic; O: out std_logic); + end component; + component CLKDIVB + port (CLKI: in std_logic; RST: in std_logic; + RELEASE: in std_logic; CDIV1: out std_logic; + CDIV2: out std_logic; CDIV4: out std_logic; + CDIV8: out std_logic); + end component; + component IDDRX2D + generic (DELAYMODE : in String; SCLKLATENCY : in Integer); + port (D: in std_logic; SCLK: in std_logic; ECLK: in std_logic; + ECLKDQSR: in std_logic; DDRLAT: in std_logic; + DDRCLKPOL: in std_logic; QA0: out std_logic; + QB0: out std_logic; QA1: out std_logic; + QB1: out std_logic); + end component; + component DQSBUFD + generic (NRZMODE : in String; DYNDEL_CNTL : in String; + DYNDEL_VAL : in Integer; DYNDEL_TYPE : in String); + port (DQSI: in std_logic; SCLK: in std_logic; + READ: in std_logic; DQSDEL: in std_logic; + ECLK: in std_logic; ECLKW: in std_logic; + RST: in std_logic; DYNDELPOL: in std_logic; + DYNDELAY6: in std_logic; DYNDELAY5: in std_logic; + DYNDELAY4: in std_logic; DYNDELAY3: in std_logic; + DYNDELAY2: in std_logic; DYNDELAY1: in std_logic; + DYNDELAY0: in std_logic; DQSW: out std_logic; + DDRCLKPOL: out std_logic; PRMBDET: out std_logic; + DATAVALID: out std_logic; DDRLAT: out std_logic; + ECLKDQSR: out std_logic; DQCLK0: out std_logic; + DQCLK1: out std_logic); + end component; + component DQSDLLB + generic (LOCK_SENSITIVITY : in String); + port (CLK: in std_logic; RST: in std_logic; + UDDCNTLN: in std_logic; LOCK: out std_logic; + DQSDEL: out std_logic); + end component; + component DELAYC + port (A: in std_logic; Z: out std_logic); + end component; + attribute IDDRAPPS : string; + attribute IO_TYPE : string; + attribute IO_TYPE of Inst10_IB4 : label is "LVDS25"; + attribute IO_TYPE of Inst10_IB3 : label is "LVDS25"; + attribute IO_TYPE of Inst10_IB2 : label is "LVDS25"; + attribute IO_TYPE of Inst10_IB1 : label is "LVDS25"; + attribute IO_TYPE of Inst10_IB0 : label is "LVDS25"; + attribute IO_TYPE of Inst9_IB4 : label is "LVDS25"; + attribute IO_TYPE of Inst9_IB3 : label is "LVDS25"; + attribute IO_TYPE of Inst9_IB2 : label is "LVDS25"; + attribute IO_TYPE of Inst9_IB1 : label is "LVDS25"; + attribute IO_TYPE of Inst9_IB0 : label is "LVDS25"; + attribute IO_TYPE of Inst8_IB4 : label is "LVDS25"; + attribute IO_TYPE of Inst8_IB3 : label is "LVDS25"; + attribute IO_TYPE of Inst8_IB2 : label is "LVDS25"; + attribute IO_TYPE of Inst8_IB1 : label is "LVDS25"; + attribute IO_TYPE of Inst8_IB0 : label is "LVDS25"; + attribute IO_TYPE of Inst7_IB4 : label is "LVDS25"; + attribute IO_TYPE of Inst7_IB3 : label is "LVDS25"; + attribute IO_TYPE of Inst7_IB2 : label is "LVDS25"; + attribute IO_TYPE of Inst7_IB1 : label is "LVDS25"; + attribute IO_TYPE of Inst7_IB0 : label is "LVDS25"; + attribute IO_TYPE of Inst6_IB4 : label is "LVDS25"; + attribute IO_TYPE of Inst6_IB3 : label is "LVDS25"; + attribute IO_TYPE of Inst6_IB2 : label is "LVDS25"; + attribute IO_TYPE of Inst6_IB1 : label is "LVDS25"; + attribute IO_TYPE of Inst6_IB0 : label is "LVDS25"; + attribute IO_TYPE of Inst5_IB4 : label is "LVDS25"; + attribute IO_TYPE of Inst5_IB3 : label is "LVDS25"; + attribute IO_TYPE of Inst5_IB2 : label is "LVDS25"; + attribute IO_TYPE of Inst5_IB1 : label is "LVDS25"; + attribute IO_TYPE of Inst5_IB0 : label is "LVDS25"; + attribute IDDRAPPS of Inst_IDDRX2D_5_4 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_5_3 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_5_2 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_5_1 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_5_0 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_4_4 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_4_3 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_4_2 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_4_1 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_4_0 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_3_4 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_3_3 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_3_2 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_3_1 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_3_0 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_2_4 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_2_3 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_2_2 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_2_1 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_2_0 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_1_4 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_1_3 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_1_2 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_1_1 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_1_0 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_0_4 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_0_3 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_0_2 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_0_1 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_0_0 : label is "DQS_CENTERED"; + attribute IO_TYPE of Inst1_IB5 : label is "LVDS25"; + attribute IO_TYPE of Inst1_IB4 : label is "LVDS25"; + attribute IO_TYPE of Inst1_IB3 : label is "LVDS25"; + attribute IO_TYPE of Inst1_IB2 : label is "LVDS25"; + attribute IO_TYPE of Inst1_IB1 : label is "LVDS25"; + attribute IO_TYPE of Inst1_IB0 : label is "LVDS25"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + udel_datain_5i4: DELAYC + port map (A=>buf_datain_5i4, Z=>datain_5i_t4); + + udel_datain_5i3: DELAYC + port map (A=>buf_datain_5i3, Z=>datain_5i_t3); + + udel_datain_5i2: DELAYC + port map (A=>buf_datain_5i2, Z=>datain_5i_t2); + + udel_datain_5i1: DELAYC + port map (A=>buf_datain_5i1, Z=>datain_5i_t1); + + udel_datain_5i0: DELAYC + port map (A=>buf_datain_5i0, Z=>datain_5i_t0); + + Inst10_IB4: IB + port map (I=>datain_5(4), O=>buf_datain_5i4); + + Inst10_IB3: IB + port map (I=>datain_5(3), O=>buf_datain_5i3); + + Inst10_IB2: IB + port map (I=>datain_5(2), O=>buf_datain_5i2); + + Inst10_IB1: IB + port map (I=>datain_5(1), O=>buf_datain_5i1); + + Inst10_IB0: IB + port map (I=>datain_5(0), O=>buf_datain_5i0); + + udel_datain_4i4: DELAYC + port map (A=>buf_datain_4i4, Z=>datain_4i_t4); + + udel_datain_4i3: DELAYC + port map (A=>buf_datain_4i3, Z=>datain_4i_t3); + + udel_datain_4i2: DELAYC + port map (A=>buf_datain_4i2, Z=>datain_4i_t2); + + udel_datain_4i1: DELAYC + port map (A=>buf_datain_4i1, Z=>datain_4i_t1); + + udel_datain_4i0: DELAYC + port map (A=>buf_datain_4i0, Z=>datain_4i_t0); + + Inst9_IB4: IB + port map (I=>datain_4(4), O=>buf_datain_4i4); + + Inst9_IB3: IB + port map (I=>datain_4(3), O=>buf_datain_4i3); + + Inst9_IB2: IB + port map (I=>datain_4(2), O=>buf_datain_4i2); + + Inst9_IB1: IB + port map (I=>datain_4(1), O=>buf_datain_4i1); + + Inst9_IB0: IB + port map (I=>datain_4(0), O=>buf_datain_4i0); + + udel_datain_3i4: DELAYC + port map (A=>buf_datain_3i4, Z=>datain_3i_t4); + + udel_datain_3i3: DELAYC + port map (A=>buf_datain_3i3, Z=>datain_3i_t3); + + udel_datain_3i2: DELAYC + port map (A=>buf_datain_3i2, Z=>datain_3i_t2); + + udel_datain_3i1: DELAYC + port map (A=>buf_datain_3i1, Z=>datain_3i_t1); + + udel_datain_3i0: DELAYC + port map (A=>buf_datain_3i0, Z=>datain_3i_t0); + + Inst8_IB4: IB + port map (I=>datain_3(4), O=>buf_datain_3i4); + + Inst8_IB3: IB + port map (I=>datain_3(3), O=>buf_datain_3i3); + + Inst8_IB2: IB + port map (I=>datain_3(2), O=>buf_datain_3i2); + + Inst8_IB1: IB + port map (I=>datain_3(1), O=>buf_datain_3i1); + + Inst8_IB0: IB + port map (I=>datain_3(0), O=>buf_datain_3i0); + + udel_datain_2i4: DELAYC + port map (A=>buf_datain_2i4, Z=>datain_2i_t4); + + udel_datain_2i3: DELAYC + port map (A=>buf_datain_2i3, Z=>datain_2i_t3); + + udel_datain_2i2: DELAYC + port map (A=>buf_datain_2i2, Z=>datain_2i_t2); + + udel_datain_2i1: DELAYC + port map (A=>buf_datain_2i1, Z=>datain_2i_t1); + + udel_datain_2i0: DELAYC + port map (A=>buf_datain_2i0, Z=>datain_2i_t0); + + Inst7_IB4: IB + port map (I=>datain_2(4), O=>buf_datain_2i4); + + Inst7_IB3: IB + port map (I=>datain_2(3), O=>buf_datain_2i3); + + Inst7_IB2: IB + port map (I=>datain_2(2), O=>buf_datain_2i2); + + Inst7_IB1: IB + port map (I=>datain_2(1), O=>buf_datain_2i1); + + Inst7_IB0: IB + port map (I=>datain_2(0), O=>buf_datain_2i0); + + udel_datain_1i4: DELAYC + port map (A=>buf_datain_1i4, Z=>datain_1i_t4); + + udel_datain_1i3: DELAYC + port map (A=>buf_datain_1i3, Z=>datain_1i_t3); + + udel_datain_1i2: DELAYC + port map (A=>buf_datain_1i2, Z=>datain_1i_t2); + + udel_datain_1i1: DELAYC + port map (A=>buf_datain_1i1, Z=>datain_1i_t1); + + udel_datain_1i0: DELAYC + port map (A=>buf_datain_1i0, Z=>datain_1i_t0); + + Inst6_IB4: IB + port map (I=>datain_1(4), O=>buf_datain_1i4); + + Inst6_IB3: IB + port map (I=>datain_1(3), O=>buf_datain_1i3); + + Inst6_IB2: IB + port map (I=>datain_1(2), O=>buf_datain_1i2); + + Inst6_IB1: IB + port map (I=>datain_1(1), O=>buf_datain_1i1); + + Inst6_IB0: IB + port map (I=>datain_1(0), O=>buf_datain_1i0); + + udel_datain_0i4: DELAYC + port map (A=>buf_datain_0i4, Z=>datain_0i_t4); + + udel_datain_0i3: DELAYC + port map (A=>buf_datain_0i3, Z=>datain_0i_t3); + + udel_datain_0i2: DELAYC + port map (A=>buf_datain_0i2, Z=>datain_0i_t2); + + udel_datain_0i1: DELAYC + port map (A=>buf_datain_0i1, Z=>datain_0i_t1); + + udel_datain_0i0: DELAYC + port map (A=>buf_datain_0i0, Z=>datain_0i_t0); + + Inst5_IB4: IB + port map (I=>datain_0(4), O=>buf_datain_0i4); + + Inst5_IB3: IB + port map (I=>datain_0(3), O=>buf_datain_0i3); + + Inst5_IB2: IB + port map (I=>datain_0(2), O=>buf_datain_0i2); + + Inst5_IB1: IB + port map (I=>datain_0(1), O=>buf_datain_0i1); + + Inst5_IB0: IB + port map (I=>datain_0(0), O=>buf_datain_0i0); + + Inst_IDDRX2D_5_4: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t29, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr5, DDRLAT=>ddrlat5, DDRCLKPOL=>ddrclkpol5, + QA0=>qa029, QB0=>qb029, QA1=>qa129, QB1=>qb129); + + Inst_IDDRX2D_5_3: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t28, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr5, DDRLAT=>ddrlat5, DDRCLKPOL=>ddrclkpol5, + QA0=>qa028, QB0=>qb028, QA1=>qa128, QB1=>qb128); + + Inst_IDDRX2D_5_2: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t27, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr5, DDRLAT=>ddrlat5, DDRCLKPOL=>ddrclkpol5, + QA0=>qa027, QB0=>qb027, QA1=>qa127, QB1=>qb127); + + Inst_IDDRX2D_5_1: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t26, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr5, DDRLAT=>ddrlat5, DDRCLKPOL=>ddrclkpol5, + QA0=>qa026, QB0=>qb026, QA1=>qa126, QB1=>qb126); + + Inst_IDDRX2D_5_0: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t25, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr5, DDRLAT=>ddrlat5, DDRCLKPOL=>ddrclkpol5, + QA0=>qa025, QB0=>qb025, QA1=>qa125, QB1=>qb125); + + Inst_IDDRX2D_4_4: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t24, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr4, DDRLAT=>ddrlat4, DDRCLKPOL=>ddrclkpol4, + QA0=>qa024, QB0=>qb024, QA1=>qa124, QB1=>qb124); + + Inst_IDDRX2D_4_3: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t23, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr4, DDRLAT=>ddrlat4, DDRCLKPOL=>ddrclkpol4, + QA0=>qa023, QB0=>qb023, QA1=>qa123, QB1=>qb123); + + Inst_IDDRX2D_4_2: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t22, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr4, DDRLAT=>ddrlat4, DDRCLKPOL=>ddrclkpol4, + QA0=>qa022, QB0=>qb022, QA1=>qa122, QB1=>qb122); + + Inst_IDDRX2D_4_1: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t21, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr4, DDRLAT=>ddrlat4, DDRCLKPOL=>ddrclkpol4, + QA0=>qa021, QB0=>qb021, QA1=>qa121, QB1=>qb121); + + Inst_IDDRX2D_4_0: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t20, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr4, DDRLAT=>ddrlat4, DDRCLKPOL=>ddrclkpol4, + QA0=>qa020, QB0=>qb020, QA1=>qa120, QB1=>qb120); + + Inst_IDDRX2D_3_4: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t19, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr3, DDRLAT=>ddrlat3, DDRCLKPOL=>ddrclkpol3, + QA0=>qa019, QB0=>qb019, QA1=>qa119, QB1=>qb119); + + Inst_IDDRX2D_3_3: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t18, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr3, DDRLAT=>ddrlat3, DDRCLKPOL=>ddrclkpol3, + QA0=>qa018, QB0=>qb018, QA1=>qa118, QB1=>qb118); + + Inst_IDDRX2D_3_2: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t17, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr3, DDRLAT=>ddrlat3, DDRCLKPOL=>ddrclkpol3, + QA0=>qa017, QB0=>qb017, QA1=>qa117, QB1=>qb117); + + Inst_IDDRX2D_3_1: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t16, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr3, DDRLAT=>ddrlat3, DDRCLKPOL=>ddrclkpol3, + QA0=>qa016, QB0=>qb016, QA1=>qa116, QB1=>qb116); + + Inst_IDDRX2D_3_0: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t15, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr3, DDRLAT=>ddrlat3, DDRCLKPOL=>ddrclkpol3, + QA0=>qa015, QB0=>qb015, QA1=>qa115, QB1=>qb115); + + Inst_IDDRX2D_2_4: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t14, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr2, DDRLAT=>ddrlat2, DDRCLKPOL=>ddrclkpol2, + QA0=>qa014, QB0=>qb014, QA1=>qa114, QB1=>qb114); + + Inst_IDDRX2D_2_3: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t13, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr2, DDRLAT=>ddrlat2, DDRCLKPOL=>ddrclkpol2, + QA0=>qa013, QB0=>qb013, QA1=>qa113, QB1=>qb113); + + Inst_IDDRX2D_2_2: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t12, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr2, DDRLAT=>ddrlat2, DDRCLKPOL=>ddrclkpol2, + QA0=>qa012, QB0=>qb012, QA1=>qa112, QB1=>qb112); + + Inst_IDDRX2D_2_1: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t11, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr2, DDRLAT=>ddrlat2, DDRCLKPOL=>ddrclkpol2, + QA0=>qa011, QB0=>qb011, QA1=>qa111, QB1=>qb111); + + Inst_IDDRX2D_2_0: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t10, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr2, DDRLAT=>ddrlat2, DDRCLKPOL=>ddrclkpol2, + QA0=>qa010, QB0=>qb010, QA1=>qa110, QB1=>qb110); + + Inst_IDDRX2D_1_4: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t9, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, + QA0=>qa09, QB0=>qb09, QA1=>qa19, QB1=>qb19); + + Inst_IDDRX2D_1_3: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t8, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, + QA0=>qa08, QB0=>qb08, QA1=>qa18, QB1=>qb18); + + Inst_IDDRX2D_1_2: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t7, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, + QA0=>qa07, QB0=>qb07, QA1=>qa17, QB1=>qb17); + + Inst_IDDRX2D_1_1: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t6, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, + QA0=>qa06, QB0=>qb06, QA1=>qa16, QB1=>qb16); + + Inst_IDDRX2D_1_0: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t5, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, + QA0=>qa05, QB0=>qb05, QA1=>qa15, QB1=>qb15); + + Inst_IDDRX2D_0_4: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t4, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, + QA0=>qa04, QB0=>qb04, QA1=>qa14, QB1=>qb14); + + Inst_IDDRX2D_0_3: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t3, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, + QA0=>qa03, QB0=>qb03, QA1=>qa13, QB1=>qb13); + + Inst_IDDRX2D_0_2: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t2, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, + QA0=>qa02, QB0=>qb02, QA1=>qa12, QB1=>qb12); + + Inst_IDDRX2D_0_1: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t1, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, + QA0=>qa01, QB0=>qb01, QA1=>qa11, QB1=>qb11); + + Inst_IDDRX2D_0_0: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t0, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, + QA0=>qa00, QB0=>qb00, QA1=>qa10, QB1=>qb10); + + Inst4_DQSBUFD5: DQSBUFD + generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC", + DYNDEL_TYPE=> "NORMAL") + port map (DQSI=>buf_clk_5, SCLK=>clkok, READ=>reset_5, + DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_5, + DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, + DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, + DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, + DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw5, + DDRCLKPOL=>ddrclkpol5, PRMBDET=>prmbdet5, + DATAVALID=>datavalid5, DDRLAT=>ddrlat5, ECLKDQSR=>eclkdqsr5, + DQCLK0=>dqclk05, DQCLK1=>dqclk15); + + Inst4_DQSBUFD4: DQSBUFD + generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC", + DYNDEL_TYPE=> "NORMAL") + port map (DQSI=>buf_clk_4, SCLK=>clkok, READ=>reset_4, + DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_4, + DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, + DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, + DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, + DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw4, + DDRCLKPOL=>ddrclkpol4, PRMBDET=>prmbdet4, + DATAVALID=>datavalid4, DDRLAT=>ddrlat4, ECLKDQSR=>eclkdqsr4, + DQCLK0=>dqclk04, DQCLK1=>dqclk14); + + Inst4_DQSBUFD3: DQSBUFD + generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC", + DYNDEL_TYPE=> "NORMAL") + port map (DQSI=>buf_clk_3, SCLK=>clkok, READ=>reset_3, + DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_3, + DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, + DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, + DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, + DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw3, + DDRCLKPOL=>ddrclkpol3, PRMBDET=>prmbdet3, + DATAVALID=>datavalid3, DDRLAT=>ddrlat3, ECLKDQSR=>eclkdqsr3, + DQCLK0=>dqclk03, DQCLK1=>dqclk13); + + Inst4_DQSBUFD2: DQSBUFD + generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC", + DYNDEL_TYPE=> "NORMAL") + port map (DQSI=>buf_clk_2, SCLK=>clkok, READ=>reset_2, + DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_2, + DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, + DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, + DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, + DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw2, + DDRCLKPOL=>ddrclkpol2, PRMBDET=>prmbdet2, + DATAVALID=>datavalid2, DDRLAT=>ddrlat2, ECLKDQSR=>eclkdqsr2, + DQCLK0=>dqclk02, DQCLK1=>dqclk12); + + Inst4_DQSBUFD1: DQSBUFD + generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC", + DYNDEL_TYPE=> "NORMAL") + port map (DQSI=>buf_clk_1, SCLK=>clkok, READ=>reset_1, + DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_1, + DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, + DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, + DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, + DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw1, + DDRCLKPOL=>ddrclkpol1, PRMBDET=>prmbdet1, + DATAVALID=>datavalid1, DDRLAT=>ddrlat1, ECLKDQSR=>eclkdqsr1, + DQCLK0=>dqclk01, DQCLK1=>dqclk11); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + Inst4_DQSBUFD0: DQSBUFD + generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC", + DYNDEL_TYPE=> "NORMAL") + port map (DQSI=>buf_clk_0, SCLK=>clkok, READ=>reset_0, + DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_0, + DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, + DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, + DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, + DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw0, + DDRCLKPOL=>ddrclkpol0, PRMBDET=>prmbdet0, + DATAVALID=>datavalid0, DDRLAT=>ddrlat0, ECLKDQSR=>eclkdqsr0, + DQCLK0=>dqclk00, DQCLK1=>dqclk10); + + Inst3_DQSDLLB: DQSDLLB + generic map (LOCK_SENSITIVITY=> "LOW") + port map (CLK=>clkos, RST=>dqsdll_reset, + UDDCNTLN=>dqsdll_uddcntln, LOCK=>dqsdll_lock, DQSDEL=>dqsdel); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + Inst2_CLKDIVB: CLKDIVB + port map (CLKI=>eclk, RST=>clkdiv_reset, RELEASE=>scuba_vhi, + CDIV1=>cdiv1, CDIV2=>clkok, CDIV4=>cdiv4, CDIV8=>cdiv8); + + Inst1_IB5: IB + port map (I=>clk_5, O=>buf_clk_5); + + Inst1_IB4: IB + port map (I=>clk_4, O=>buf_clk_4); + + Inst1_IB3: IB + port map (I=>clk_3, O=>buf_clk_3); + + Inst1_IB2: IB + port map (I=>clk_2, O=>buf_clk_2); + + Inst1_IB1: IB + port map (I=>clk_1, O=>buf_clk_1); + + Inst1_IB0: IB + port map (I=>clk_0, O=>buf_clk_0); + + q_5(19) <= qb129; + q_5(18) <= qb128; + q_5(17) <= qb127; + q_5(16) <= qb126; + q_5(15) <= qb125; + q_5(14) <= qa129; + q_5(13) <= qa128; + q_5(12) <= qa127; + q_5(11) <= qa126; + q_5(10) <= qa125; + q_5(9) <= qb029; + q_5(8) <= qb028; + q_5(7) <= qb027; + q_5(6) <= qb026; + q_5(5) <= qb025; + q_5(4) <= qa029; + q_5(3) <= qa028; + q_5(2) <= qa027; + q_5(1) <= qa026; + q_5(0) <= qa025; + datain_t29 <= datain_5i_t4; + datain_t28 <= datain_5i_t3; + datain_t27 <= datain_5i_t2; + datain_t26 <= datain_5i_t1; + datain_t25 <= datain_5i_t0; + q_4(19) <= qb124; + q_4(18) <= qb123; + q_4(17) <= qb122; + q_4(16) <= qb121; + q_4(15) <= qb120; + q_4(14) <= qa124; + q_4(13) <= qa123; + q_4(12) <= qa122; + q_4(11) <= qa121; + q_4(10) <= qa120; + q_4(9) <= qb024; + q_4(8) <= qb023; + q_4(7) <= qb022; + q_4(6) <= qb021; + q_4(5) <= qb020; + q_4(4) <= qa024; + q_4(3) <= qa023; + q_4(2) <= qa022; + q_4(1) <= qa021; + q_4(0) <= qa020; + datain_t24 <= datain_4i_t4; + datain_t23 <= datain_4i_t3; + datain_t22 <= datain_4i_t2; + datain_t21 <= datain_4i_t1; + datain_t20 <= datain_4i_t0; + q_3(19) <= qb119; + q_3(18) <= qb118; + q_3(17) <= qb117; + q_3(16) <= qb116; + q_3(15) <= qb115; + q_3(14) <= qa119; + q_3(13) <= qa118; + q_3(12) <= qa117; + q_3(11) <= qa116; + q_3(10) <= qa115; + q_3(9) <= qb019; + q_3(8) <= qb018; + q_3(7) <= qb017; + q_3(6) <= qb016; + q_3(5) <= qb015; + q_3(4) <= qa019; + q_3(3) <= qa018; + q_3(2) <= qa017; + q_3(1) <= qa016; + q_3(0) <= qa015; + datain_t19 <= datain_3i_t4; + datain_t18 <= datain_3i_t3; + datain_t17 <= datain_3i_t2; + datain_t16 <= datain_3i_t1; + datain_t15 <= datain_3i_t0; + q_2(19) <= qb114; + q_2(18) <= qb113; + q_2(17) <= qb112; + q_2(16) <= qb111; + q_2(15) <= qb110; + q_2(14) <= qa114; + q_2(13) <= qa113; + q_2(12) <= qa112; + q_2(11) <= qa111; + q_2(10) <= qa110; + q_2(9) <= qb014; + q_2(8) <= qb013; + q_2(7) <= qb012; + q_2(6) <= qb011; + q_2(5) <= qb010; + q_2(4) <= qa014; + q_2(3) <= qa013; + q_2(2) <= qa012; + q_2(1) <= qa011; + q_2(0) <= qa010; + datain_t14 <= datain_2i_t4; + datain_t13 <= datain_2i_t3; + datain_t12 <= datain_2i_t2; + datain_t11 <= datain_2i_t1; + datain_t10 <= datain_2i_t0; + q_1(19) <= qb19; + q_1(18) <= qb18; + q_1(17) <= qb17; + q_1(16) <= qb16; + q_1(15) <= qb15; + q_1(14) <= qa19; + q_1(13) <= qa18; + q_1(12) <= qa17; + q_1(11) <= qa16; + q_1(10) <= qa15; + q_1(9) <= qb09; + q_1(8) <= qb08; + q_1(7) <= qb07; + q_1(6) <= qb06; + q_1(5) <= qb05; + q_1(4) <= qa09; + q_1(3) <= qa08; + q_1(2) <= qa07; + q_1(1) <= qa06; + q_1(0) <= qa05; + datain_t9 <= datain_1i_t4; + datain_t8 <= datain_1i_t3; + datain_t7 <= datain_1i_t2; + datain_t6 <= datain_1i_t1; + datain_t5 <= datain_1i_t0; + q_0(19) <= qb14; + q_0(18) <= qb13; + q_0(17) <= qb12; + q_0(16) <= qb11; + q_0(15) <= qb10; + q_0(14) <= qa14; + q_0(13) <= qa13; + q_0(12) <= qa12; + q_0(11) <= qa11; + q_0(10) <= qa10; + q_0(9) <= qb04; + q_0(8) <= qb03; + q_0(7) <= qb02; + q_0(6) <= qb01; + q_0(5) <= qb00; + q_0(4) <= qa04; + q_0(3) <= qa03; + q_0(2) <= qa02; + q_0(1) <= qa01; + q_0(0) <= qa00; + datain_t4 <= datain_0i_t4; + datain_t3 <= datain_0i_t3; + datain_t2 <= datain_0i_t2; + datain_t1 <= datain_0i_t1; + datain_t0 <= datain_0i_t0; + dqsdll_uddcntln <= scuba_vhi; + dqsdll_reset <= scuba_vhi; + clkos <= eclk; + sclk_t <= clkok; + sclk <= sclk_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of dqsinput_6x5 is + for Structure + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:IB use entity ecp3.IB(V); end for; + for all:CLKDIVB use entity ecp3.CLKDIVB(V); end for; + for all:IDDRX2D use entity ecp3.IDDRX2D(V); end for; + for all:DQSBUFD use entity ecp3.DQSBUFD(V); end for; + for all:DQSDLLB use entity ecp3.DQSDLLB(V); end for; + for all:DELAYC use entity ecp3.DELAYC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on