From: hadeshyp <hadeshyp>
Date: Wed, 19 Oct 2011 12:02:37 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~98
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5b19ee5291496633dceb50a088c448a4ff1c2491;p=trbnet.git

*** empty log message ***
---

diff --git a/xilinx/virtex4/lattice_ecp2m_fifo.vhd b/xilinx/virtex4/lattice_ecp2m_fifo.vhd
new file mode 100644
index 0000000..1b5b553
--- /dev/null
+++ b/xilinx/virtex4/lattice_ecp2m_fifo.vhd
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+package lattice_ecp2m_fifo is
+
+  component fifo_var_oreg is
+    generic(
+      FIFO_WIDTH                   : integer range 1 to 64 := 36;
+      FIFO_DEPTH                   : integer range 1 to 16 := 8
+      );
+    port(
+      Data                         : in  std_logic_vector(FIFO_WIDTH-1 downto 0);
+      Clock                        : in  std_logic;
+      WrEn                         : in  std_logic;
+      RdEn                         : in  std_logic;
+      Reset                        : in  std_logic;
+      AmFullThresh                 : in  std_logic_vector(FIFO_DEPTH-1 downto 0);
+      Q                            : out std_logic_vector(FIFO_WIDTH-1 downto 0);
+      WCNT                         : out std_logic_vector(FIFO_DEPTH downto 0);
+      Empty                        : out std_logic;
+      Full                         : out std_logic;
+      AlmostFull                   : out std_logic
+      );
+  end component;
+
+end package;