From: Cahit Date: Wed, 9 Dec 2015 10:51:29 +0000 (+0100) Subject: updated the release notes table and edited export script for new org-mode version 8 X-Git-Tag: v2.3~59 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5b1a9a60cfcd8995781e87f04bae579feda358a1;p=tdc.git updated the release notes table and edited export script for new org-mode version 8 --- diff --git a/releases/ReleaseNotes.org b/releases/ReleaseNotes.org index e6697f0..301b1cb 100644 --- a/releases/ReleaseNotes.org +++ b/releases/ReleaseNotes.org @@ -1,100 +1,95 @@ -#+ATTR_LATEX: :environment longtable: align=|l|l|p{10cm}| #+CAPTION: TDC versions release information. #+LABEL: tab:tdcVersionTable - -#+BEGIN_CENTER -|-------------+----------------+----------------------------------------------------------------------------------| -| *Version* | *Release Date* | *Release Notes* | -|-------------+----------------+----------------------------------------------------------------------------------| -| | | <80> | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v2.4* | 08.03.2015 | Faster clock (400 MHz) for the delay line is used. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v2.3 | 08.12.2015 | Trailer word is introduced to mark some error bits. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v2.2 | 07.10.2015 | The delay line size is decreased to 288 from 304. | -| | | The trigger window end and coarse counter reset signals are distributed via SECONDARY clock nets | -| | | A bug in the semi-asynchronous stretcher (combinatoral reset signal caused blockage) is removed. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v2.1.5 | 22.06.2015 | Extra coarse counter reset register for higher frequency. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v2.1.4 | 17.06.2015 | Several bug fixes for the stretcher option. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v2.1.2 | 28.01.2015 | In case of a missing reference time a header error bit is set and DAQ keeps running. | -| | | Grass hits in ToT with calbration trigger is removed. The ToT mean value - 10ns gives the stretching offset of the channel. | -| | | Channel invert bits are implemented. | -| | | Trigger window bugfix. | -| | | Resource usages in Channel\_200 and Channel entity are decreased. | -| | | Hit detection is increased to 2 bits. | -| | | Coarse counter number is increased to channel number for better timing. | -| | | Instead of the internal oscillator 125MHz clock input is used for the calibration. | -| | | | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v2.1.1 | 28.01.2015 | The dead time of the TDC is decreased to 20ns. | -| | | Small bug with "Light Mode" is removed. | -| | | "Data Limit" parameter is removed, as it is not needed due to the dynamic buffer size. | -| | | Coarse/Epoch counter misallignment bug is fixed. | -| | | Channel input is blocked until the falling edge information is written in the ring buffer to avoid data mismatch. | -| | | Ring buffer overwrite bit is implemented. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v2.1.0 | 15.12.2014 | The ring buffer almost full threshold is made dynamic in order to "mimic" a adjustable ring buffer size. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v2.0.1 | 05.12.2014 | Calibration-physik trigger switching problem is fixed. | -| | | With the calibration trigger 50ns pulses are sent to the channels in order to calibrate the ToT measurements in the channels. There are some grass hits around the main peak. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v2.0 | 01.12.2014 | Double edge detection in a single channel is implemented. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v1.7.3 | 15.08.2014 | Hit scaler register size is increased to 31 bits. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v1.7.1 | 29.07.2014 | Feature Bit support. | -| | | Tidy up the entities. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v1.7 | 24.06.2014 | Paralel working Readouts are implemented. | -| | | Trigger time calculation is done in the trigger handler. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v1.6.3 | 24.06.2014 | Bug fix in the hit rate counters (syncronisation problem). | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v1.6.2 | 08.05.2014 | Small bug fix in the wait time for data transfer to buffer. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v1.6.1 | 06.05.2014 | Less EPOCH counter - unnecessary EPOCH words, which occur with enabled trigger window, are eliminated from the data stream. | -| | | FSM initialisation problem by the Channel\_200 entity is solved. | -| | | Channel FSM debug words are written to bus 0xc200. | -| | | Number of coarse counters is increased to 16 to ease the fanout. | -| | | Bug fix for the missing data with the calibration trigger. | -| | | Bug fix for the duplicate data when trigger window is enabled. | -| | | | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v1.6 | 20.01.2014 | Epoch counter bug fix (data word - epoch word place swap). | -| | | Trigger window bug fix (epoch counter more than 24 bit had integer conversion problem. Trigger window right side control is enabled). | -| | | Readout algorith change (the channel fifos are readout to intermediate buffer, so the later channels in the readout order are kept as the trigger arrival time). | -| | | Trigger on TDC channel (the feature for triggering on TDC channel is implemented) Reference channel hit rate counter implemented. | -| | | The channels (incl. ch0) can be calibrated with the internal oscillator with different frequencies (see manual slow control registers). | -| | | The coarse counter can be set to reset via slow control. The action will take place when the first valid trigger arrives. | -| | | | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v1.5.1 | 20.06.2013 | Efficiency bug fix (epoch counter update - hit at the same time). Hit level bit bug fix for the web server. Reference Channel coarse counter alignmet fix. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v1.5 | 03.05.2013 | TDC calibration trigger is implemented in order to shoot every channel with sufficient # of hits for proper calibration. Also the TDC is adapted for short pulses. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v1.4 | 18.04.2013 | Limiting data transfer functionality is added. Use 0xc804 register to define the # of word per channel to be read-out. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v1.3 | 05.03.2013 | Encoder efficiency is increased to 100%. Extra bits are encoded in the data (low resolution and no successfull binary conversion, see the manual). | -| | | Channel block during the readout is removed. Only the relevant hits per trigger are readout. | -| | | Control registers are moved to 0xc800. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v1.2 | 12.11.2012 | First strecher prototype is successfully implemented. Some bugs are fixed. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v1.1.1 | 07.11.2012 | The status registers are moved to the bus address 0xc100. Also debug registers (encoder start, fifo write, lost hits) are included in the bus - 0xc200 0xc300 0xc400 | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v1.1 | 26.10.2012 | Readout process is collected in an individual entity. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v1.0 | 25.10.2012 | The time measurement interval is extended with a 28-bit epoch counter. | -|-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v0.5 | 22.10.2012 | Hit counter registers and LVDS receiver output level can be reached via slow control. | -|-------------+----------------+----------------------------------------------------------------------------------| -| | | * Design under construction... | -|-------------+----------------+----------------------------------------------------------------------------------| - - - -#+END_CENTER +#+OPTIONS: ^:nil +#+ATTR_LATEX: :environment longtable :align |l|l|p{10cm}| +|------------+----------------+----------------------------------------------------------------------------------| +| *Version* | *Release Date* | *Release Notes* | +|------------+----------------+----------------------------------------------------------------------------------| +| | | <80> | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v2.4* | 08.03.2015 | Faster clock (400 MHz) for the delay line is used. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v2.3 | 08.12.2015 | Trailer word is introduced to mark some error bits. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v2.2 | 07.10.2015 | The delay line size is decreased to 288 from 304. | +| | | The trigger window end and coarse counter reset signals are distributed via SECONDARY clock nets | +| | | A bug in the semi-asynchronous stretcher (combinatoral reset signal caused blockage) is removed. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v2.1.5 | 22.06.2015 | Extra coarse counter reset register for higher frequency. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v2.1.4 | 17.06.2015 | Several bug fixes for the stretcher option. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v2.1.2 | 28.01.2015 | In case of a missing reference time a header error bit is set and DAQ keeps running. | +| | | Grass hits in ToT with calbration trigger is removed. The ToT mean value - 10ns gives the stretching offset of the channel. | +| | | Channel invert bits are implemented. | +| | | Trigger window bugfix. | +| | | Resource usages in Channel_200 and Channel entity are decreased. | +| | | Hit detection is increased to 2 bits. | +| | | Coarse counter number is increased to channel number for better timing. | +| | | Instead of the internal oscillator 125MHz clock input is used for the calibration. | +| | | | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v2.1.1 | 28.01.2015 | The dead time of the TDC is decreased to 20ns. | +| | | Small bug with "Light Mode" is removed. | +| | | "Data Limit" parameter is removed, as it is not needed due to the dynamic buffer size. | +| | | Coarse/Epoch counter misallignment bug is fixed. | +| | | Channel input is blocked until the falling edge information is written in the ring buffer to avoid data mismatch. | +| | | Ring buffer overwrite bit is implemented. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v2.1.0 | 15.12.2014 | The ring buffer almost full threshold is made dynamic in order to "mimic" a adjustable ring buffer size. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v2.0.1 | 05.12.2014 | Calibration-physik trigger switching problem is fixed. | +| | | With the calibration trigger 50ns pulses are sent to the channels in order to calibrate the ToT measurements in the channels. There are some grass hits around the main peak. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v2.0 | 01.12.2014 | Double edge detection in a single channel is implemented. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v1.7.3 | 15.08.2014 | Hit scaler register size is increased to 31 bits. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v1.7.1 | 29.07.2014 | Feature Bit support. | +| | | Tidy up the entities. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v1.7 | 24.06.2014 | Paralel working Readouts are implemented. | +| | | Trigger time calculation is done in the trigger handler. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v1.6.3 | 24.06.2014 | Bug fix in the hit rate counters (syncronisation problem). | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v1.6.2 | 08.05.2014 | Small bug fix in the wait time for data transfer to buffer. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v1.6.1 | 06.05.2014 | Less EPOCH counter - unnecessary EPOCH words, which occur with enabled trigger window, are eliminated from the data stream. | +| | | FSM initialisation problem by the Channel_200 entity is solved. | +| | | Channel FSM debug words are written to bus 0xc200. | +| | | Number of coarse counters is increased to 16 to ease the fanout. | +| | | Bug fix for the missing data with the calibration trigger. | +| | | Bug fix for the duplicate data when trigger window is enabled. | +| | | | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v1.6 | 20.01.2014 | Epoch counter bug fix (data word - epoch word place swap). | +| | | Trigger window bug fix (epoch counter more than 24 bit had integer conversion problem. Trigger window right side control is enabled). | +| | | Readout algorith change (the channel fifos are readout to intermediate buffer, so the later channels in the readout order are kept as the trigger arrival time). | +| | | Trigger on TDC channel (the feature for triggering on TDC channel is implemented) Reference channel hit rate counter implemented. | +| | | The channels (incl. ch0) can be calibrated with the internal oscillator with different frequencies (see manual slow control registers). | +| | | The coarse counter can be set to reset via slow control. The action will take place when the first valid trigger arrives. | +| | | | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v1.5.1 | 20.06.2013 | Efficiency bug fix (epoch counter update - hit at the same time). Hit level bit bug fix for the web server. Reference Channel coarse counter alignmet fix. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v1.5 | 03.05.2013 | TDC calibration trigger is implemented in order to shoot every channel with sufficient # of hits for proper calibration. Also the TDC is adapted for short pulses. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v1.4 | 18.04.2013 | Limiting data transfer functionality is added. Use 0xc804 register to define the # of word per channel to be read-out. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v1.3 | 05.03.2013 | Encoder efficiency is increased to 100%. Extra bits are encoded in the data (low resolution and no successfull binary conversion, see the manual). | +| | | Channel block during the readout is removed. Only the relevant hits per trigger are readout. | +| | | Control registers are moved to 0xc800. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v1.2 | 12.11.2012 | First strecher prototype is successfully implemented. Some bugs are fixed. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v1.1.1 | 07.11.2012 | The status registers are moved to the bus address 0xc100. Also debug registers (encoder start, fifo write, lost hits) are included in the bus - 0xc200 0xc300 0xc400 | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v1.1 | 26.10.2012 | Readout process is collected in an individual entity. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v1.0 | 25.10.2012 | The time measurement interval is extended with a 28-bit epoch counter. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v0.5 | 22.10.2012 | Hit counter registers and LVDS receiver output level can be reached via slow control. | +|------------+----------------+----------------------------------------------------------------------------------| +| | | * Design under construction... | +|------------+----------------+----------------------------------------------------------------------------------| diff --git a/releases/export_table.pl b/releases/export_table.pl index 7c735e6..dc696f9 100755 --- a/releases/export_table.pl +++ b/releases/export_table.pl @@ -12,8 +12,7 @@ my $outfile = "ReleaseNotesEdited.tex"; my $skip = 1; # export the tex file from org mode -system("touch ReleaseNotes.tex"); -system("emacs ReleaseNotes.org --batch -f org-export-as-latex --kill"); +system("emacs ReleaseNotes.org --batch -f org-latex-export-to-latex --kill"); # edit tex file to suit the main documentation open(DATA, "< $sourcedata") || die $!; @@ -23,13 +22,15 @@ print FILE "% Automatically generated by the scprip trb3/tdc_releases/export_tab while(my $file = ) { - my @buffer = split(/\s+/, $file); - - $skip = 1 if ($buffer[0] eq '\end{document}'); - - next if (($buffer[0] ne '\begin{center}') && $skip); + my @buffer = split(/\n/, $file); +# print "$buffer[0]\n"; +# print "start skipping\n" if ($buffer[0] =~ /end\{document\}/); + $skip = 1 if ($buffer[0] =~ /end\{document\}/); +# print "stop skipping\n" if (($buffer[0] !~ /begin\{longtable\}/) && $skip); + next if (($buffer[0] !~ /begin\{longtable\}/) && $skip); $skip = 0; - print FILE "@buffer\n"; + print FILE "$buffer[0]\n"; +# print "writing line: $buffer[0]\n"; } close(DATA); close(FILE);