From: Cahit Date: Mon, 20 Jan 2014 16:10:58 +0000 (+0100) Subject: first version of the tdc_v1.6 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5b97125cceff9ef52677a639f1ffb6ef23141e19;p=trb3.git first version of the tdc_v1.6 --- diff --git a/32PinAddOn/compile_constraints.pl b/32PinAddOn/compile_constraints.pl new file mode 100755 index 0000000..346074d --- /dev/null +++ b/32PinAddOn/compile_constraints.pl @@ -0,0 +1,13 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; + +my $TOPNAME = "trb3_periph_32PinAddOn"; #Name of top-level entity + + +#create full lpf file +system("cp ../base/trb3_periph_32PinAddOn.lpf diamond/$TOPNAME.lpf"); +system("cat currentRelease/trbnet_constraints.lpf >> diamond/$TOPNAME.lpf"); +system("cat currentRelease/tdc_constraints.lpf >> diamond/$TOPNAME.lpf"); + diff --git a/32PinAddOn/trb3_periph_32PinAddOn.vhd b/32PinAddOn/trb3_periph_32PinAddOn.vhd new file mode 100644 index 0000000..dc829ae --- /dev/null +++ b/32PinAddOn/trb3_periph_32PinAddOn.vhd @@ -0,0 +1,824 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + + +entity trb3_periph_32PinAddOn is + port( + --Clocks + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + --Trigger + TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out + TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out + --Serdes + CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible + CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems + SERDES_INT_TX : out std_logic_vector(3 downto 0); + SERDES_INT_RX : in std_logic_vector(3 downto 0); + SERDES_ADDON_TX : out std_logic_vector(11 downto 0); + SERDES_ADDON_RX : in std_logic_vector(11 downto 0); + --Inter-FPGA Communication + FPGA5_COMM : inout std_logic_vector(11 downto 0); + --Bit 0/1 input, serial link RX active + --Bit 2/3 output, serial link TX active + --Connection to ADA AddOn + SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only + INP : in std_logic_vector(63 downto 0); + --DAC + DAC_IN_SDI : in std_logic; + DAC_OUT_SDO : out std_logic; + DAC_OUT_SCK : out std_logic; + DAC_OUT_CS : out std_logic; + DAC_OUT_CLR : out std_logic; + + --Flash ROM & Reboot + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_DIN : out std_logic; + FLASH_DOUT : in std_logic; + PROGRAMN : out std_logic; --reboot FPGA + --Misc + TEMPSENS : inout std_logic; --Temperature Sensor + CODE_LINE : in std_logic_vector(1 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + SUPPL : in std_logic; --terminated diff pair, PCLK, Pads + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + attribute syn_useioff of CODE_LINE : signal is false; + attribute syn_useioff of TRIGGER_LEFT : signal is false; + attribute syn_useioff of TRIGGER_RIGHT : signal is false; + --important signals + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_DIN : signal is true; + attribute syn_useioff of FLASH_DOUT : signal is true; + attribute syn_useioff of FPGA5_COMM : signal is true; + attribute syn_useioff of TEST_LINE : signal is true; + attribute syn_useioff of INP : signal is false; + attribute syn_useioff of SPARE_LINE : signal is true; + attribute syn_useioff of DAC_IN_SDI : signal is true; + attribute syn_useioff of DAC_OUT_SDO : signal is true; + attribute syn_useioff of DAC_OUT_SCK : signal is true; + attribute syn_useioff of DAC_OUT_CS : signal is true; + attribute syn_useioff of DAC_OUT_CLR : signal is true; + + +end entity; + + +architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is + --Constants + constant REGIO_NUM_STAT_REGS : integer := 3; + constant REGIO_NUM_CTRL_REGS : integer := 3; + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + --Clock / Reset + signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal clk_125_i : std_logic; -- 125 MHz, via Clock Manager and bypassed PLL + signal clk_20_i : std_logic; -- clock for calibrating the tdc, 20 MHz, via Clock Manager and internal PLL + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + --Media Interface + signal med_stat_op : std_logic_vector (1*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med_data_out : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); + signal med_dataready_out : std_logic; + signal med_read_out : std_logic; + signal med_data_in : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); + signal med_dataready_in : std_logic; + signal med_read_in : std_logic; + + --LVL1 channel + signal timing_trg_received_i : std_logic; + signal trg_data_valid_i : std_logic; + signal trg_timing_valid_i : std_logic; + signal trg_notiming_valid_i : std_logic; + signal trg_invalid_i : std_logic; + signal trg_type_i : std_logic_vector(3 downto 0); + signal trg_number_i : std_logic_vector(15 downto 0); + signal trg_code_i : std_logic_vector(7 downto 0); + signal trg_information_i : std_logic_vector(23 downto 0); + signal trg_int_number_i : std_logic_vector(15 downto 0); + signal trg_multiple_trg_i : std_logic; + signal trg_timeout_detected_i : std_logic; + signal trg_spurious_trg_i : std_logic; + signal trg_missing_tmg_trg_i : std_logic; + signal trg_spike_detected_i : std_logic; + + --Data channel + signal fee_trg_release_i : std_logic; + signal fee_trg_statusbits_i : std_logic_vector(31 downto 0); + signal fee_data_i : std_logic_vector(31 downto 0); + signal fee_data_write_i : std_logic; + signal fee_data_finished_i : std_logic; + signal fee_almost_full_i : std_logic; + + --Slow Control channel + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); + + --RegIO + signal regio_addr_out : std_logic_vector (15 downto 0); + signal regio_read_enable_out : std_logic; + signal regio_write_enable_out : std_logic; + signal regio_data_out : std_logic_vector (31 downto 0); + signal regio_data_in : std_logic_vector (31 downto 0); + signal regio_dataready_in : std_logic; + signal regio_no_more_data_in : std_logic; + signal regio_write_ack_in : std_logic; + signal regio_unknown_addr_in : std_logic; + signal regio_timeout_out : std_logic; + + --Timer + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_ticks : std_logic_vector(1 downto 0); + + --Flash + signal spictrl_read_en : std_logic; + signal spictrl_write_en : std_logic; + signal spictrl_data_in : std_logic_vector(31 downto 0); + signal spictrl_addr : std_logic; + signal spictrl_data_out : std_logic_vector(31 downto 0); + signal spictrl_ack : std_logic; + signal spictrl_busy : std_logic; + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(5 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_ack : std_logic; + signal spidac_read_en : std_logic; + signal spidac_write_en : std_logic; + signal spidac_data_in : std_logic_vector(31 downto 0); + signal spidac_addr : std_logic_vector(4 downto 0); + signal spidac_data_out : std_logic_vector(31 downto 0); + signal spidac_ack : std_logic; + signal spidac_busy : std_logic; + + signal dac_cs_i : std_logic_vector(3 downto 0); + signal dac_sck_i : std_logic; + signal dac_sdi_i : std_logic; + + signal hitreg_read_en : std_logic; + signal hitreg_write_en : std_logic; + signal hitreg_addr : std_logic_vector(6 downto 0); + signal hitreg_data_out : std_logic_vector(31 downto 0); + signal hitreg_data_ready : std_logic; + signal hitreg_invalid : std_logic; + + signal srb_read_en : std_logic; + signal srb_write_en : std_logic; + signal srb_addr : std_logic_vector(6 downto 0); + signal srb_data_out : std_logic_vector(31 downto 0); + signal srb_data_ready : std_logic; + signal srb_invalid : std_logic; + + signal lhb_read_en : std_logic; + signal lhb_write_en : std_logic; + signal lhb_addr : std_logic_vector(6 downto 0); + signal lhb_data_out : std_logic_vector(31 downto 0); + signal lhb_data_ready : std_logic; + signal lhb_invalid : std_logic; + + signal esb_read_en : std_logic; + signal esb_write_en : std_logic; + signal esb_addr : std_logic_vector(6 downto 0); + signal esb_data_out : std_logic_vector(31 downto 0); + signal esb_data_ready : std_logic; + signal esb_invalid : std_logic; + + signal efb_read_en : std_logic; + signal efb_write_en : std_logic; + signal efb_addr : std_logic_vector(6 downto 0); + signal efb_data_out : std_logic_vector(31 downto 0); + signal efb_data_ready : std_logic; + signal efb_invalid : std_logic; + + signal tdc_ctrl_read : std_logic; + signal last_tdc_ctrl_read : std_logic; + signal tdc_ctrl_write : std_logic; + signal tdc_ctrl_addr : std_logic_vector(2 downto 0); + signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); + signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); + signal tdc_ctrl_reg : std_logic_vector(5*32+31 downto 0); + + signal spi_bram_addr : std_logic_vector(7 downto 0); + signal spi_bram_wr_d : std_logic_vector(7 downto 0); + signal spi_bram_rd_d : std_logic_vector(7 downto 0); + signal spi_bram_we : std_logic; + + --TDC + signal hit_in_i : std_logic_vector(64 downto 1); + signal logic_analyser_i : std_logic_vector(15 downto 0); + +begin +--------------------------------------------------------------------------- +-- Reset Generation +--------------------------------------------------------------------------- + + GSR_N <= pll_lock; + + THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + + +--------------------------------------------------------------------------- +-- Clock Handling +--------------------------------------------------------------------------- + THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_RIGHT, + CLKOP => clk_100_i, + CLKOK => clk_200_i, + LOCK => pll_lock + ); + + -- generates hits for calibration uncorrelated with tdc clk + THE_CALIBRATION_PLL : pll_in125_out20 + port map ( + CLK => CLK_GPLL_LEFT, + CLKOP => clk_20_i, + CLKOK => clk_125_i, + LOCK => open); + +--------------------------------------------------------------------------- +-- The TrbNet media interface (to other FPGA) +--------------------------------------------------------------------------- + THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp + generic map( + SERDES_NUM => 1, --number of serdes in quad + EXT_CLOCK => c_NO, --use internal clock + USE_200_MHZ => c_YES, --run on 200 MHz clock + USE_125_MHZ => c_NO, + USE_CTC => c_NO + ) + port map( + CLK => clk_200_i, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => med_data_out, + MED_PACKET_NUM_IN => med_packet_num_out, + MED_DATAREADY_IN => med_dataready_out, + MED_READ_OUT => med_read_in, + MED_DATA_OUT => med_data_in, + MED_PACKET_NUM_OUT => med_packet_num_in, + MED_DATAREADY_OUT => med_dataready_in, + MED_READ_IN => med_read_out, + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => SERDES_INT_RX(2), + SD_RXD_N_IN => SERDES_INT_RX(3), + SD_TXD_P_OUT => SERDES_INT_TX(2), + SD_TXD_N_OUT => SERDES_INT_TX(3), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => FPGA5_COMM(0), + SD_LOS_IN => FPGA5_COMM(0), + SD_TXDIS_OUT => FPGA5_COMM(2), + -- Status and control port + STAT_OP => med_stat_op, + CTRL_OP => med_ctrl_op, + STAT_DEBUG => med_stat_debug, + CTRL_DEBUG => (others => '0') + ); + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + --regio_hardware_version_i <= x"9100" & addOn_type_i & edge_type_i & tdc_channel_no_i & x"0"; + + --addOn_type_i <= x"0"; -- x"0" - ADA AddOn version 1 + -- -- x"1" - ADA AddOn version 2 + -- -- x"2" - multi purpose test AddOn + -- -- x"3" - SFP hub AddOn + -- -- x"4" - Wasa AddOn + -- -- x"5" - GeneralPurpose AddOn + -- -- x"6" - Nxyter + -- -- x"7" - 32PinAddOn + --edge_type_i <= x"0"; -- x"0" - single edge + -- -- x"1" - double edge + -- -- x"4" - has spi interface + -- -- x"8" - double edge on consecutive channels + --tdc_channel_no_i <= x"6"; -- 2^n channels + + THE_ENDPOINT : trb_net16_endpoint_hades_full_handler + generic map( + REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg + REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + BROADCAST_SPECIAL_ADDR => x"48", + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), + REGIO_HARDWARE_VERSION => x"91007C60", -- regio_hardware_version_i, + REGIO_INIT_ADDRESS => x"f305", + REGIO_USE_VAR_ENDPOINT_ID => c_YES, + CLOCK_FREQUENCY => 100, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 13, --13 + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-(maximal 2**12) + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + MED_DATAREADY_OUT => med_dataready_out, -- open, -- + MED_DATA_OUT => med_data_out, -- open, -- + MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, -- open, -- + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, + LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, + LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, + LVL1_INVALID_TRG_OUT => trg_invalid_i, + + LVL1_TRG_TYPE_OUT => trg_type_i, + LVL1_TRG_NUMBER_OUT => trg_number_i, + LVL1_TRG_CODE_OUT => trg_code_i, + LVL1_TRG_INFORMATION_OUT => trg_information_i, + LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, + + --Information about trigger handler errors + TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i, + TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i, + TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i, + TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i, + TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i, + + --Response from FEE + FEE_TRG_RELEASE_IN(0) => fee_trg_release_i, + FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i, + FEE_DATA_IN => fee_data_i, + FEE_DATA_WRITE_IN(0) => fee_data_write_i, + FEE_DATA_FINISHED_IN(0) => fee_data_finished_i, + FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i, + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, + REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, + REGIO_STAT_REG_IN => stat_reg, --start 0x80 + REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 + REGIO_STAT_STROBE_OUT => stat_reg_strobe, + REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), + + BUS_ADDR_OUT => regio_addr_out, + BUS_READ_ENABLE_OUT => regio_read_enable_out, + BUS_WRITE_ENABLE_OUT => regio_write_enable_out, + BUS_DATA_OUT => regio_data_out, + BUS_DATA_IN => regio_data_in, + BUS_DATAREADY_IN => regio_dataready_in, + BUS_NO_MORE_DATA_IN => regio_no_more_data_in, + BUS_WRITE_ACK_IN => regio_write_ack_in, + BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + BUS_TIMEOUT_OUT => regio_timeout_out, + ONEWIRE_INOUT => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + + TIME_GLOBAL_OUT => global_time, + TIME_LOCAL_OUT => local_time, + TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, + TIME_TICKS_OUT => timer_ticks, + + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => open, + STAT_DEBUG_2 => open, + STAT_DEBUG_DATA_HANDLER_OUT => open, + STAT_DEBUG_IPU_HANDLER_OUT => open, + STAT_TRIGGER_OUT => open, + CTRL_MPLEX => (others => '0'), + IOBUF_CTRL_GEN => (others => '0'), + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open, + DEBUG_LVL1_HANDLER_OUT => open + ); + + timing_trg_received_i <= TRIGGER_LEFT; --TRIGGER_RIGHT; -- + common_stat_reg <= (others => '0'); + stat_reg <= (others => '0'); + +--------------------------------------------------------------------------- +-- AddOn +--------------------------------------------------------------------------- + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : trb_net16_regio_bus_handler + generic map( + PORT_NUMBER => 9, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 3, others => 0) + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + + --Bus Handler (SPI CTRL) + BUS_READ_ENABLE_OUT(0) => spictrl_read_en, + BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, + BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, + BUS_ADDR_OUT(0*16) => spictrl_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, + BUS_DATAREADY_IN(0) => spictrl_ack, + BUS_WRITE_ACK_IN(0) => spictrl_ack, + BUS_NO_MORE_DATA_IN(0) => spictrl_busy, + BUS_UNKNOWN_ADDR_IN(0) => '0', + --Bus Handler (SPI Memory) + BUS_READ_ENABLE_OUT(1) => spimem_read_en, + BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, + BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, + BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, + BUS_DATAREADY_IN(1) => spimem_ack, + BUS_WRITE_ACK_IN(1) => spimem_ack, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', + --Bus Handler (SPI DAC) + BUS_READ_ENABLE_OUT(2) => spidac_read_en, + BUS_WRITE_ENABLE_OUT(2) => spidac_write_en, + BUS_DATA_OUT(2*32+31 downto 2*32) => spidac_data_in, + BUS_ADDR_OUT(2*16+4 downto 2*16) => spidac_addr, + BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATA_IN(2*32+31 downto 2*32) => spidac_data_out, + BUS_DATAREADY_IN(2) => spidac_ack, + BUS_WRITE_ACK_IN(2) => spidac_ack, + BUS_NO_MORE_DATA_IN(2) => spidac_busy, + BUS_UNKNOWN_ADDR_IN(2) => '0', + --HitRegisters + BUS_READ_ENABLE_OUT(3) => hitreg_read_en, + BUS_WRITE_ENABLE_OUT(3) => hitreg_write_en, + BUS_DATA_OUT(3*32+31 downto 3*32) => open, + BUS_ADDR_OUT(3*16+6 downto 3*16) => hitreg_addr, + BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(3*32+31 downto 3*32) => hitreg_data_out, + BUS_DATAREADY_IN(3) => hitreg_data_ready, + BUS_WRITE_ACK_IN(3) => '0', + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => hitreg_invalid, + --Status Registers + BUS_READ_ENABLE_OUT(4) => srb_read_en, + BUS_WRITE_ENABLE_OUT(4) => srb_write_en, + BUS_DATA_OUT(4*32+31 downto 4*32) => open, + BUS_ADDR_OUT(4*16+6 downto 4*16) => srb_addr, + BUS_ADDR_OUT(4*16+15 downto 4*16+7) => open, + BUS_TIMEOUT_OUT(4) => open, + BUS_DATA_IN(4*32+31 downto 4*32) => srb_data_out, + BUS_DATAREADY_IN(4) => srb_data_ready, + BUS_WRITE_ACK_IN(4) => '0', + BUS_NO_MORE_DATA_IN(4) => '0', + BUS_UNKNOWN_ADDR_IN(4) => srb_invalid, + --Encoder Start Registers + BUS_READ_ENABLE_OUT(5) => esb_read_en, + BUS_WRITE_ENABLE_OUT(5) => esb_write_en, + BUS_DATA_OUT(5*32+31 downto 5*32) => open, + BUS_ADDR_OUT(5*16+6 downto 5*16) => esb_addr, + BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open, + BUS_TIMEOUT_OUT(5) => open, + BUS_DATA_IN(5*32+31 downto 5*32) => esb_data_out, + BUS_DATAREADY_IN(5) => esb_data_ready, + BUS_WRITE_ACK_IN(5) => '0', + BUS_NO_MORE_DATA_IN(5) => '0', + BUS_UNKNOWN_ADDR_IN(5) => esb_invalid, + --Fifo Write Registers + BUS_READ_ENABLE_OUT(6) => efb_read_en, + BUS_WRITE_ENABLE_OUT(6) => efb_write_en, + BUS_DATA_OUT(6*32+31 downto 6*32) => open, + BUS_ADDR_OUT(6*16+6 downto 6*16) => efb_addr, + BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open, + BUS_TIMEOUT_OUT(6) => open, + BUS_DATA_IN(6*32+31 downto 6*32) => efb_data_out, + BUS_DATAREADY_IN(6) => efb_data_ready, + BUS_WRITE_ACK_IN(6) => '0', + BUS_NO_MORE_DATA_IN(6) => '0', + BUS_UNKNOWN_ADDR_IN(6) => efb_invalid, + --Lost Hit Registers + BUS_READ_ENABLE_OUT(7) => lhb_read_en, + BUS_WRITE_ENABLE_OUT(7) => lhb_write_en, + BUS_DATA_OUT(7*32+31 downto 7*32) => open, + BUS_ADDR_OUT(7*16+6 downto 7*16) => lhb_addr, + BUS_ADDR_OUT(7*16+15 downto 7*16+7) => open, + BUS_TIMEOUT_OUT(7) => open, + BUS_DATA_IN(7*32+31 downto 7*32) => lhb_data_out, + BUS_DATAREADY_IN(7) => lhb_data_ready, + BUS_WRITE_ACK_IN(7) => '0', + BUS_NO_MORE_DATA_IN(7) => '0', + BUS_UNKNOWN_ADDR_IN(7) => lhb_invalid, + --TDC config registers + BUS_READ_ENABLE_OUT(8) => tdc_ctrl_read, + BUS_WRITE_ENABLE_OUT(8) => tdc_ctrl_write, + BUS_DATA_OUT(8*32+31 downto 8*32) => tdc_ctrl_data_in, + BUS_ADDR_OUT(8*16+2 downto 8*16) => tdc_ctrl_addr, + BUS_ADDR_OUT(8*16+15 downto 8*16+3) => open, + BUS_TIMEOUT_OUT(8) => open, + BUS_DATA_IN(8*32+31 downto 8*32) => tdc_ctrl_data_out, + BUS_DATAREADY_IN(8) => last_tdc_ctrl_read, + BUS_WRITE_ACK_IN(8) => tdc_ctrl_write, + BUS_NO_MORE_DATA_IN(8) => '0', + BUS_UNKNOWN_ADDR_IN(8) => '0', + + STAT_DEBUG => open + ); + + PROC_TDC_CTRL_REG : process + variable pos : integer; + begin + wait until rising_edge(clk_100_i); + pos := to_integer(unsigned(tdc_ctrl_addr))*32; + tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos); + last_tdc_ctrl_read <= tdc_ctrl_read; + if tdc_ctrl_write = '1' then + tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in; + end if; + end process; + +--------------------------------------------------------------------------- +-- SPI / Flash +--------------------------------------------------------------------------- + + THE_SPI_MASTER : spi_master + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_READ_IN => spictrl_read_en, + BUS_WRITE_IN => spictrl_write_en, + BUS_BUSY_OUT => spictrl_busy, + BUS_ACK_OUT => spictrl_ack, + BUS_ADDR_IN(0) => spictrl_addr, + BUS_DATA_IN => spictrl_data_in, + BUS_DATA_OUT => spictrl_data_out, + -- SPI connections + SPI_CS_OUT => FLASH_CS, + SPI_SDI_IN => FLASH_DOUT, + SPI_SDO_OUT => FLASH_DIN, + SPI_SCK_OUT => FLASH_CLK, + -- BRAM for read/write data + BRAM_A_OUT => spi_bram_addr, + BRAM_WR_D_IN => spi_bram_wr_d, + BRAM_RD_D_OUT => spi_bram_rd_d, + BRAM_WE_OUT => spi_bram_we, + -- Status lines + STAT => open + ); + + -- data memory for SPI accesses + THE_SPI_MEMORY : spi_databus_memory + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_ACK_OUT => spimem_ack, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + -- state machine connections + BRAM_ADDR_IN => spi_bram_addr, + BRAM_WR_D_OUT => spi_bram_wr_d, + BRAM_RD_D_IN => spi_bram_rd_d, + BRAM_WE_IN => spi_bram_we, + -- Status lines + STAT => open + ); + +------------------------------------------------------------------------------- +-- DAC +------------------------------------------------------------------------------- + DAC_SPI : spi_ltc2600 + generic map ( + BITS => 14, + WAITCYCLES => 15) + port map ( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_READ_IN => spidac_read_en, + BUS_WRITE_IN => spidac_write_en, + BUS_BUSY_OUT => spidac_busy, + BUS_ACK_OUT => spidac_ack, + BUS_ADDR_IN => spidac_addr, + BUS_DATA_IN => spidac_data_in, + BUS_DATA_OUT => spidac_data_out, + -- SPI connections + SPI_CS_OUT(0) => DAC_OUT_CS, + SPI_SDI_IN => DAC_IN_SDI, + SPI_SDO_OUT => DAC_OUT_SDO, + SPI_SCK_OUT => DAC_OUT_SCK, + SPI_CLR_OUT(0) => DAC_OUT_CLR + ); + +--------------------------------------------------------------------------- +-- Reboot FPGA +--------------------------------------------------------------------------- + THE_FPGA_REBOOT : fpga_reboot + port map( + CLK => clk_100_i, + RESET => reset_i, + DO_REBOOT => common_ctrl_reg(15), + PROGRAMN => PROGRAMN + ); + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_GREEN <= not med_stat_op(9); + LED_ORANGE <= not med_stat_op(10); + LED_RED <= not INP(0); + LED_YELLOW <= not med_stat_op(11); + +--------------------------------------------------------------------------- +-- Test Connector - Logic Analyser +--------------------------------------------------------------------------- + + TEST_LINE <= logic_analyser_i; + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + + THE_TDC : TDC + generic map ( + CHANNEL_NUMBER => 5, -- Number of TDC channels + CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr + TDC_VERSION => x"160", -- TDC version number + DEBUG => c_YES, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement + CLK_READOUT => clk_100_i, -- Clock for the readout + REFERENCE_TIME => timing_trg_received_i, -- Reference time input + HIT_IN => hit_in_i(4 downto 1), -- Channel start signals + HIT_CALIBRATION => clk_20_i, -- Hits for calibrating the TDC + TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width + TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width + -- + -- Trigger signals from handler + TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet + VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet + VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet + INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet + TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet + SPIKE_DETECTED_IN => trg_spike_detected_i, + MULTI_TMG_TRG_IN => trg_multiple_trg_i, + SPURIOUS_TRG_IN => trg_spurious_trg_i, + -- + TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package + TRG_CODE_IN => trg_code_i, -- + TRG_INFORMATION_IN => trg_information_i, -- + TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package + -- + --Response to handler + TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal + TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc + DATA_OUT => fee_data_i, -- tdc data + DATA_WRITE_OUT => fee_data_write_i, -- data valid signal + DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal + -- + --Hit Counter Bus + HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe + HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe + HCB_ADDR_IN => hitreg_addr, -- bus address + HCB_DATA_OUT => hitreg_data_out, -- bus data + HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe + HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr + --Status Registers Bus + SRB_READ_EN_IN => srb_read_en, -- bus read en strobe + SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe + SRB_ADDR_IN => srb_addr, -- bus address + SRB_DATA_OUT => srb_data_out, -- bus data + SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe + SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr + --Encoder Start Registers Bus + ESB_READ_EN_IN => esb_read_en, -- bus read en strobe + ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe + ESB_ADDR_IN => esb_addr, -- bus address + ESB_DATA_OUT => esb_data_out, -- bus data + ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe + ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr + --Fifo Write Registers Bus + EFB_READ_EN_IN => efb_read_en, -- bus read en strobe + EFB_WRITE_EN_IN => efb_write_en, -- bus write en strobe + EFB_ADDR_IN => efb_addr, -- bus address + EFB_DATA_OUT => efb_data_out, -- bus data + EFB_DATAREADY_OUT => efb_data_ready, -- bus data ready strobe + EFB_UNKNOWN_ADDR_OUT => efb_invalid, -- bus invalid addr + --Lost Hit Registers Bus + LHB_READ_EN_IN => lhb_read_en, -- bus read en strobe + LHB_WRITE_EN_IN => lhb_write_en, -- bus write en strobe + LHB_ADDR_IN => lhb_addr, -- bus address + LHB_DATA_OUT => lhb_data_out, -- bus data + LHB_DATAREADY_OUT => lhb_data_ready, -- bus data ready strobe + LHB_UNKNOWN_ADDR_OUT => lhb_invalid, -- bus invalid addr + -- + LOGIC_ANALYSER_OUT => logic_analyser_i, + CONTROL_REG_IN => tdc_ctrl_reg); + + -- For single edge measurements + --hit_in_i <= INP; + --hit_in_i <= (others => timing_trg_received_i); + + -- For ToT Measurements + Gen_Hit_In_Signals : for i in 1 to 32 generate + hit_in_i(i*2-1) <= INP(i-1); + hit_in_i(i*2) <= not INP(i-1); + end generate Gen_Hit_In_Signals; + + -- Trigger on a TDC Channel + FPGA5_COMM(10) <= hit_in_i(to_integer(unsigned(tdc_ctrl_reg(5*32+7 downto 5*32)))); + +-- !!!!! IMPORTANT !!!!! Don't forget to set the REGIO_HARDWARE_VERSION !!!!! +end architecture; diff --git a/base/cores/FIFO_36x128_OutReg.vhd b/base/cores/FIFO_36x128_OutReg.vhd new file mode 100644 index 0000000..3716909 --- /dev/null +++ b/base/cores/FIFO_36x128_OutReg.vhd @@ -0,0 +1,644 @@ +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 4.8 +--/opt/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -regout -no_enable -pe 3 -pf -1 -e + +-- Tue Oct 15 10:43:36 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity FIFO_36x128_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic); +end FIFO_36x128_OutReg; + +architecture Structure of FIFO_36x128_OutReg is + + -- internal signal declarations + signal invout_2 : std_logic; + signal invout_1 : std_logic; + signal rden_i_inv : std_logic; + signal invout_0 : std_logic; + signal cnt_con_inv : std_logic; + signal fcnt_en_inv_inv : std_logic; + signal fcnt_en : std_logic; + signal empty_i : std_logic; + signal empty_d : std_logic; + signal full_i : std_logic; + signal full_d : std_logic; + signal ifcount_0 : std_logic; + signal ifcount_1 : std_logic; + signal bdcnt_bctr_ci : std_logic; + signal ifcount_2 : std_logic; + signal ifcount_3 : std_logic; + signal co0 : std_logic; + signal ifcount_4 : std_logic; + signal ifcount_5 : std_logic; + signal co1 : std_logic; + signal ifcount_6 : std_logic; + signal ifcount_7 : std_logic; + signal co3 : std_logic; + signal cnt_con : std_logic; + signal co2 : std_logic; + signal cmp_ci : std_logic; + signal rden_i : std_logic; + signal co0_1 : std_logic; + signal co1_1 : std_logic; + signal co2_1 : std_logic; + signal cmp_le_1 : std_logic; + signal cmp_le_1_c : std_logic; + signal cmp_ci_1 : std_logic; + signal co0_2 : std_logic; + signal co1_2 : std_logic; + signal co2_2 : std_logic; + signal wren_i : std_logic; + signal wren_i_inv : std_logic; + signal cmp_ge_d1 : std_logic; + signal cmp_ge_d1_c : std_logic; + signal iwcount_0 : std_logic; + signal iwcount_1 : std_logic; + signal wcount_0 : std_logic; + signal wcount_1 : std_logic; + signal w_ctr_ci : std_logic; + signal iwcount_2 : std_logic; + signal iwcount_3 : std_logic; + signal wcount_2 : std_logic; + signal wcount_3 : std_logic; + signal co0_3 : std_logic; + signal iwcount_4 : std_logic; + signal iwcount_5 : std_logic; + signal wcount_4 : std_logic; + signal wcount_5 : std_logic; + signal co1_3 : std_logic; + signal iwcount_6 : std_logic; + signal iwcount_7 : std_logic; + signal co3_1 : std_logic; + signal wcount_6 : std_logic; + signal wcount_7 : std_logic; + signal co2_3 : std_logic; + signal ircount_0 : std_logic; + signal ircount_1 : std_logic; + signal rcount_0 : std_logic; + signal rcount_1 : std_logic; + signal r_ctr_ci : std_logic; + signal ircount_2 : std_logic; + signal ircount_3 : std_logic; + signal rcount_2 : std_logic; + signal rcount_3 : std_logic; + signal co0_4 : std_logic; + signal ircount_4 : std_logic; + signal ircount_5 : std_logic; + signal rcount_4 : std_logic; + signal rcount_5 : std_logic; + signal co1_4 : std_logic; + signal ircount_6 : std_logic; + signal ircount_7 : std_logic; + signal co3_2 : std_logic; + signal rcount_6 : std_logic; + signal rcount_7 : std_logic; + signal co2_4 : std_logic; + signal scuba_vhi : std_logic; + signal cmp_ci_2 : std_logic; + signal fcnt_en_inv : std_logic; + signal r_nw_inv : std_logic; + signal fcount_0 : std_logic; + signal fcount_1 : std_logic; + signal co0_5 : std_logic; + signal r_nw : std_logic; + signal fcount_2 : std_logic; + signal fcount_3 : std_logic; + signal co1_5 : std_logic; + signal fcount_4 : std_logic; + signal fcount_5 : std_logic; + signal co2_5 : std_logic; + signal fcount_6 : std_logic; + signal fcount_7 : std_logic; + signal ae_d : std_logic; + signal ae_d_c : std_logic; + signal scuba_vlo : std_logic; + + -- local component declarations + component AGEB2 + port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; + B1 : in std_logic; CI : in std_logic; GE : out std_logic); + end component; + component ALEB2 + port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; + B1 : in std_logic; CI : in std_logic; LE : out std_logic); + end component; + component AND2 + port (A : in std_logic; B : in std_logic; Z : out std_logic); + end component; + component CU2 + port (CI : in std_logic; PC0 : in std_logic; PC1 : in std_logic; + CO : out std_logic; NC0 : out std_logic; NC1 : out std_logic); + end component; + component CB2 + port (CI : in std_logic; PC0 : in std_logic; PC1 : in std_logic; + CON : in std_logic; CO : out std_logic; NC0 : out std_logic; + NC1 : out std_logic); + end component; + component FADD2B + port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; + B1 : in std_logic; CI : in std_logic; COUT : out std_logic; + S0 : out std_logic; S1 : out std_logic); + end component; + component FD1P3DX + port (D : in std_logic; SP : in std_logic; CK : in std_logic; + CD : in std_logic; Q : out std_logic); + end component; + component FD1S3BX + port (D : in std_logic; CK : in std_logic; PD : in std_logic; + Q : out std_logic); + end component; + component FD1S3DX + port (D : in std_logic; CK : in std_logic; CD : in std_logic; + Q : out std_logic); + end component; + component INV + port (A : in std_logic; Z : out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3 : in std_logic; AD2 : in std_logic; AD1 : in std_logic; + AD0 : in std_logic; DO0 : out std_logic); + end component; + component VHI + port (Z : out std_logic); + end component; + component VLO + port (Z : out std_logic); + end component; + component XOR2 + port (A : in std_logic; B : in std_logic; Z : out std_logic); + end component; + component PDPW16KC + generic (GSR : in string; CSDECODE_R : in string; + CSDECODE_W : in string; REGMODE : in string; + DATA_WIDTH_R : in integer; DATA_WIDTH_W : in integer); + port (DI0 : in std_logic; DI1 : in std_logic; DI2 : in std_logic; + DI3 : in std_logic; DI4 : in std_logic; DI5 : in std_logic; + DI6 : in std_logic; DI7 : in std_logic; DI8 : in std_logic; + DI9 : in std_logic; DI10 : in std_logic; DI11 : in std_logic; + DI12 : in std_logic; DI13 : in std_logic; + DI14 : in std_logic; DI15 : in std_logic; + DI16 : in std_logic; DI17 : in std_logic; + DI18 : in std_logic; DI19 : in std_logic; + DI20 : in std_logic; DI21 : in std_logic; + DI22 : in std_logic; DI23 : in std_logic; + DI24 : in std_logic; DI25 : in std_logic; + DI26 : in std_logic; DI27 : in std_logic; + DI28 : in std_logic; DI29 : in std_logic; + DI30 : in std_logic; DI31 : in std_logic; + DI32 : in std_logic; DI33 : in std_logic; + DI34 : in std_logic; DI35 : in std_logic; + ADW0 : in std_logic; ADW1 : in std_logic; + ADW2 : in std_logic; ADW3 : in std_logic; + ADW4 : in std_logic; ADW5 : in std_logic; + ADW6 : in std_logic; ADW7 : in std_logic; + ADW8 : in std_logic; BE0 : in std_logic; BE1 : in std_logic; + BE2 : in std_logic; BE3 : in std_logic; CEW : in std_logic; + CLKW : in std_logic; CSW0 : in std_logic; + CSW1 : in std_logic; CSW2 : in std_logic; + ADR0 : in std_logic; ADR1 : in std_logic; + ADR2 : in std_logic; ADR3 : in std_logic; + ADR4 : in std_logic; ADR5 : in std_logic; + ADR6 : in std_logic; ADR7 : in std_logic; + ADR8 : in std_logic; ADR9 : in std_logic; + ADR10 : in std_logic; ADR11 : in std_logic; + ADR12 : in std_logic; ADR13 : in std_logic; + CER : in std_logic; CLKR : in std_logic; CSR0 : in std_logic; + CSR1 : in std_logic; CSR2 : in std_logic; RST : in std_logic; + DO0 : out std_logic; DO1 : out std_logic; + DO2 : out std_logic; DO3 : out std_logic; + DO4 : out std_logic; DO5 : out std_logic; + DO6 : out std_logic; DO7 : out std_logic; + DO8 : out std_logic; DO9 : out std_logic; + DO10 : out std_logic; DO11 : out std_logic; + DO12 : out std_logic; DO13 : out std_logic; + DO14 : out std_logic; DO15 : out std_logic; + DO16 : out std_logic; DO17 : out std_logic; + DO18 : out std_logic; DO19 : out std_logic; + DO20 : out std_logic; DO21 : out std_logic; + DO22 : out std_logic; DO23 : out std_logic; + DO24 : out std_logic; DO25 : out std_logic; + DO26 : out std_logic; DO27 : out std_logic; + DO28 : out std_logic; DO29 : out std_logic; + DO30 : out std_logic; DO31 : out std_logic; + DO32 : out std_logic; DO33 : out std_logic; + DO34 : out std_logic; DO35 : out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_36x128_OutReg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t4 : AND2 + port map (A => WrEn, B => invout_2, Z => wren_i); + + INV_8 : INV + port map (A => full_i, Z => invout_2); + + AND2_t3 : AND2 + port map (A => RdEn, B => invout_1, Z => rden_i); + + INV_7 : INV + port map (A => empty_i, Z => invout_1); + + AND2_t2 : AND2 + port map (A => wren_i, B => rden_i_inv, Z => cnt_con); + + XOR2_t1 : XOR2 + port map (A => wren_i, B => rden_i, Z => fcnt_en); + + INV_6 : INV + port map (A => rden_i, Z => rden_i_inv); + + INV_5 : INV + port map (A => wren_i, Z => wren_i_inv); + + LUT4_1 : ROM16X1A + generic map (initval => X"3232") + port map (AD3 => scuba_vlo, AD2 => cmp_le_1, AD1 => wren_i, + AD0 => empty_i, DO0 => empty_d); + + LUT4_0 : ROM16X1A + generic map (initval => X"3232") + port map (AD3 => scuba_vlo, AD2 => cmp_ge_d1, AD1 => rden_i, + AD0 => full_i, DO0 => full_d); + + AND2_t0 : AND2 + port map (A => rden_i, B => invout_0, Z => r_nw); + + INV_4 : INV + port map (A => wren_i, Z => invout_0); + + INV_3 : INV + port map (A => fcnt_en, Z => fcnt_en_inv); + + INV_2 : INV + port map (A => cnt_con, Z => cnt_con_inv); + + INV_1 : INV + port map (A => r_nw, Z => r_nw_inv); + + INV_0 : INV + port map (A => fcnt_en_inv, Z => fcnt_en_inv_inv); + + pdp_ram_0_0_0 : PDPW16KC + generic map (CSDECODE_R => "0b001", CSDECODE_W => "0b001", GSR => "DISABLED", + REGMODE => "OUTREG", DATA_WIDTH_R => 36, DATA_WIDTH_W => 36) + port map (DI0 => Data(0), DI1 => Data(1), DI2 => Data(2), DI3 => Data(3), + DI4 => Data(4), DI5 => Data(5), DI6 => Data(6), DI7 => Data(7), + DI8 => Data(8), DI9 => Data(9), DI10 => Data(10), DI11 => Data(11), + DI12 => Data(12), DI13 => Data(13), DI14 => Data(14), + DI15 => Data(15), DI16 => Data(16), DI17 => Data(17), + DI18 => Data(18), DI19 => Data(19), DI20 => Data(20), + DI21 => Data(21), DI22 => Data(22), DI23 => Data(23), + DI24 => Data(24), DI25 => Data(25), DI26 => Data(26), + DI27 => Data(27), DI28 => Data(28), DI29 => Data(29), + DI30 => Data(30), DI31 => Data(31), DI32 => Data(32), + DI33 => Data(33), DI34 => Data(34), DI35 => Data(35), + ADW0 => wcount_0, ADW1 => wcount_1, ADW2 => wcount_2, + ADW3 => wcount_3, ADW4 => wcount_4, ADW5 => wcount_5, + ADW6 => wcount_6, ADW7 => scuba_vlo, ADW8 => scuba_vlo, + BE0 => scuba_vhi, BE1 => scuba_vhi, BE2 => scuba_vhi, + BE3 => scuba_vhi, CEW => wren_i, CLKW => Clock, CSW0 => scuba_vhi, + CSW1 => scuba_vlo, CSW2 => scuba_vlo, ADR0 => scuba_vlo, + ADR1 => scuba_vlo, ADR2 => scuba_vlo, ADR3 => scuba_vlo, + ADR4 => scuba_vlo, ADR5 => rcount_0, ADR6 => rcount_1, + ADR7 => rcount_2, ADR8 => rcount_3, ADR9 => rcount_4, + ADR10 => rcount_5, ADR11 => rcount_6, ADR12 => scuba_vlo, + ADR13 => scuba_vlo, CER => scuba_vhi, CLKR => Clock, CSR0 => rden_i, + CSR1 => scuba_vlo, CSR2 => scuba_vlo, RST => Reset, DO0 => Q(18), + DO1 => Q(19), DO2 => Q(20), DO3 => Q(21), DO4 => Q(22), DO5 => Q(23), + DO6 => Q(24), DO7 => Q(25), DO8 => Q(26), DO9 => Q(27), DO10 => Q(28), + DO11 => Q(29), DO12 => Q(30), DO13 => Q(31), DO14 => Q(32), + DO15 => Q(33), DO16 => Q(34), DO17 => Q(35), DO18 => Q(0), + DO19 => Q(1), DO20 => Q(2), DO21 => Q(3), DO22 => Q(4), DO23 => Q(5), + DO24 => Q(6), DO25 => Q(7), DO26 => Q(8), DO27 => Q(9), DO28 => Q(10), + DO29 => Q(11), DO30 => Q(12), DO31 => Q(13), DO32 => Q(14), + DO33 => Q(15), DO34 => Q(16), DO35 => Q(17)); + + FF_26 : FD1P3DX + port map (D => ifcount_0, SP => fcnt_en, CK => Clock, CD => Reset, + Q => fcount_0); + + FF_25 : FD1P3DX + port map (D => ifcount_1, SP => fcnt_en, CK => Clock, CD => Reset, + Q => fcount_1); + + FF_24 : FD1P3DX + port map (D => ifcount_2, SP => fcnt_en, CK => Clock, CD => Reset, + Q => fcount_2); + + FF_23 : FD1P3DX + port map (D => ifcount_3, SP => fcnt_en, CK => Clock, CD => Reset, + Q => fcount_3); + + FF_22 : FD1P3DX + port map (D => ifcount_4, SP => fcnt_en, CK => Clock, CD => Reset, + Q => fcount_4); + + FF_21 : FD1P3DX + port map (D => ifcount_5, SP => fcnt_en, CK => Clock, CD => Reset, + Q => fcount_5); + + FF_20 : FD1P3DX + port map (D => ifcount_6, SP => fcnt_en, CK => Clock, CD => Reset, + Q => fcount_6); + + FF_19 : FD1P3DX + port map (D => ifcount_7, SP => fcnt_en, CK => Clock, CD => Reset, + Q => fcount_7); + + FF_18 : FD1S3BX + port map (D => empty_d, CK => Clock, PD => Reset, Q => empty_i); + + FF_17 : FD1S3DX + port map (D => full_d, CK => Clock, CD => Reset, Q => full_i); + + FF_16 : FD1P3DX + port map (D => iwcount_0, SP => wren_i, CK => Clock, CD => Reset, + Q => wcount_0); + + FF_15 : FD1P3DX + port map (D => iwcount_1, SP => wren_i, CK => Clock, CD => Reset, + Q => wcount_1); + + FF_14 : FD1P3DX + port map (D => iwcount_2, SP => wren_i, CK => Clock, CD => Reset, + Q => wcount_2); + + FF_13 : FD1P3DX + port map (D => iwcount_3, SP => wren_i, CK => Clock, CD => Reset, + Q => wcount_3); + + FF_12 : FD1P3DX + port map (D => iwcount_4, SP => wren_i, CK => Clock, CD => Reset, + Q => wcount_4); + + FF_11 : FD1P3DX + port map (D => iwcount_5, SP => wren_i, CK => Clock, CD => Reset, + Q => wcount_5); + + FF_10 : FD1P3DX + port map (D => iwcount_6, SP => wren_i, CK => Clock, CD => Reset, + Q => wcount_6); + + FF_9 : FD1P3DX + port map (D => iwcount_7, SP => wren_i, CK => Clock, CD => Reset, + Q => wcount_7); + + FF_8 : FD1P3DX + port map (D => ircount_0, SP => rden_i, CK => Clock, CD => Reset, + Q => rcount_0); + + FF_7 : FD1P3DX + port map (D => ircount_1, SP => rden_i, CK => Clock, CD => Reset, + Q => rcount_1); + + FF_6 : FD1P3DX + port map (D => ircount_2, SP => rden_i, CK => Clock, CD => Reset, + Q => rcount_2); + + FF_5 : FD1P3DX + port map (D => ircount_3, SP => rden_i, CK => Clock, CD => Reset, + Q => rcount_3); + + FF_4 : FD1P3DX + port map (D => ircount_4, SP => rden_i, CK => Clock, CD => Reset, + Q => rcount_4); + + FF_3 : FD1P3DX + port map (D => ircount_5, SP => rden_i, CK => Clock, CD => Reset, + Q => rcount_5); + + FF_2 : FD1P3DX + port map (D => ircount_6, SP => rden_i, CK => Clock, CD => Reset, + Q => rcount_6); + + FF_1 : FD1P3DX + port map (D => ircount_7, SP => rden_i, CK => Clock, CD => Reset, + Q => rcount_7); + + FF_0 : FD1S3BX + port map (D => ae_d, CK => Clock, PD => Reset, Q => AlmostEmpty); + + bdcnt_bctr_cia : FADD2B + port map (A0 => scuba_vlo, A1 => cnt_con, B0 => scuba_vlo, B1 => cnt_con, + CI => scuba_vlo, COUT => bdcnt_bctr_ci, S0 => open, S1 => open); + + bdcnt_bctr_0 : CB2 + port map (CI => bdcnt_bctr_ci, PC0 => fcount_0, PC1 => fcount_1, + CON => cnt_con, CO => co0, NC0 => ifcount_0, NC1 => ifcount_1); + + bdcnt_bctr_1 : CB2 + port map (CI => co0, PC0 => fcount_2, PC1 => fcount_3, CON => cnt_con, + CO => co1, NC0 => ifcount_2, NC1 => ifcount_3); + + bdcnt_bctr_2 : CB2 + port map (CI => co1, PC0 => fcount_4, PC1 => fcount_5, CON => cnt_con, + CO => co2, NC0 => ifcount_4, NC1 => ifcount_5); + + bdcnt_bctr_3 : CB2 + port map (CI => co2, PC0 => fcount_6, PC1 => fcount_7, CON => cnt_con, + CO => co3, NC0 => ifcount_6, NC1 => ifcount_7); + + e_cmp_ci_a : FADD2B + port map (A0 => scuba_vhi, A1 => scuba_vhi, B0 => scuba_vhi, + B1 => scuba_vhi, CI => scuba_vlo, COUT => cmp_ci, S0 => open, + S1 => open); + + e_cmp_0 : ALEB2 + port map (A0 => fcount_0, A1 => fcount_1, B0 => rden_i, B1 => scuba_vlo, + CI => cmp_ci, LE => co0_1); + + e_cmp_1 : ALEB2 + port map (A0 => fcount_2, A1 => fcount_3, B0 => scuba_vlo, + B1 => scuba_vlo, CI => co0_1, LE => co1_1); + + e_cmp_2 : ALEB2 + port map (A0 => fcount_4, A1 => fcount_5, B0 => scuba_vlo, + B1 => scuba_vlo, CI => co1_1, LE => co2_1); + + e_cmp_3 : ALEB2 + port map (A0 => fcount_6, A1 => fcount_7, B0 => scuba_vlo, + B1 => scuba_vlo, CI => co2_1, LE => cmp_le_1_c); + + a0 : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo, + B1 => scuba_vlo, CI => cmp_le_1_c, COUT => open, S0 => cmp_le_1, + S1 => open); + + g_cmp_ci_a : FADD2B + port map (A0 => scuba_vhi, A1 => scuba_vhi, B0 => scuba_vhi, + B1 => scuba_vhi, CI => scuba_vlo, COUT => cmp_ci_1, S0 => open, + S1 => open); + + g_cmp_0 : AGEB2 + port map (A0 => fcount_0, A1 => fcount_1, B0 => wren_i, B1 => wren_i, + CI => cmp_ci_1, GE => co0_2); + + g_cmp_1 : AGEB2 + port map (A0 => fcount_2, A1 => fcount_3, B0 => wren_i, B1 => wren_i, + CI => co0_2, GE => co1_2); + + g_cmp_2 : AGEB2 + port map (A0 => fcount_4, A1 => fcount_5, B0 => wren_i, B1 => wren_i, + CI => co1_2, GE => co2_2); + + g_cmp_3 : AGEB2 + port map (A0 => fcount_6, A1 => fcount_7, B0 => wren_i, B1 => wren_i_inv, + CI => co2_2, GE => cmp_ge_d1_c); + + a1 : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo, + B1 => scuba_vlo, CI => cmp_ge_d1_c, COUT => open, S0 => cmp_ge_d1, + S1 => open); + + w_ctr_cia : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo, + B1 => scuba_vhi, CI => scuba_vlo, COUT => w_ctr_ci, S0 => open, + S1 => open); + + w_ctr_0 : CU2 + port map (CI => w_ctr_ci, PC0 => wcount_0, PC1 => wcount_1, CO => co0_3, + NC0 => iwcount_0, NC1 => iwcount_1); + + w_ctr_1 : CU2 + port map (CI => co0_3, PC0 => wcount_2, PC1 => wcount_3, CO => co1_3, + NC0 => iwcount_2, NC1 => iwcount_3); + + w_ctr_2 : CU2 + port map (CI => co1_3, PC0 => wcount_4, PC1 => wcount_5, CO => co2_3, + NC0 => iwcount_4, NC1 => iwcount_5); + + w_ctr_3 : CU2 + port map (CI => co2_3, PC0 => wcount_6, PC1 => wcount_7, CO => co3_1, + NC0 => iwcount_6, NC1 => iwcount_7); + + r_ctr_cia : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo, + B1 => scuba_vhi, CI => scuba_vlo, COUT => r_ctr_ci, S0 => open, + S1 => open); + + r_ctr_0 : CU2 + port map (CI => r_ctr_ci, PC0 => rcount_0, PC1 => rcount_1, CO => co0_4, + NC0 => ircount_0, NC1 => ircount_1); + + r_ctr_1 : CU2 + port map (CI => co0_4, PC0 => rcount_2, PC1 => rcount_3, CO => co1_4, + NC0 => ircount_2, NC1 => ircount_3); + + r_ctr_2 : CU2 + port map (CI => co1_4, PC0 => rcount_4, PC1 => rcount_5, CO => co2_4, + NC0 => ircount_4, NC1 => ircount_5); + + r_ctr_3 : CU2 + port map (CI => co2_4, PC0 => rcount_6, PC1 => rcount_7, CO => co3_2, + NC0 => ircount_6, NC1 => ircount_7); + + scuba_vhi_inst : VHI + port map (Z => scuba_vhi); + + ae_cmp_ci_a : FADD2B + port map (A0 => scuba_vhi, A1 => scuba_vhi, B0 => scuba_vhi, + B1 => scuba_vhi, CI => scuba_vlo, COUT => cmp_ci_2, S0 => open, + S1 => open); + + ae_cmp_0 : ALEB2 + port map (A0 => fcount_0, A1 => fcount_1, B0 => fcnt_en_inv, + B1 => r_nw_inv, CI => cmp_ci_2, LE => co0_5); + + ae_cmp_1 : ALEB2 + port map (A0 => fcount_2, A1 => fcount_3, B0 => r_nw, B1 => scuba_vlo, + CI => co0_5, LE => co1_5); + + ae_cmp_2 : ALEB2 + port map (A0 => fcount_4, A1 => fcount_5, B0 => scuba_vlo, + B1 => scuba_vlo, CI => co1_5, LE => co2_5); + + ae_cmp_3 : ALEB2 + port map (A0 => fcount_6, A1 => fcount_7, B0 => scuba_vlo, + B1 => scuba_vlo, CI => co2_5, LE => ae_d_c); + + scuba_vlo_inst : VLO + port map (Z => scuba_vlo); + + a2 : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo, + B1 => scuba_vlo, CI => ae_d_c, COUT => open, S0 => ae_d, S1 => open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of FIFO_36x128_OutReg is + for Structure + for all : AGEB2 use entity ecp3.AGEB2(V); end for; + for all : ALEB2 use entity ecp3.ALEB2(V); end for; + for all : AND2 use entity ecp3.AND2(V); end for; + for all : CU2 use entity ecp3.CU2(V); end for; + for all : CB2 use entity ecp3.CB2(V); end for; + for all : FADD2B use entity ecp3.FADD2B(V); end for; + for all : FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all : FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all : FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all : INV use entity ecp3.INV(V); end for; + for all : ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all : VHI use entity ecp3.VHI(V); end for; + for all : VLO use entity ecp3.VLO(V); end for; + for all : XOR2 use entity ecp3.XOR2(V); end for; + for all : PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/cores/FIFO_DC_36x128_OutReg.vhd b/base/cores/FIFO_DC_36x128_OutReg.vhd new file mode 100644 index 0000000..42360b0 --- /dev/null +++ b/base/cores/FIFO_DC_36x128_OutReg.vhd @@ -0,0 +1,1147 @@ +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 5.4 +--/opt/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -rdata_width 36 -regout -no_enable -pe -1 -pf 125 -e + +-- Fri Oct 25 11:43:54 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity FIFO_DC_36x128_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic); +end FIFO_DC_36x128_OutReg; + +architecture Structure of FIFO_DC_36x128_OutReg is + + -- internal signal declarations + signal invout_1 : std_logic; + signal invout_0 : std_logic; + signal w_g2b_xor_cluster_1 : std_logic; + signal r_g2b_xor_cluster_1 : std_logic; + signal w_gdata_0 : std_logic; + signal w_gdata_1 : std_logic; + signal w_gdata_2 : std_logic; + signal w_gdata_3 : std_logic; + signal w_gdata_4 : std_logic; + signal w_gdata_5 : std_logic; + signal w_gdata_6 : std_logic; + signal wptr_0 : std_logic; + signal wptr_1 : std_logic; + signal wptr_2 : std_logic; + signal wptr_3 : std_logic; + signal wptr_4 : std_logic; + signal wptr_5 : std_logic; + signal wptr_6 : std_logic; + signal wptr_7 : std_logic; + signal r_gdata_0 : std_logic; + signal r_gdata_1 : std_logic; + signal r_gdata_2 : std_logic; + signal r_gdata_3 : std_logic; + signal r_gdata_4 : std_logic; + signal r_gdata_5 : std_logic; + signal r_gdata_6 : std_logic; + signal rptr_0 : std_logic; + signal rptr_1 : std_logic; + signal rptr_2 : std_logic; + signal rptr_3 : std_logic; + signal rptr_4 : std_logic; + signal rptr_5 : std_logic; + signal rptr_6 : std_logic; + signal rptr_7 : std_logic; + signal w_gcount_0 : std_logic; + signal w_gcount_1 : std_logic; + signal w_gcount_2 : std_logic; + signal w_gcount_3 : std_logic; + signal w_gcount_4 : std_logic; + signal w_gcount_5 : std_logic; + signal w_gcount_6 : std_logic; + signal w_gcount_7 : std_logic; + signal r_gcount_0 : std_logic; + signal r_gcount_1 : std_logic; + signal r_gcount_2 : std_logic; + signal r_gcount_3 : std_logic; + signal r_gcount_4 : std_logic; + signal r_gcount_5 : std_logic; + signal r_gcount_6 : std_logic; + signal r_gcount_7 : std_logic; + signal w_gcount_r20 : std_logic; + signal w_gcount_r0 : std_logic; + signal w_gcount_r21 : std_logic; + signal w_gcount_r1 : std_logic; + signal w_gcount_r22 : std_logic; + signal w_gcount_r2 : std_logic; + signal w_gcount_r23 : std_logic; + signal w_gcount_r3 : std_logic; + signal w_gcount_r24 : std_logic; + signal w_gcount_r4 : std_logic; + signal w_gcount_r25 : std_logic; + signal w_gcount_r5 : std_logic; + signal w_gcount_r26 : std_logic; + signal w_gcount_r6 : std_logic; + signal w_gcount_r27 : std_logic; + signal w_gcount_r7 : std_logic; + signal r_gcount_w20 : std_logic; + signal r_gcount_w0 : std_logic; + signal r_gcount_w21 : std_logic; + signal r_gcount_w1 : std_logic; + signal r_gcount_w22 : std_logic; + signal r_gcount_w2 : std_logic; + signal r_gcount_w23 : std_logic; + signal r_gcount_w3 : std_logic; + signal r_gcount_w24 : std_logic; + signal r_gcount_w4 : std_logic; + signal r_gcount_w25 : std_logic; + signal r_gcount_w5 : std_logic; + signal r_gcount_w26 : std_logic; + signal r_gcount_w6 : std_logic; + signal r_gcount_w27 : std_logic; + signal r_gcount_w7 : std_logic; + signal empty_i : std_logic; + signal rRst : std_logic; + signal full_i : std_logic; + signal iwcount_0 : std_logic; + signal iwcount_1 : std_logic; + signal w_gctr_ci : std_logic; + signal iwcount_2 : std_logic; + signal iwcount_3 : std_logic; + signal co0 : std_logic; + signal iwcount_4 : std_logic; + signal iwcount_5 : std_logic; + signal co1 : std_logic; + signal iwcount_6 : std_logic; + signal iwcount_7 : std_logic; + signal co3 : std_logic; + signal wcount_7 : std_logic; + signal co2 : std_logic; + signal ircount_0 : std_logic; + signal ircount_1 : std_logic; + signal r_gctr_ci : std_logic; + signal ircount_2 : std_logic; + signal ircount_3 : std_logic; + signal co0_1 : std_logic; + signal ircount_4 : std_logic; + signal ircount_5 : std_logic; + signal co1_1 : std_logic; + signal ircount_6 : std_logic; + signal ircount_7 : std_logic; + signal co3_1 : std_logic; + signal rcount_7 : std_logic; + signal co2_1 : std_logic; + signal rden_i : std_logic; + signal cmp_ci : std_logic; + signal wcount_r0 : std_logic; + signal wcount_r1 : std_logic; + signal rcount_0 : std_logic; + signal rcount_1 : std_logic; + signal co0_2 : std_logic; + signal wcount_r2 : std_logic; + signal wcount_r3 : std_logic; + signal rcount_2 : std_logic; + signal rcount_3 : std_logic; + signal co1_2 : std_logic; + signal w_g2b_xor_cluster_0 : std_logic; + signal wcount_r5 : std_logic; + signal rcount_4 : std_logic; + signal rcount_5 : std_logic; + signal co2_2 : std_logic; + signal wcount_r6 : std_logic; + signal empty_cmp_clr : std_logic; + signal rcount_6 : std_logic; + signal empty_cmp_set : std_logic; + signal empty_d : std_logic; + signal empty_d_c : std_logic; + signal cmp_ci_1 : std_logic; + signal wcount_0 : std_logic; + signal wcount_1 : std_logic; + signal co0_3 : std_logic; + signal wcount_2 : std_logic; + signal wcount_3 : std_logic; + signal co1_3 : std_logic; + signal wcount_4 : std_logic; + signal wcount_5 : std_logic; + signal co2_3 : std_logic; + signal full_cmp_clr : std_logic; + signal wcount_6 : std_logic; + signal full_cmp_set : std_logic; + signal full_d : std_logic; + signal full_d_c : std_logic; + signal scuba_vhi : std_logic; + signal iaf_setcount_0 : std_logic; + signal iaf_setcount_1 : std_logic; + signal af_set_ctr_ci : std_logic; + signal iaf_setcount_2 : std_logic; + signal iaf_setcount_3 : std_logic; + signal co0_4 : std_logic; + signal iaf_setcount_4 : std_logic; + signal iaf_setcount_5 : std_logic; + signal co1_4 : std_logic; + signal iaf_setcount_6 : std_logic; + signal iaf_setcount_7 : std_logic; + signal co3_2 : std_logic; + signal af_setcount_7 : std_logic; + signal co2_4 : std_logic; + signal wren_i : std_logic; + signal cmp_ci_2 : std_logic; + signal rcount_w0 : std_logic; + signal rcount_w1 : std_logic; + signal af_setcount_0 : std_logic; + signal af_setcount_1 : std_logic; + signal co0_5 : std_logic; + signal rcount_w2 : std_logic; + signal rcount_w3 : std_logic; + signal af_setcount_2 : std_logic; + signal af_setcount_3 : std_logic; + signal co1_5 : std_logic; + signal r_g2b_xor_cluster_0 : std_logic; + signal rcount_w5 : std_logic; + signal af_setcount_4 : std_logic; + signal af_setcount_5 : std_logic; + signal co2_5 : std_logic; + signal rcount_w6 : std_logic; + signal af_set_cmp_clr : std_logic; + signal af_setcount_6 : std_logic; + signal af_set_cmp_set : std_logic; + signal af_set : std_logic; + signal af_set_c : std_logic; + signal scuba_vlo : std_logic; + + -- local component declarations + component AGEB2 + port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; + B1 : in std_logic; CI : in std_logic; GE : out std_logic); + end component; + component AND2 + port (A : in std_logic; B : in std_logic; Z : out std_logic); + end component; + component CU2 + port (CI : in std_logic; PC0 : in std_logic; PC1 : in std_logic; + CO : out std_logic; NC0 : out std_logic; NC1 : out std_logic); + end component; + component FADD2B + port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; + B1 : in std_logic; CI : in std_logic; COUT : out std_logic; + S0 : out std_logic; S1 : out std_logic); + end component; + component FD1P3BX + port (D : in std_logic; SP : in std_logic; CK : in std_logic; + PD : in std_logic; Q : out std_logic); + end component; + component FD1P3DX + port (D : in std_logic; SP : in std_logic; CK : in std_logic; + CD : in std_logic; Q : out std_logic); + end component; + component FD1S3BX + port (D : in std_logic; CK : in std_logic; PD : in std_logic; + Q : out std_logic); + end component; + component FD1S3DX + port (D : in std_logic; CK : in std_logic; CD : in std_logic; + Q : out std_logic); + end component; + component INV + port (A : in std_logic; Z : out std_logic); + end component; + component OR2 + port (A : in std_logic; B : in std_logic; Z : out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3 : in std_logic; AD2 : in std_logic; AD1 : in std_logic; + AD0 : in std_logic; DO0 : out std_logic); + end component; + component VHI + port (Z : out std_logic); + end component; + component VLO + port (Z : out std_logic); + end component; + component XOR2 + port (A : in std_logic; B : in std_logic; Z : out std_logic); + end component; + component PDPW16KC + generic (GSR : in string; CSDECODE_R : in string; + CSDECODE_W : in string; REGMODE : in string; + DATA_WIDTH_R : in integer; DATA_WIDTH_W : in integer); + port (DI0 : in std_logic; DI1 : in std_logic; DI2 : in std_logic; + DI3 : in std_logic; DI4 : in std_logic; DI5 : in std_logic; + DI6 : in std_logic; DI7 : in std_logic; DI8 : in std_logic; + DI9 : in std_logic; DI10 : in std_logic; DI11 : in std_logic; + DI12 : in std_logic; DI13 : in std_logic; + DI14 : in std_logic; DI15 : in std_logic; + DI16 : in std_logic; DI17 : in std_logic; + DI18 : in std_logic; DI19 : in std_logic; + DI20 : in std_logic; DI21 : in std_logic; + DI22 : in std_logic; DI23 : in std_logic; + DI24 : in std_logic; DI25 : in std_logic; + DI26 : in std_logic; DI27 : in std_logic; + DI28 : in std_logic; DI29 : in std_logic; + DI30 : in std_logic; DI31 : in std_logic; + DI32 : in std_logic; DI33 : in std_logic; + DI34 : in std_logic; DI35 : in std_logic; + ADW0 : in std_logic; ADW1 : in std_logic; + ADW2 : in std_logic; ADW3 : in std_logic; + ADW4 : in std_logic; ADW5 : in std_logic; + ADW6 : in std_logic; ADW7 : in std_logic; + ADW8 : in std_logic; BE0 : in std_logic; BE1 : in std_logic; + BE2 : in std_logic; BE3 : in std_logic; CEW : in std_logic; + CLKW : in std_logic; CSW0 : in std_logic; + CSW1 : in std_logic; CSW2 : in std_logic; + ADR0 : in std_logic; ADR1 : in std_logic; + ADR2 : in std_logic; ADR3 : in std_logic; + ADR4 : in std_logic; ADR5 : in std_logic; + ADR6 : in std_logic; ADR7 : in std_logic; + ADR8 : in std_logic; ADR9 : in std_logic; + ADR10 : in std_logic; ADR11 : in std_logic; + ADR12 : in std_logic; ADR13 : in std_logic; + CER : in std_logic; CLKR : in std_logic; CSR0 : in std_logic; + CSR1 : in std_logic; CSR2 : in std_logic; RST : in std_logic; + DO0 : out std_logic; DO1 : out std_logic; + DO2 : out std_logic; DO3 : out std_logic; + DO4 : out std_logic; DO5 : out std_logic; + DO6 : out std_logic; DO7 : out std_logic; + DO8 : out std_logic; DO9 : out std_logic; + DO10 : out std_logic; DO11 : out std_logic; + DO12 : out std_logic; DO13 : out std_logic; + DO14 : out std_logic; DO15 : out std_logic; + DO16 : out std_logic; DO17 : out std_logic; + DO18 : out std_logic; DO19 : out std_logic; + DO20 : out std_logic; DO21 : out std_logic; + DO22 : out std_logic; DO23 : out std_logic; + DO24 : out std_logic; DO25 : out std_logic; + DO26 : out std_logic; DO27 : out std_logic; + DO28 : out std_logic; DO29 : out std_logic; + DO30 : out std_logic; DO31 : out std_logic; + DO32 : out std_logic; DO33 : out std_logic; + DO34 : out std_logic; DO35 : out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_DC_36x128_OutReg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t16 : AND2 + port map (A => WrEn, B => invout_1, Z => wren_i); + + INV_1 : INV + port map (A => full_i, Z => invout_1); + + AND2_t15 : AND2 + port map (A => RdEn, B => invout_0, Z => rden_i); + + INV_0 : INV + port map (A => empty_i, Z => invout_0); + + OR2_t14 : OR2 + port map (A => Reset, B => RPReset, Z => rRst); + + XOR2_t13 : XOR2 + port map (A => wcount_0, B => wcount_1, Z => w_gdata_0); + + XOR2_t12 : XOR2 + port map (A => wcount_1, B => wcount_2, Z => w_gdata_1); + + XOR2_t11 : XOR2 + port map (A => wcount_2, B => wcount_3, Z => w_gdata_2); + + XOR2_t10 : XOR2 + port map (A => wcount_3, B => wcount_4, Z => w_gdata_3); + + XOR2_t9 : XOR2 + port map (A => wcount_4, B => wcount_5, Z => w_gdata_4); + + XOR2_t8 : XOR2 + port map (A => wcount_5, B => wcount_6, Z => w_gdata_5); + + XOR2_t7 : XOR2 + port map (A => wcount_6, B => wcount_7, Z => w_gdata_6); + + XOR2_t6 : XOR2 + port map (A => rcount_0, B => rcount_1, Z => r_gdata_0); + + XOR2_t5 : XOR2 + port map (A => rcount_1, B => rcount_2, Z => r_gdata_1); + + XOR2_t4 : XOR2 + port map (A => rcount_2, B => rcount_3, Z => r_gdata_2); + + XOR2_t3 : XOR2 + port map (A => rcount_3, B => rcount_4, Z => r_gdata_3); + + XOR2_t2 : XOR2 + port map (A => rcount_4, B => rcount_5, Z => r_gdata_4); + + XOR2_t1 : XOR2 + port map (A => rcount_5, B => rcount_6, Z => r_gdata_5); + + XOR2_t0 : XOR2 + port map (A => rcount_6, B => rcount_7, Z => r_gdata_6); + + LUT4_21 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r24, AD2 => w_gcount_r25, + AD1 => w_gcount_r26, AD0 => w_gcount_r27, + DO0 => w_g2b_xor_cluster_0); + + LUT4_20 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r20, AD2 => w_gcount_r21, + AD1 => w_gcount_r22, AD0 => w_gcount_r23, + DO0 => w_g2b_xor_cluster_1); + + LUT4_19 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r26, AD2 => w_gcount_r27, AD1 => scuba_vlo, + AD0 => scuba_vlo, DO0 => wcount_r6); + + LUT4_18 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r25, AD2 => w_gcount_r26, + AD1 => w_gcount_r27, AD0 => scuba_vlo, DO0 => wcount_r5); + + LUT4_17 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r23, AD2 => w_gcount_r24, + AD1 => w_gcount_r25, AD0 => wcount_r6, DO0 => wcount_r3); + + LUT4_16 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r22, AD2 => w_gcount_r23, + AD1 => w_gcount_r24, AD0 => wcount_r5, DO0 => wcount_r2); + + LUT4_15 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r21, AD2 => w_gcount_r22, + AD1 => w_gcount_r23, AD0 => w_g2b_xor_cluster_0, DO0 => wcount_r1); + + LUT4_14 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_g2b_xor_cluster_0, AD2 => w_g2b_xor_cluster_1, + AD1 => scuba_vlo, AD0 => scuba_vlo, DO0 => wcount_r0); + + LUT4_13 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w24, AD2 => r_gcount_w25, + AD1 => r_gcount_w26, AD0 => r_gcount_w27, + DO0 => r_g2b_xor_cluster_0); + + LUT4_12 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w20, AD2 => r_gcount_w21, + AD1 => r_gcount_w22, AD0 => r_gcount_w23, + DO0 => r_g2b_xor_cluster_1); + + LUT4_11 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w26, AD2 => r_gcount_w27, AD1 => scuba_vlo, + AD0 => scuba_vlo, DO0 => rcount_w6); + + LUT4_10 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w25, AD2 => r_gcount_w26, + AD1 => r_gcount_w27, AD0 => scuba_vlo, DO0 => rcount_w5); + + LUT4_9 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w23, AD2 => r_gcount_w24, + AD1 => r_gcount_w25, AD0 => rcount_w6, DO0 => rcount_w3); + + LUT4_8 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w22, AD2 => r_gcount_w23, + AD1 => r_gcount_w24, AD0 => rcount_w5, DO0 => rcount_w2); + + LUT4_7 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w21, AD2 => r_gcount_w22, + AD1 => r_gcount_w23, AD0 => r_g2b_xor_cluster_0, DO0 => rcount_w1); + + LUT4_6 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_g2b_xor_cluster_0, AD2 => r_g2b_xor_cluster_1, + AD1 => scuba_vlo, AD0 => scuba_vlo, DO0 => rcount_w0); + + LUT4_5 : ROM16X1A + generic map (initval => X"0410") + port map (AD3 => rptr_7, AD2 => rcount_7, AD1 => w_gcount_r27, + AD0 => scuba_vlo, DO0 => empty_cmp_set); + + LUT4_4 : ROM16X1A + generic map (initval => X"1004") + port map (AD3 => rptr_7, AD2 => rcount_7, AD1 => w_gcount_r27, + AD0 => scuba_vlo, DO0 => empty_cmp_clr); + + LUT4_3 : ROM16X1A + generic map (initval => X"0140") + port map (AD3 => wptr_7, AD2 => wcount_7, AD1 => r_gcount_w27, + AD0 => scuba_vlo, DO0 => full_cmp_set); + + LUT4_2 : ROM16X1A + generic map (initval => X"4001") + port map (AD3 => wptr_7, AD2 => wcount_7, AD1 => r_gcount_w27, + AD0 => scuba_vlo, DO0 => full_cmp_clr); + + LUT4_1 : ROM16X1A + generic map (initval => X"4c32") + port map (AD3 => af_setcount_7, AD2 => wcount_7, AD1 => r_gcount_w27, + AD0 => wptr_7, DO0 => af_set_cmp_set); + + LUT4_0 : ROM16X1A + generic map (initval => X"8001") + port map (AD3 => af_setcount_7, AD2 => wcount_7, AD1 => r_gcount_w27, + AD0 => wptr_7, DO0 => af_set_cmp_clr); + + pdp_ram_0_0_0 : PDPW16KC + generic map (CSDECODE_R => "0b001", CSDECODE_W => "0b001", GSR => "DISABLED", + REGMODE => "OUTREG", DATA_WIDTH_R => 36, DATA_WIDTH_W => 36) + port map (DI0 => Data(0), DI1 => Data(1), DI2 => Data(2), DI3 => Data(3), + DI4 => Data(4), DI5 => Data(5), DI6 => Data(6), DI7 => Data(7), + DI8 => Data(8), DI9 => Data(9), DI10 => Data(10), DI11 => Data(11), + DI12 => Data(12), DI13 => Data(13), DI14 => Data(14), + DI15 => Data(15), DI16 => Data(16), DI17 => Data(17), + DI18 => Data(18), DI19 => Data(19), DI20 => Data(20), + DI21 => Data(21), DI22 => Data(22), DI23 => Data(23), + DI24 => Data(24), DI25 => Data(25), DI26 => Data(26), + DI27 => Data(27), DI28 => Data(28), DI29 => Data(29), + DI30 => Data(30), DI31 => Data(31), DI32 => Data(32), + DI33 => Data(33), DI34 => Data(34), DI35 => Data(35), ADW0 => wptr_0, + ADW1 => wptr_1, ADW2 => wptr_2, ADW3 => wptr_3, ADW4 => wptr_4, + ADW5 => wptr_5, ADW6 => wptr_6, ADW7 => scuba_vlo, ADW8 => scuba_vlo, + BE0 => scuba_vhi, BE1 => scuba_vhi, BE2 => scuba_vhi, + BE3 => scuba_vhi, CEW => wren_i, CLKW => WrClock, CSW0 => scuba_vhi, + CSW1 => scuba_vlo, CSW2 => scuba_vlo, ADR0 => scuba_vlo, + ADR1 => scuba_vlo, ADR2 => scuba_vlo, ADR3 => scuba_vlo, + ADR4 => scuba_vlo, ADR5 => rptr_0, ADR6 => rptr_1, ADR7 => rptr_2, + ADR8 => rptr_3, ADR9 => rptr_4, ADR10 => rptr_5, ADR11 => rptr_6, + ADR12 => scuba_vlo, ADR13 => scuba_vlo, CER => scuba_vhi, + CLKR => RdClock, CSR0 => rden_i, CSR1 => scuba_vlo, + CSR2 => scuba_vlo, RST => Reset, DO0 => Q(18), DO1 => Q(19), + DO2 => Q(20), DO3 => Q(21), DO4 => Q(22), DO5 => Q(23), DO6 => Q(24), + DO7 => Q(25), DO8 => Q(26), DO9 => Q(27), DO10 => Q(28), DO11 => Q(29), + DO12 => Q(30), DO13 => Q(31), DO14 => Q(32), DO15 => Q(33), + DO16 => Q(34), DO17 => Q(35), DO18 => Q(0), DO19 => Q(1), DO20 => Q(2), + DO21 => Q(3), DO22 => Q(4), DO23 => Q(5), DO24 => Q(6), DO25 => Q(7), + DO26 => Q(8), DO27 => Q(9), DO28 => Q(10), DO29 => Q(11), + DO30 => Q(12), DO31 => Q(13), DO32 => Q(14), DO33 => Q(15), + DO34 => Q(16), DO35 => Q(17)); + + FF_90 : FD1P3BX + port map (D => iwcount_0, SP => wren_i, CK => WrClock, PD => Reset, + Q => wcount_0); + + FF_89 : FD1P3DX + port map (D => iwcount_1, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_1); + + FF_88 : FD1P3DX + port map (D => iwcount_2, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_2); + + FF_87 : FD1P3DX + port map (D => iwcount_3, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_3); + + FF_86 : FD1P3DX + port map (D => iwcount_4, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_4); + + FF_85 : FD1P3DX + port map (D => iwcount_5, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_5); + + FF_84 : FD1P3DX + port map (D => iwcount_6, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_6); + + FF_83 : FD1P3DX + port map (D => iwcount_7, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_7); + + FF_82 : FD1P3DX + port map (D => w_gdata_0, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_0); + + FF_81 : FD1P3DX + port map (D => w_gdata_1, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_1); + + FF_80 : FD1P3DX + port map (D => w_gdata_2, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_2); + + FF_79 : FD1P3DX + port map (D => w_gdata_3, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_3); + + FF_78 : FD1P3DX + port map (D => w_gdata_4, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_4); + + FF_77 : FD1P3DX + port map (D => w_gdata_5, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_5); + + FF_76 : FD1P3DX + port map (D => w_gdata_6, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_6); + + FF_75 : FD1P3DX + port map (D => wcount_7, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_7); + + FF_74 : FD1P3DX + port map (D => wcount_0, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_0); + + FF_73 : FD1P3DX + port map (D => wcount_1, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_1); + + FF_72 : FD1P3DX + port map (D => wcount_2, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_2); + + FF_71 : FD1P3DX + port map (D => wcount_3, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_3); + + FF_70 : FD1P3DX + port map (D => wcount_4, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_4); + + FF_69 : FD1P3DX + port map (D => wcount_5, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_5); + + FF_68 : FD1P3DX + port map (D => wcount_6, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_6); + + FF_67 : FD1P3DX + port map (D => wcount_7, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_7); + + FF_66 : FD1P3BX + port map (D => ircount_0, SP => rden_i, CK => RdClock, PD => rRst, + Q => rcount_0); + + FF_65 : FD1P3DX + port map (D => ircount_1, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_1); + + FF_64 : FD1P3DX + port map (D => ircount_2, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_2); + + FF_63 : FD1P3DX + port map (D => ircount_3, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_3); + + FF_62 : FD1P3DX + port map (D => ircount_4, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_4); + + FF_61 : FD1P3DX + port map (D => ircount_5, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_5); + + FF_60 : FD1P3DX + port map (D => ircount_6, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_6); + + FF_59 : FD1P3DX + port map (D => ircount_7, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_7); + + FF_58 : FD1P3DX + port map (D => r_gdata_0, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_0); + + FF_57 : FD1P3DX + port map (D => r_gdata_1, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_1); + + FF_56 : FD1P3DX + port map (D => r_gdata_2, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_2); + + FF_55 : FD1P3DX + port map (D => r_gdata_3, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_3); + + FF_54 : FD1P3DX + port map (D => r_gdata_4, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_4); + + FF_53 : FD1P3DX + port map (D => r_gdata_5, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_5); + + FF_52 : FD1P3DX + port map (D => r_gdata_6, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_6); + + FF_51 : FD1P3DX + port map (D => rcount_7, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_7); + + FF_50 : FD1P3DX + port map (D => rcount_0, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_0); + + FF_49 : FD1P3DX + port map (D => rcount_1, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_1); + + FF_48 : FD1P3DX + port map (D => rcount_2, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_2); + + FF_47 : FD1P3DX + port map (D => rcount_3, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_3); + + FF_46 : FD1P3DX + port map (D => rcount_4, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_4); + + FF_45 : FD1P3DX + port map (D => rcount_5, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_5); + + FF_44 : FD1P3DX + port map (D => rcount_6, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_6); + + FF_43 : FD1P3DX + port map (D => rcount_7, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_7); + + FF_42 : FD1S3DX + port map (D => w_gcount_0, CK => RdClock, CD => Reset, Q => w_gcount_r0); + + FF_41 : FD1S3DX + port map (D => w_gcount_1, CK => RdClock, CD => Reset, Q => w_gcount_r1); + + FF_40 : FD1S3DX + port map (D => w_gcount_2, CK => RdClock, CD => Reset, Q => w_gcount_r2); + + FF_39 : FD1S3DX + port map (D => w_gcount_3, CK => RdClock, CD => Reset, Q => w_gcount_r3); + + FF_38 : FD1S3DX + port map (D => w_gcount_4, CK => RdClock, CD => Reset, Q => w_gcount_r4); + + FF_37 : FD1S3DX + port map (D => w_gcount_5, CK => RdClock, CD => Reset, Q => w_gcount_r5); + + FF_36 : FD1S3DX + port map (D => w_gcount_6, CK => RdClock, CD => Reset, Q => w_gcount_r6); + + FF_35 : FD1S3DX + port map (D => w_gcount_7, CK => RdClock, CD => Reset, Q => w_gcount_r7); + + FF_34 : FD1S3DX + port map (D => r_gcount_0, CK => WrClock, CD => rRst, Q => r_gcount_w0); + + FF_33 : FD1S3DX + port map (D => r_gcount_1, CK => WrClock, CD => rRst, Q => r_gcount_w1); + + FF_32 : FD1S3DX + port map (D => r_gcount_2, CK => WrClock, CD => rRst, Q => r_gcount_w2); + + FF_31 : FD1S3DX + port map (D => r_gcount_3, CK => WrClock, CD => rRst, Q => r_gcount_w3); + + FF_30 : FD1S3DX + port map (D => r_gcount_4, CK => WrClock, CD => rRst, Q => r_gcount_w4); + + FF_29 : FD1S3DX + port map (D => r_gcount_5, CK => WrClock, CD => rRst, Q => r_gcount_w5); + + FF_28 : FD1S3DX + port map (D => r_gcount_6, CK => WrClock, CD => rRst, Q => r_gcount_w6); + + FF_27 : FD1S3DX + port map (D => r_gcount_7, CK => WrClock, CD => rRst, Q => r_gcount_w7); + + FF_26 : FD1S3DX + port map (D => w_gcount_r0, CK => RdClock, CD => Reset, + Q => w_gcount_r20); + + FF_25 : FD1S3DX + port map (D => w_gcount_r1, CK => RdClock, CD => Reset, + Q => w_gcount_r21); + + FF_24 : FD1S3DX + port map (D => w_gcount_r2, CK => RdClock, CD => Reset, + Q => w_gcount_r22); + + FF_23 : FD1S3DX + port map (D => w_gcount_r3, CK => RdClock, CD => Reset, + Q => w_gcount_r23); + + FF_22 : FD1S3DX + port map (D => w_gcount_r4, CK => RdClock, CD => Reset, + Q => w_gcount_r24); + + FF_21 : FD1S3DX + port map (D => w_gcount_r5, CK => RdClock, CD => Reset, + Q => w_gcount_r25); + + FF_20 : FD1S3DX + port map (D => w_gcount_r6, CK => RdClock, CD => Reset, + Q => w_gcount_r26); + + FF_19 : FD1S3DX + port map (D => w_gcount_r7, CK => RdClock, CD => Reset, + Q => w_gcount_r27); + + FF_18 : FD1S3DX + port map (D => r_gcount_w0, CK => WrClock, CD => rRst, Q => r_gcount_w20); + + FF_17 : FD1S3DX + port map (D => r_gcount_w1, CK => WrClock, CD => rRst, Q => r_gcount_w21); + + FF_16 : FD1S3DX + port map (D => r_gcount_w2, CK => WrClock, CD => rRst, Q => r_gcount_w22); + + FF_15 : FD1S3DX + port map (D => r_gcount_w3, CK => WrClock, CD => rRst, Q => r_gcount_w23); + + FF_14 : FD1S3DX + port map (D => r_gcount_w4, CK => WrClock, CD => rRst, Q => r_gcount_w24); + + FF_13 : FD1S3DX + port map (D => r_gcount_w5, CK => WrClock, CD => rRst, Q => r_gcount_w25); + + FF_12 : FD1S3DX + port map (D => r_gcount_w6, CK => WrClock, CD => rRst, Q => r_gcount_w26); + + FF_11 : FD1S3DX + port map (D => r_gcount_w7, CK => WrClock, CD => rRst, Q => r_gcount_w27); + + FF_10 : FD1S3BX + port map (D => empty_d, CK => RdClock, PD => rRst, Q => empty_i); + + FF_9 : FD1S3DX + port map (D => full_d, CK => WrClock, CD => Reset, Q => full_i); + + FF_8 : FD1P3DX + port map (D => iaf_setcount_0, SP => wren_i, CK => WrClock, CD => Reset, + Q => af_setcount_0); + + FF_7 : FD1P3DX + port map (D => iaf_setcount_1, SP => wren_i, CK => WrClock, CD => Reset, + Q => af_setcount_1); + + FF_6 : FD1P3BX + port map (D => iaf_setcount_2, SP => wren_i, CK => WrClock, PD => Reset, + Q => af_setcount_2); + + FF_5 : FD1P3DX + port map (D => iaf_setcount_3, SP => wren_i, CK => WrClock, CD => Reset, + Q => af_setcount_3); + + FF_4 : FD1P3DX + port map (D => iaf_setcount_4, SP => wren_i, CK => WrClock, CD => Reset, + Q => af_setcount_4); + + FF_3 : FD1P3DX + port map (D => iaf_setcount_5, SP => wren_i, CK => WrClock, CD => Reset, + Q => af_setcount_5); + + FF_2 : FD1P3DX + port map (D => iaf_setcount_6, SP => wren_i, CK => WrClock, CD => Reset, + Q => af_setcount_6); + + FF_1 : FD1P3DX + port map (D => iaf_setcount_7, SP => wren_i, CK => WrClock, CD => Reset, + Q => af_setcount_7); + + FF_0 : FD1S3DX + port map (D => af_set, CK => WrClock, CD => Reset, Q => AlmostFull); + + w_gctr_cia : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo, + B1 => scuba_vhi, CI => scuba_vlo, COUT => w_gctr_ci, S0 => open, + S1 => open); + + w_gctr_0 : CU2 + port map (CI => w_gctr_ci, PC0 => wcount_0, PC1 => wcount_1, CO => co0, + NC0 => iwcount_0, NC1 => iwcount_1); + + w_gctr_1 : CU2 + port map (CI => co0, PC0 => wcount_2, PC1 => wcount_3, CO => co1, + NC0 => iwcount_2, NC1 => iwcount_3); + + w_gctr_2 : CU2 + port map (CI => co1, PC0 => wcount_4, PC1 => wcount_5, CO => co2, + NC0 => iwcount_4, NC1 => iwcount_5); + + w_gctr_3 : CU2 + port map (CI => co2, PC0 => wcount_6, PC1 => wcount_7, CO => co3, + NC0 => iwcount_6, NC1 => iwcount_7); + + r_gctr_cia : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo, + B1 => scuba_vhi, CI => scuba_vlo, COUT => r_gctr_ci, S0 => open, + S1 => open); + + r_gctr_0 : CU2 + port map (CI => r_gctr_ci, PC0 => rcount_0, PC1 => rcount_1, CO => co0_1, + NC0 => ircount_0, NC1 => ircount_1); + + r_gctr_1 : CU2 + port map (CI => co0_1, PC0 => rcount_2, PC1 => rcount_3, CO => co1_1, + NC0 => ircount_2, NC1 => ircount_3); + + r_gctr_2 : CU2 + port map (CI => co1_1, PC0 => rcount_4, PC1 => rcount_5, CO => co2_1, + NC0 => ircount_4, NC1 => ircount_5); + + r_gctr_3 : CU2 + port map (CI => co2_1, PC0 => rcount_6, PC1 => rcount_7, CO => co3_1, + NC0 => ircount_6, NC1 => ircount_7); + + empty_cmp_ci_a : FADD2B + port map (A0 => scuba_vlo, A1 => rden_i, B0 => scuba_vlo, B1 => rden_i, + CI => scuba_vlo, COUT => cmp_ci, S0 => open, S1 => open); + + empty_cmp_0 : AGEB2 + port map (A0 => rcount_0, A1 => rcount_1, B0 => wcount_r0, + B1 => wcount_r1, CI => cmp_ci, GE => co0_2); + + empty_cmp_1 : AGEB2 + port map (A0 => rcount_2, A1 => rcount_3, B0 => wcount_r2, + B1 => wcount_r3, CI => co0_2, GE => co1_2); + + empty_cmp_2 : AGEB2 + port map (A0 => rcount_4, A1 => rcount_5, B0 => w_g2b_xor_cluster_0, + B1 => wcount_r5, CI => co1_2, GE => co2_2); + + empty_cmp_3 : AGEB2 + port map (A0 => rcount_6, A1 => empty_cmp_set, B0 => wcount_r6, + B1 => empty_cmp_clr, CI => co2_2, GE => empty_d_c); + + a0 : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo, + B1 => scuba_vlo, CI => empty_d_c, COUT => open, S0 => empty_d, + S1 => open); + + full_cmp_ci_a : FADD2B + port map (A0 => scuba_vlo, A1 => wren_i, B0 => scuba_vlo, B1 => wren_i, + CI => scuba_vlo, COUT => cmp_ci_1, S0 => open, S1 => open); + + full_cmp_0 : AGEB2 + port map (A0 => wcount_0, A1 => wcount_1, B0 => rcount_w0, + B1 => rcount_w1, CI => cmp_ci_1, GE => co0_3); + + full_cmp_1 : AGEB2 + port map (A0 => wcount_2, A1 => wcount_3, B0 => rcount_w2, + B1 => rcount_w3, CI => co0_3, GE => co1_3); + + full_cmp_2 : AGEB2 + port map (A0 => wcount_4, A1 => wcount_5, B0 => r_g2b_xor_cluster_0, + B1 => rcount_w5, CI => co1_3, GE => co2_3); + + full_cmp_3 : AGEB2 + port map (A0 => wcount_6, A1 => full_cmp_set, B0 => rcount_w6, + B1 => full_cmp_clr, CI => co2_3, GE => full_d_c); + + a1 : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo, + B1 => scuba_vlo, CI => full_d_c, COUT => open, S0 => full_d, + S1 => open); + + scuba_vhi_inst : VHI + port map (Z => scuba_vhi); + + af_set_ctr_cia : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo, + B1 => scuba_vhi, CI => scuba_vlo, COUT => af_set_ctr_ci, S0 => open, + S1 => open); + + af_set_ctr_0 : CU2 + port map (CI => af_set_ctr_ci, PC0 => af_setcount_0, + PC1 => af_setcount_1, CO => co0_4, NC0 => iaf_setcount_0, + NC1 => iaf_setcount_1); + + af_set_ctr_1 : CU2 + port map (CI => co0_4, PC0 => af_setcount_2, PC1 => af_setcount_3, + CO => co1_4, NC0 => iaf_setcount_2, NC1 => iaf_setcount_3); + + af_set_ctr_2 : CU2 + port map (CI => co1_4, PC0 => af_setcount_4, PC1 => af_setcount_5, + CO => co2_4, NC0 => iaf_setcount_4, NC1 => iaf_setcount_5); + + af_set_ctr_3 : CU2 + port map (CI => co2_4, PC0 => af_setcount_6, PC1 => af_setcount_7, + CO => co3_2, NC0 => iaf_setcount_6, NC1 => iaf_setcount_7); + + af_set_cmp_ci_a : FADD2B + port map (A0 => scuba_vlo, A1 => wren_i, B0 => scuba_vlo, B1 => wren_i, + CI => scuba_vlo, COUT => cmp_ci_2, S0 => open, S1 => open); + + af_set_cmp_0 : AGEB2 + port map (A0 => af_setcount_0, A1 => af_setcount_1, B0 => rcount_w0, + B1 => rcount_w1, CI => cmp_ci_2, GE => co0_5); + + af_set_cmp_1 : AGEB2 + port map (A0 => af_setcount_2, A1 => af_setcount_3, B0 => rcount_w2, + B1 => rcount_w3, CI => co0_5, GE => co1_5); + + af_set_cmp_2 : AGEB2 + port map (A0 => af_setcount_4, A1 => af_setcount_5, + B0 => r_g2b_xor_cluster_0, B1 => rcount_w5, CI => co1_5, GE => co2_5); + + af_set_cmp_3 : AGEB2 + port map (A0 => af_setcount_6, A1 => af_set_cmp_set, B0 => rcount_w6, + B1 => af_set_cmp_clr, CI => co2_5, GE => af_set_c); + + scuba_vlo_inst : VLO + port map (Z => scuba_vlo); + + a2 : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo, + B1 => scuba_vlo, CI => af_set_c, COUT => open, S0 => af_set, + S1 => open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of FIFO_DC_36x128_OutReg is + for Structure + for all : AGEB2 use entity ecp3.AGEB2(V); end for; + for all : AND2 use entity ecp3.AND2(V); end for; + for all : CU2 use entity ecp3.CU2(V); end for; + for all : FADD2B use entity ecp3.FADD2B(V); end for; + for all : FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all : FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all : FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all : FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all : INV use entity ecp3.INV(V); end for; + for all : OR2 use entity ecp3.OR2(V); end for; + for all : ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all : VHI use entity ecp3.VHI(V); end for; + for all : VLO use entity ecp3.VLO(V); end for; + for all : XOR2 use entity ecp3.XOR2(V); end for; + for all : PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd index 6f45278..ec9b8cf 100644 --- a/base/trb3_components.vhd +++ b/base/trb3_components.vhd @@ -13,18 +13,6 @@ package trb3_components is type std_logic_vector_array_8 is array (integer range <>) of std_logic_vector(7 downto 0); type unsigned_array_8 is array (integer range <>) of unsigned(7 downto 0); - --already in trb_net_components --- component pll_in200_out100 --- port ( --- CLK : in std_logic; --- RESET : in std_logic := '0'; --- CLKOP : out std_logic; --100 MHz --- CLKOK : out std_logic; --200 MHz, bypass --- LOCK : out std_logic --- ); --- end component; - - component oddr is port ( clk : in std_logic; @@ -34,7 +22,6 @@ package trb3_components is q : out std_logic_vector(0 downto 0)); end component; - component pll_in125_out125 port ( CLK : in std_logic; @@ -51,12 +38,14 @@ package trb3_components is CLKOK : out std_logic; -- 125 MHz, bypass LOCK : out std_logic); end component pll_in125_out20; - + component TDC is generic ( CHANNEL_NUMBER : integer range 2 to 65; CONTROL_REG_NR : integer range 0 to 6; - TDC_VERSION : std_logic_vector(10 downto 0)); + TDC_VERSION : std_logic_vector(11 downto 0); + DEBUG : integer range 0 to 1 := c_YES; + SIMULATION : integer range 0 to 1 := c_NO); port ( RESET : in std_logic; CLK_TDC : in std_logic; @@ -176,9 +165,12 @@ package trb3_components is COARSE_COUNTER_IN : in std_logic_vector(10 downto 0)); end component; - component Channel is + component Channel generic ( - CHANNEL_ID : integer range 0 to 64); + CHANNEL_ID : integer range 0 to 64; + DEBUG : integer range 0 to 1; + SIMULATION : integer range 0 to 1; + REFERENCE : integer range 0 to 1); port ( RESET_200 : in std_logic; RESET_100 : in std_logic; @@ -186,66 +178,129 @@ package trb3_components is CLK_200 : in std_logic; CLK_100 : in std_logic; HIT_IN : in std_logic; - TRIGGER_IN : in std_logic; -- not used after version 1.3 - TRIGGER_WIN_END_IN : in std_logic; + TRIGGER_WIN_END_TDC : in std_logic; + TRIGGER_WIN_END_RDO : in std_logic; READ_EN_IN : in std_logic; FIFO_DATA_OUT : out std_logic_vector(35 downto 0); - FIFO_WCNT_OUT : out unsigned(7 downto 0); + FIFO_DATA_VALID_OUT : out std_logic; FIFO_EMPTY_OUT : out std_logic; FIFO_FULL_OUT : out std_logic; + FIFO_ALMOST_EMPTY_OUT : out std_logic; FIFO_ALMOST_FULL_OUT : out std_logic; COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + VALID_TIMING_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + EPOCH_WRITE_EN_IN : in std_logic; LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0); ENCODER_START_NUMBER : out std_logic_vector(23 downto 0); ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0); + FIFO_WRITE_NUMBER : out std_logic_vector(23 downto 0); + Channel_200_DEBUG : out std_logic_vector(31 downto 0); Channel_DEBUG : out std_logic_vector(31 downto 0)); - end component Channel; + end component; - component Channel_200 is + component Channel_200 generic ( - CHANNEL_ID : integer range 0 to 64); + CHANNEL_ID : integer range 0 to 64; + SIMULATION : integer range 0 to 1; + REFERENCE : integer range 0 to 1); port ( CLK_200 : in std_logic; RESET_200 : in std_logic; CLK_100 : in std_logic; RESET_100 : in std_logic; HIT_IN : in std_logic; - TRIGGER_IN : in std_logic; -- not used after version 1.3 - TRIGGER_WIN_END_IN : in std_logic; + TRIGGER_WIN_END_TDC : in std_logic; + TRIGGER_WIN_END_RDO : in std_logic; EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); READ_EN_IN : in std_logic; FIFO_DATA_OUT : out std_logic_vector(35 downto 0); - FIFO_WCNT_OUT : out unsigned(7 downto 0); + FIFO_DATA_VALID_OUT : out std_logic; FIFO_EMPTY_OUT : out std_logic; FIFO_FULL_OUT : out std_logic; FIFO_ALMOST_FULL_OUT : out std_logic; + VALID_TIMING_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + EPOCH_WRITE_EN_IN : in std_logic; ENCODER_START_OUT : out std_logic; - ENCODER_FINISHED_OUT : out std_logic); - end component Channel_200; + ENCODER_FINISHED_OUT : out std_logic; + FIFO_WRITE_OUT : out std_logic; + Channel_200_DEBUG : out std_logic_vector(31 downto 0)); + end component; + +-- component Channel is +-- generic ( +-- CHANNEL_ID : integer range 0 to 64); +-- port ( +-- RESET_200 : in std_logic; +-- RESET_100 : in std_logic; +-- RESET_COUNTERS : in std_logic; +-- CLK_200 : in std_logic; +-- CLK_100 : in std_logic; +-- HIT_IN : in std_logic; +---- TRIGGER_IN : in std_logic; -- not used after version 1.3 +-- TRIGGER_WIN_END_IN : in std_logic; +-- READ_EN_IN : in std_logic; +-- FIFO_DATA_OUT : out std_logic_vector(35 downto 0); +-- FIFO_WCNT_OUT : out unsigned(7 downto 0); +-- FIFO_EMPTY_OUT : out std_logic; +-- FIFO_FULL_OUT : out std_logic; +-- FIFO_ALMOST_FULL_OUT : out std_logic; +-- COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); +-- EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); +-- LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); +-- HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0); +-- ENCODER_START_NUMBER : out std_logic_vector(23 downto 0); +-- ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0); +-- Channel_DEBUG : out std_logic_vector(31 downto 0)); +-- end component Channel; + +-- component Channel_200 is +-- generic ( +-- CHANNEL_ID : integer range 0 to 64); +-- port ( +-- CLK_200 : in std_logic; +-- RESET_200 : in std_logic; +-- CLK_100 : in std_logic; +-- RESET_100 : in std_logic; +-- HIT_IN : in std_logic; +---- TRIGGER_IN : in std_logic; -- not used after version 1.3 +-- TRIGGER_WIN_END_IN : in std_logic; +-- EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); +-- COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); +-- READ_EN_IN : in std_logic; +-- FIFO_DATA_OUT : out std_logic_vector(35 downto 0); +-- FIFO_WCNT_OUT : out unsigned(7 downto 0); +-- FIFO_EMPTY_OUT : out std_logic; +-- FIFO_FULL_OUT : out std_logic; +-- FIFO_ALMOST_FULL_OUT : out std_logic; +-- ENCODER_START_OUT : out std_logic; +-- ENCODER_FINISHED_OUT : out std_logic); +-- end component Channel_200; + component Readout is generic ( CHANNEL_NUMBER : integer range 2 to 65; - TDC_VERSION : std_logic_vector(10 downto 0)); + TDC_VERSION : std_logic_vector(11 downto 0)); port ( - CLK_200 : in std_logic; - RESET_200 : in std_logic; - CLK_100 : in std_logic; RESET_100 : in std_logic; + RESET_200 : in std_logic; RESET_COUNTERS : in std_logic; - REFERENCE_TIME : in std_logic; - TRIGGER_TIME_IN : in std_logic_vector(38 downto 0); - TRG_WIN_PRE : in std_logic_vector(10 downto 0); - TRG_WIN_POST : in std_logic_vector(10 downto 0); - DEBUG_MODE_EN_IN : in std_logic; - TRIGGER_WIN_EN_IN : in std_logic; + CLK_100 : in std_logic; + CLK_200 : in std_logic; + TRIGGER_RDO_IN : in std_logic; + TRIGGER_TDC_IN : in std_logic; CH_DATA_IN : in std_logic_vector_array_36(0 to CHANNEL_NUMBER); - CH_WCNT_IN : in unsigned_array_8(0 to CHANNEL_NUMBER-1); - CH_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER downto 0); + CH_DATA_VALID_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); CH_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_ALMOST_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); CH_ALMOST_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); TRG_DATA_VALID_IN : in std_logic; VALID_TIMING_TRG_IN : in std_logic; @@ -266,11 +321,25 @@ package trb3_components is DATA_WRITE_OUT : out std_logic; DATA_FINISHED_OUT : out std_logic; READ_EN_OUT : out std_logic_vector(CHANNEL_NUMBER-1 downto 0); + TRG_WIN_PRE : in std_logic_vector(10 downto 0); + TRG_WIN_POST : in std_logic_vector(10 downto 0); + TRIGGER_WIN_EN_IN : in std_logic; + TRIG_WIN_END_TDC_IN : in std_logic; + TRIG_WIN_END_RDO_IN : in std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + DEBUG_MODE_EN_IN : in std_logic; + STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to 20); + READOUT_DEBUG : out std_logic_vector(31 downto 0); +-- ports not used after tdc_v1.5.2 TRIGGER_WIN_END_OUT : out std_logic; - STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to 18); - READOUT_DEBUG : out std_logic_vector(31 downto 0)); + CH_WCNT_IN : in unsigned_array_8(0 to CHANNEL_NUMBER-1); + REFERENCE_TIME : in std_logic; + TRIGGER_TIME_IN : in std_logic_vector(38 downto 0) + ); end component Readout; + component TriggerHandler is generic ( TRIGGER_NUM : integer; @@ -290,7 +359,7 @@ package trb3_components is TRIGGER_WIN_END_RDO_OUT : out std_logic; TRIGGER_WIN_END_TDC_OUT : out std_logic); end component TriggerHandler; - + component LogicAnalyser generic ( CHANNEL_NUMBER : integer range 2 to 65); @@ -384,6 +453,34 @@ package trb3_components is AlmostFull : out std_logic); end component; + component FIFO_36x128_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic); + end component FIFO_36x128_OutReg; + + component FIFO_DC_36x128_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic); + end component FIFO_DC_36x128_OutReg; + component FIFO_36x128_OutReg_Counter is port ( Data : in std_logic_vector(35 downto 0); diff --git a/base/trb3_periph_32PinAddOn.lpf b/base/trb3_periph_32PinAddOn.lpf new file mode 100644 index 0000000..1fb3d5a --- /dev/null +++ b/base/trb3_periph_32PinAddOn.lpf @@ -0,0 +1,218 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + + +################################################################# +# Basic Settings +################################################################# + +SYSCONFIG MCCLK_FREQ = 20; + +FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; +FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; +FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; + +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1"; +LOCATE COMP "CLK_PCLK_LEFT" SITE "M4"; +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; +LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; +LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; + +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; + +################################################################# +# Trigger I/O +################################################################# + +#Trigger from fan-out +LOCATE COMP "TRIGGER_RIGHT" SITE "N24"; +IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25; + +LOCATE COMP "TRIGGER_LEFT" SITE "V3"; +IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25; + +################################################################# +# To central FPGA +################################################################# + +LOCATE COMP "FPGA5_COMM_0" SITE "AD4"; +LOCATE COMP "FPGA5_COMM_1" SITE "AE3"; +LOCATE COMP "FPGA5_COMM_2" SITE "AA7"; +LOCATE COMP "FPGA5_COMM_3" SITE "AB7"; +LOCATE COMP "FPGA5_COMM_4" SITE "AD3"; +LOCATE COMP "FPGA5_COMM_5" SITE "AC4"; +LOCATE COMP "FPGA5_COMM_6" SITE "AE2"; +LOCATE COMP "FPGA5_COMM_7" SITE "AF3"; +LOCATE COMP "FPGA5_COMM_8" SITE "AE4"; +LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; +LOCATE COMP "FPGA5_COMM_10" SITE "V10"; +LOCATE COMP "FPGA5_COMM_11" SITE "W10"; +DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +LOCATE COMP "TEST_LINE_0" SITE "A5"; +LOCATE COMP "TEST_LINE_1" SITE "A6"; +LOCATE COMP "TEST_LINE_2" SITE "G8"; +LOCATE COMP "TEST_LINE_3" SITE "F9"; +LOCATE COMP "TEST_LINE_4" SITE "D9"; +LOCATE COMP "TEST_LINE_5" SITE "D10"; +LOCATE COMP "TEST_LINE_6" SITE "F10"; +LOCATE COMP "TEST_LINE_7" SITE "E10"; +LOCATE COMP "TEST_LINE_8" SITE "A8"; +LOCATE COMP "TEST_LINE_9" SITE "B8"; +LOCATE COMP "TEST_LINE_10" SITE "G10"; +LOCATE COMP "TEST_LINE_11" SITE "G9"; +LOCATE COMP "TEST_LINE_12" SITE "C9"; +LOCATE COMP "TEST_LINE_13" SITE "C10"; +LOCATE COMP "TEST_LINE_14" SITE "H10"; +LOCATE COMP "TEST_LINE_15" SITE "H11"; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12; + +################################################################# +# TDC INPUTS +################################################################# + +LOCATE COMP "INP_0" SITE "P1"; +LOCATE COMP "INP_1" SITE "T2"; +LOCATE COMP "INP_2" SITE "R1"; +LOCATE COMP "INP_3" SITE "N3"; +LOCATE COMP "INP_4" SITE "P5"; +LOCATE COMP "INP_5" SITE "N5"; +LOCATE COMP "INP_6" SITE "AC2"; +LOCATE COMP "INP_7" SITE "AB1"; +LOCATE COMP "INP_8" SITE "AA1"; +LOCATE COMP "INP_9" SITE "W7"; +LOCATE COMP "INP_10" SITE "Y5"; +LOCATE COMP "INP_11" SITE "V6"; +LOCATE COMP "INP_12" SITE "H2"; +LOCATE COMP "INP_13" SITE "K3"; +LOCATE COMP "INP_14" SITE "H1"; +LOCATE COMP "INP_15" SITE "M5"; +LOCATE COMP "INP_16" SITE "AD1"; +LOCATE COMP "INP_17" SITE "AB5"; +LOCATE COMP "INP_18" SITE "AB3"; +LOCATE COMP "INP_19" SITE "Y6"; +LOCATE COMP "INP_20" SITE "AA3"; +LOCATE COMP "INP_21" SITE "W8"; +LOCATE COMP "INP_22" SITE "V1"; +LOCATE COMP "INP_23" SITE "T1"; +LOCATE COMP "INP_24" SITE "P4"; +LOCATE COMP "INP_25" SITE "T3"; +LOCATE COMP "INP_26" SITE "R5"; +LOCATE COMP "INP_27" SITE "T7"; +LOCATE COMP "INP_28" SITE "K2"; +LOCATE COMP "INP_29" SITE "J4"; +LOCATE COMP "INP_30" SITE "D1"; +LOCATE COMP "INP_31" SITE "K4"; +LOCATE COMP "INP_32" SITE "J23"; +LOCATE COMP "INP_33" SITE "G26"; +LOCATE COMP "INP_34" SITE "F24"; +LOCATE COMP "INP_35" SITE "H26"; +LOCATE COMP "INP_36" SITE "K23"; +LOCATE COMP "INP_37" SITE "F25"; +LOCATE COMP "INP_38" SITE "AC26"; +LOCATE COMP "INP_39" SITE "Y19"; +LOCATE COMP "INP_40" SITE "AB24"; +LOCATE COMP "INP_41" SITE "Y22"; +LOCATE COMP "INP_42" SITE "AD24"; +LOCATE COMP "INP_43" SITE "AE25"; +LOCATE COMP "INP_44" SITE "W23"; +LOCATE COMP "INP_45" SITE "AA25"; +LOCATE COMP "INP_46" SITE "AA26"; +LOCATE COMP "INP_47" SITE "W21"; +LOCATE COMP "INP_48" SITE "H24"; +LOCATE COMP "INP_49" SITE "L20"; +LOCATE COMP "INP_50" SITE "K24"; +LOCATE COMP "INP_51" SITE "M23"; +LOCATE COMP "INP_52" SITE "L24"; +LOCATE COMP "INP_53" SITE "M22"; +LOCATE COMP "INP_54" SITE "J26"; +LOCATE COMP "INP_55" SITE "N23"; +LOCATE COMP "INP_56" SITE "K19"; +LOCATE COMP "INP_57" SITE "P23"; +LOCATE COMP "INP_58" SITE "L25"; +LOCATE COMP "INP_59" SITE "P21"; +LOCATE COMP "INP_60" SITE "R25"; +LOCATE COMP "INP_61" SITE "T25"; +LOCATE COMP "INP_62" SITE "T26"; +LOCATE COMP "INP_63" SITE "V21"; + +DEFINE PORT GROUP "INP_group" "INP*" ; +IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +################################################################# +# Additional Lines to AddOn +################################################################# + +#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 +#all lines are input only +#line 4/5 go to PLL input +LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 +LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 +LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 +LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 + +################################################################# +# DAC SPI & Flash ROM & Reboot +################################################################# + +LOCATE COMP "FLASH_CLK" SITE "B12"; +LOCATE COMP "FLASH_CS" SITE "E11"; +LOCATE COMP "FLASH_DIN" SITE "E12"; +LOCATE COMP "FLASH_DOUT" SITE "A12"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE; + +LOCATE COMP "PROGRAMN" SITE "B11"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + +LOCATE COMP "DAC_IN_SDI" SITE "D4"; #"DQUL_6" DQSUL0_T #86 +LOCATE COMP "DAC_OUT_SCK" SITE "C3"; #"DQUL_4" DQUL0_4 #82 +LOCATE COMP "DAC_OUT_CS" SITE "H6"; #"DQUL_10" DQUL0_8 #94 +LOCATE COMP "DAC_OUT_SDO" SITE "G5"; #"DQUL_2" DQUL0_2 #78 +LOCATE COMP "DAC_OUT_CLR" SITE "U24"; #"DQLR2_6" + +DEFINE PORT GROUP "DAC_IN_group" "DAC_IN_*" ; +IOBUF GROUP "DAC_IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +DEFINE PORT GROUP "DAC_OUT_group" "DAC_OUT_*" ; +IOBUF GROUP "DAC_OUT_group" IO_TYPE=LVDS25; + +IOBUF PORT "DAC_OUT_SDO" IO_TYPE=LVDS25E ; + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "A13"; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + +#coding of FPGA number +LOCATE COMP "CODE_LINE_1" SITE "AA20"; +LOCATE COMP "CODE_LINE_0" SITE "Y21"; +IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +#terminated differential pair to pads +LOCATE COMP "SUPPL" SITE "C14"; +IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; + + +################################################################# +# LED +################################################################# +LOCATE COMP "LED_GREEN" SITE "F12"; +LOCATE COMP "LED_ORANGE" SITE "G13"; +LOCATE COMP "LED_RED" SITE "A15"; +LOCATE COMP "LED_YELLOW" SITE "A16"; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; diff --git a/cbmtof/cbmtof.vhd b/cbmtof/cbmtof.vhd index 9bb2c48..d72824c 100644 --- a/cbmtof/cbmtof.vhd +++ b/cbmtof/cbmtof.vhd @@ -248,7 +248,7 @@ architecture cbmtof_arch of cbmtof is signal tdc_ctrl_read : std_logic; signal last_tdc_ctrl_read : std_logic; signal tdc_ctrl_write : std_logic; - signal tdc_ctrl_addr : std_logic_vector(1 downto 0); + signal tdc_ctrl_addr : std_logic_vector(2 downto 0); signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); signal tdc_ctrl_reg : std_logic_vector(5*32-1 downto 0); @@ -610,8 +610,8 @@ begin BUS_READ_ENABLE_OUT(8) => tdc_ctrl_read, BUS_WRITE_ENABLE_OUT(8) => tdc_ctrl_write, BUS_DATA_OUT(8*32+31 downto 8*32) => tdc_ctrl_data_in, - BUS_ADDR_OUT(8*16+1 downto 8*16) => tdc_ctrl_addr, - BUS_ADDR_OUT(8*16+15 downto 8*16+2) => open, + BUS_ADDR_OUT(8*16+2 downto 8*16) => tdc_ctrl_addr, + BUS_ADDR_OUT(8*16+15 downto 8*16+3) => open, BUS_TIMEOUT_OUT(8) => open, BUS_DATA_IN(8*32+31 downto 8*32) => tdc_ctrl_data_out, BUS_DATAREADY_IN(8) => last_tdc_ctrl_read, @@ -689,24 +689,28 @@ begin -- DAC --------------------------------------------------------------------------- THE_DAC_SPI : spi_ltc2600 + generic map ( + BITS => 14, + WAITCYCLES => 15) port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, + CLK_IN => clk_100_i, + RESET_IN => reset_i, -- Slave bus - BUS_ADDR_IN => dac_addr, - BUS_READ_IN => dac_read_en, - BUS_WRITE_IN => dac_write_en, - BUS_ACK_OUT => dac_ack, - BUS_BUSY_OUT => dac_busy, - BUS_DATA_IN => dac_data_in, - BUS_DATA_OUT => dac_data_out, + BUS_ADDR_IN => dac_addr, + BUS_READ_IN => dac_read_en, + BUS_WRITE_IN => dac_write_en, + BUS_ACK_OUT => dac_ack, + BUS_BUSY_OUT => dac_busy, + BUS_DATA_IN => dac_data_in, + BUS_DATA_OUT => dac_data_out, -- SPI connections - SPI_CS_OUT(0) => DAC_CS, - SPI_SDI_IN => DAC_SDO, - SPI_SDO_OUT => DAC_SDI, - SPI_SCK_OUT => DAC_SCK + SPI_CS_OUT(0) => DAC_CS, + SPI_SDI_IN => DAC_SDO, + SPI_SDO_OUT => DAC_SDI, + SPI_SCK_OUT => DAC_SCK, + SPI_CLR_OUT(0) => DAC_CLR ); - + --------------------------------------------------------------------------- -- Reboot FPGA --------------------------------------------------------------------------- @@ -721,10 +725,10 @@ begin --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- - LED_GREEN <= not time_counter(24); - LED_ORANGE <= not time_counter(25); - LED_RED <= not time_counter(26); - LED_YELLOW <= not time_counter(27); + LED_GREEN <= not time_counter(26); + LED_ORANGE <= not time_counter(27); + LED_RED <= not time_counter(28); + LED_YELLOW <= not time_counter(29); LED_SFP_GREEN <= not med_stat_op(9); LED_SFP_RED <= not (med_stat_op(10) or med_stat_op(11)); @@ -747,7 +751,7 @@ begin --------------------------------------------------------------------------- process begin - wait until rising_edge(clk_100_i); + wait until rising_edge(CLK_EXT);--(clk_100_i); time_counter <= time_counter + 1; end process; @@ -756,16 +760,16 @@ begin ------------------------------------------------------------------------------- THE_TDC : TDC generic map ( - CHANNEL_NUMBER => 33, -- Number of TDC channels + CHANNEL_NUMBER => 65, -- Number of TDC channels CONTROL_REG_NR => 5, -- Number of control regs TDC_VERSION => "001" & x"51") -- TDC version numberTDC_VERSION => "001" & x"51") -- TDC version number port map ( RESET => reset_i, --- CLK_TDC => CLK_OSC, -- Oscillator used for the time measurement - CLK_TDC => CLK_EXT, -- External Clock used for the time measurement + CLK_TDC => CLK_OSC, -- Oscillator used for the time measurement +-- CLK_TDC => CLK_EXT, -- External Clock used for the time measurement CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => hit_in_i(32 downto 1), -- Channel start signals + HIT_IN => hit_in_i(64 downto 1), -- Channel start signals HIT_CALIBRATION => clk_20_i, -- Hits for calibrating the TDC TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width diff --git a/tdc_releases/ReleaseNotes.txt b/tdc_releases/ReleaseNotes.txt index b93a866..73cba68 100644 --- a/tdc_releases/ReleaseNotes.txt +++ b/tdc_releases/ReleaseNotes.txt @@ -4,8 +4,20 @@ tdc_v2.0 15.11.2012 Double edge detection for longer than 20 ns is implemented. (Not stable-will be fixed in future releases.) -tdc_v1.5.2* 06.05.2013 Epoch counter bug fix (data word - epoch word + +tdc_v1.6 20.01.2014 Epoch counter bug fix (data word - epoch word place swap). + Trigger window bug fix (epoch counter more + than 24 bit had integer conversion + problem. Trigger window right side control is + enabled). + Readout algorith change (the channel fifos are + readout to intermediate buffer, so the later + channels in the readout order are kept as the + trigger arrival time) + Trigger on TDC channel (the feature for + triggering on TDC channel is implemented) + Reference channel hit rate counter implemented. tdc_v1.5.1 20.06.2013 Efficiency bug fix (epoch counter update - hit at the same time). Hit level bit bug fix for diff --git a/tdc_releases/tdc_v1.5.1/Channel_200.vhd b/tdc_releases/tdc_v1.5.1/Channel_200.vhd index f49c0ab..c762cb8 100644 --- a/tdc_releases/tdc_v1.5.1/Channel_200.vhd +++ b/tdc_releases/tdc_v1.5.1/Channel_200.vhd @@ -5,7 +5,7 @@ -- File : Channel_200.vhd -- Author : c.ugur@gsi.de -- Created : 2012-08-28 --- Last update: 2013-06-24 +-- Last update: 2014-01-17 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- diff --git a/tdc_releases/tdc_v1.5.1/TDC.vhd b/tdc_releases/tdc_v1.5.1/TDC.vhd index 260e340..f749f95 100644 --- a/tdc_releases/tdc_v1.5.1/TDC.vhd +++ b/tdc_releases/tdc_v1.5.1/TDC.vhd @@ -102,6 +102,10 @@ architecture TDC of TDC is -- 0: free running mode signal run_mode_200 : std_logic; signal run_mode_edge_200 : std_logic; + signal reset_coarse_cntr_i : std_logic; + signal reset_coarse_cntr_200 : std_logic; + signal reset_coarse_cntr_edge_200 : std_logic; + signal reset_coarse_cntr_flag : std_logic := '0'; signal trigger_win_en_i : std_logic; signal ch_en_i : std_logic_vector(64 downto 1); signal data_limit_i : unsigned(7 downto 0); @@ -153,17 +157,21 @@ architecture TDC of TDC is begin -- Slow control signals - logic_anal_control <= CONTROL_REG_IN(3 downto 0) when rising_edge(CLK_READOUT); - debug_mode_en_i <= CONTROL_REG_IN(4); - reset_counters_i <= CONTROL_REG_IN(8); - run_mode_i <= CONTROL_REG_IN(12); - run_mode_200 <= run_mode_i when rising_edge(CLK_TDC); -- Run mode control register synchronised to the coarse counter clk - trigger_win_en_i <= CONTROL_REG_IN(1*32+31); - ch_en_i <= CONTROL_REG_IN(3*32+31 downto 2*32+0); - data_limit_i <= unsigned(CONTROL_REG_IN(4*32+7 downto 4*32+0)); + logic_anal_control <= CONTROL_REG_IN(3 downto 0) when rising_edge(CLK_READOUT); + debug_mode_en_i <= CONTROL_REG_IN(4); + reset_counters_i <= CONTROL_REG_IN(8); + run_mode_i <= CONTROL_REG_IN(12); + run_mode_200 <= run_mode_i when rising_edge(CLK_TDC); -- Run mode control register synchronised to the coarse counter clk + reset_coarse_cntr_i <= CONTROL_REG_IN(13); + reset_coarse_cntr_200 <= reset_coarse_cntr_i when rising_edge(CLK_TDC); -- Reset coarse counter control register synchronised to the coarse counter clk + + trigger_win_en_i <= CONTROL_REG_IN(1*32+31); + ch_en_i <= CONTROL_REG_IN(3*32+31 downto 2*32+0); + data_limit_i <= unsigned(CONTROL_REG_IN(4*32+7 downto 4*32+0)); + -- Reset signal - reset_tdc <= RESET; + reset_tdc <= RESET when rising_edge(CLK_TDC); -- Blocks the input after the rising edge against short pulses GEN_HitBlock : for i in 1 to CHANNEL_NUMBER-1 generate @@ -325,13 +333,22 @@ begin Coarse_Counter_Reset : process (CLK_TDC) begin if rising_edge(CLK_TDC) then - if run_mode_200 = '0' then + if reset_tdc = '1' then + coarse_cntr_reset <= '1'; + elsif run_mode_200 = '0' then coarse_cntr_reset <= trg_win_end_i; elsif run_mode_edge_200 = '1' then coarse_cntr_reset <= '1'; + elsif reset_coarse_cntr_flag = '1' and (VALID_TIMING_TRG_IN = '1' or VALID_NOTIMING_TRG_IN = '1') then + coarse_cntr_reset <= '1'; else coarse_cntr_reset <= '0'; end if; + if reset_coarse_cntr_edge_200 = '1' then + reset_coarse_cntr_flag <= '1'; + elsif VALID_TIMING_TRG_IN = '1' or VALID_NOTIMING_TRG_IN = '1' then + reset_coarse_cntr_flag <= '0'; + end if; end if; end process Coarse_Counter_Reset; @@ -340,6 +357,12 @@ begin CLK => CLK_TDC, SIGNAL_IN => run_mode_200, PULSE_OUT => run_mode_edge_200); + + Reset_Coarse_Counter_Edge_Detect: risingEdgeDetect + port map ( + CLK => CLK_TDC, + SIGNAL_IN => reset_coarse_cntr_200, + PULSE_OUT => reset_coarse_cntr_edge_200); GenCoarseCounterReset : for i in 1 to 4 generate coarse_cntr_reset_r(i) <= coarse_cntr_reset when rising_edge(CLK_TDC); @@ -355,7 +378,7 @@ begin COUNT_OUT => epoch_cntr, UP_IN => epoch_cntr_up_i); epoch_cntr_up_i <= and_all(coarse_cntr(1)); - epoch_cntr_reset_i <= coarse_cntr_reset; + epoch_cntr_reset_i <= coarse_cntr_reset_r(1); -- Bus handler entities TheHitCounterBus : BusHandler @@ -392,19 +415,19 @@ begin DATAREADY_OUT => SRB_DATAREADY_OUT, UNKNOWN_ADDR_OUT => SRB_UNKNOWN_ADDR_OUT); - TheLostHitBus : BusHandler - generic map ( - BUS_LENGTH => CHANNEL_NUMBER-1) - port map ( - RESET => RESET, - CLK => CLK_READOUT, - DATA_IN => ch_lost_hit_bus_i, - READ_EN_IN => LHB_READ_EN_IN, - WRITE_EN_IN => LHB_WRITE_EN_IN, - ADDR_IN => LHB_ADDR_IN, - DATA_OUT => LHB_DATA_OUT, - DATAREADY_OUT => LHB_DATAREADY_OUT, - UNKNOWN_ADDR_OUT => LHB_UNKNOWN_ADDR_OUT); + --TheLostHitBus : BusHandler + -- generic map ( + -- BUS_LENGTH => CHANNEL_NUMBER-1) + -- port map ( + -- RESET => RESET, + -- CLK => CLK_READOUT, + -- DATA_IN => ch_lost_hit_bus_i, + -- READ_EN_IN => LHB_READ_EN_IN, + -- WRITE_EN_IN => LHB_WRITE_EN_IN, + -- ADDR_IN => LHB_ADDR_IN, + -- DATA_OUT => LHB_DATA_OUT, + -- DATAREADY_OUT => LHB_DATAREADY_OUT, + -- UNKNOWN_ADDR_OUT => LHB_UNKNOWN_ADDR_OUT); GenLostHitNumber : for i in 1 to CHANNEL_NUMBER-1 generate ch_lost_hit_bus_i(i) <= x"00" & ch_lost_hit_number_i(i) when rising_edge(CLK_READOUT); diff --git a/tdc_releases/tdc_v1.5.1/tdc_constraints.lpf b/tdc_releases/tdc_v1.5.1/tdc_constraints.lpf index a465eca..b4932ae 100644 --- a/tdc_releases/tdc_v1.5.1/tdc_constraints.lpf +++ b/tdc_releases/tdc_v1.5.1/tdc_constraints.lpf @@ -903,7 +903,7 @@ UGROUP "BusHandlers" ## Unimportant Data Lines ## ############################################################################# -#BLOCK NET "THE_TDC/reset_tdc*" ; +BLOCK NET "THE_TDC/reset_tdc*" ; BLOCK NET "THE_TDC/hit_in_i_*" ; #BLOCK PATH TO CELL "THE_TDC/GEN_Channels_*_Channels/Channel_200_1/FC/FF_*" ; #BLOCK NET "THE_TDC/reset_counters_200*" ; diff --git a/tdc_releases/tdc_v1.5.1/trb3_periph.vhd b/tdc_releases/tdc_v1.5.1/trb3_periph.vhd index 442a26d..47cd89a 100644 --- a/tdc_releases/tdc_v1.5.1/trb3_periph.vhd +++ b/tdc_releases/tdc_v1.5.1/trb3_periph.vhd @@ -346,6 +346,7 @@ begin -- -- x"4" - Wasa AddOn --edge_type_i <= x"0"; -- x"0" - single edge -- -- x"1" - double edge + -- -- x"4" - has spi interface -- -- x"8" - double edge on consecutive channels --tdc_channel_no_i <= x"6"; -- 2^n channels @@ -357,7 +358,7 @@ begin BROADCAST_BITMASK => x"FF", BROADCAST_SPECIAL_ADDR => x"48", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => x"91000060", -- regio_hardware_version_i, + REGIO_HARDWARE_VERSION => x"91000460", -- regio_hardware_version_i, REGIO_INIT_ADDRESS => x"f305", REGIO_USE_VAR_ENDPOINT_ID => c_YES, CLOCK_FREQUENCY => 125, diff --git a/tdc_releases/tdc_v1.6/Adder_304.ngo b/tdc_releases/tdc_v1.6/Adder_304.ngo new file mode 100644 index 0000000..e7a70ba Binary files /dev/null and b/tdc_releases/tdc_v1.6/Adder_304.ngo differ diff --git a/tdc_releases/tdc_v1.6/Adder_304.vhd b/tdc_releases/tdc_v1.6/Adder_304.vhd new file mode 100644 index 0000000..d5b4914 --- /dev/null +++ b/tdc_releases/tdc_v1.6/Adder_304.vhd @@ -0,0 +1,1310 @@ +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + + +entity Adder_304 is + port (CLK : in std_logic; + RESET : in std_logic; + DataA : in std_logic_vector(303 downto 0); + DataB : in std_logic_vector(303 downto 0); + ClkEn : in std_logic; + Result : out std_logic_vector(303 downto 0) + ); +end Adder_304; + +architecture Structure of Adder_304 is + +-- internal signal declarations + signal r0_sum : std_logic_vector(303 downto 0); + signal tsum : std_logic_vector(303 downto 0); + signal co : std_logic_vector(151 downto 0); + signal scuba_vlo : std_logic; + +-- local component declarations + component FADD2B + port (A0 : in std_logic; + A1 : in std_logic; + B0 : in std_logic; + B1 : in std_logic; + CI : in std_logic; + COUT : out std_logic; + S0 : out std_logic; + S1 : out std_logic); + end component; + component FD1P3DX + port (D : in std_logic; + SP : in std_logic; + CK : in std_logic; + CD : in std_logic; + Q : out std_logic); + end component; + component VLO + port (Z : out std_logic); + end component; + + attribute GSR : string; + attribute GSR of FF_303 : label is "ENABLED"; + attribute GSR of FF_302 : label is "ENABLED"; + attribute GSR of FF_301 : label is "ENABLED"; + attribute GSR of FF_300 : label is "ENABLED"; + attribute GSR of FF_299 : label is "ENABLED"; + attribute GSR of FF_298 : label is "ENABLED"; + attribute GSR of FF_297 : label is "ENABLED"; + attribute GSR of FF_296 : label is "ENABLED"; + attribute GSR of FF_295 : label is "ENABLED"; + attribute GSR of FF_294 : label is "ENABLED"; + attribute GSR of FF_293 : label is "ENABLED"; + attribute GSR of FF_292 : label is "ENABLED"; + attribute GSR of FF_291 : label is "ENABLED"; + attribute GSR of FF_290 : label is "ENABLED"; + attribute GSR of FF_289 : label is "ENABLED"; + attribute GSR of FF_288 : label is "ENABLED"; + attribute GSR of FF_287 : label is "ENABLED"; + attribute GSR of FF_286 : label is "ENABLED"; + attribute GSR of FF_285 : label is "ENABLED"; + attribute GSR of FF_284 : label is "ENABLED"; + attribute GSR of FF_283 : label is "ENABLED"; + attribute GSR of FF_282 : label is "ENABLED"; + attribute GSR of FF_281 : label is "ENABLED"; + attribute GSR of FF_280 : label is "ENABLED"; + attribute GSR of FF_279 : label is "ENABLED"; + attribute GSR of FF_278 : label is "ENABLED"; + attribute GSR of FF_277 : label is "ENABLED"; + attribute GSR of FF_276 : label is "ENABLED"; + attribute GSR of FF_275 : label is "ENABLED"; + attribute GSR of FF_274 : label is "ENABLED"; + attribute GSR of FF_273 : label is "ENABLED"; + attribute GSR of FF_272 : label is "ENABLED"; + attribute GSR of FF_271 : label is "ENABLED"; + attribute GSR of FF_270 : label is "ENABLED"; + attribute GSR of FF_269 : label is "ENABLED"; + attribute GSR of FF_268 : label is "ENABLED"; + attribute GSR of FF_267 : label is "ENABLED"; + attribute GSR of FF_266 : label is "ENABLED"; + attribute GSR of FF_265 : label is "ENABLED"; + attribute GSR of FF_264 : label is "ENABLED"; + attribute GSR of FF_263 : label is "ENABLED"; + attribute GSR of FF_262 : label is "ENABLED"; + attribute GSR of FF_261 : label is "ENABLED"; + attribute GSR of FF_260 : label is "ENABLED"; + attribute GSR of FF_259 : label is "ENABLED"; + attribute GSR of FF_258 : label is "ENABLED"; + attribute GSR of FF_257 : label is "ENABLED"; + attribute GSR of FF_256 : label is "ENABLED"; + attribute GSR of FF_255 : label is "ENABLED"; + attribute GSR of FF_254 : label is "ENABLED"; + attribute GSR of FF_253 : label is "ENABLED"; + attribute GSR of FF_252 : label is "ENABLED"; + attribute GSR of FF_251 : label is "ENABLED"; + attribute GSR of FF_250 : label is "ENABLED"; + attribute GSR of FF_249 : label is "ENABLED"; + attribute GSR of FF_248 : label is "ENABLED"; + attribute GSR of FF_247 : label is "ENABLED"; + attribute GSR of FF_246 : label is "ENABLED"; + attribute GSR of FF_245 : label is "ENABLED"; + attribute GSR of FF_244 : label is "ENABLED"; + attribute GSR of FF_243 : label is "ENABLED"; + attribute GSR of FF_242 : label is "ENABLED"; + attribute GSR of FF_241 : label is "ENABLED"; + attribute GSR of FF_240 : label is "ENABLED"; + attribute GSR of FF_239 : label is "ENABLED"; + attribute GSR of FF_238 : label is "ENABLED"; + attribute GSR of FF_237 : label is "ENABLED"; + attribute GSR of FF_236 : label is "ENABLED"; + attribute GSR of FF_235 : label is "ENABLED"; + attribute GSR of FF_234 : label is "ENABLED"; + attribute GSR of FF_233 : label is "ENABLED"; + attribute GSR of FF_232 : label is "ENABLED"; + attribute GSR of FF_231 : label is "ENABLED"; + attribute GSR of FF_230 : label is "ENABLED"; + attribute GSR of FF_229 : label is "ENABLED"; + attribute GSR of FF_228 : label is "ENABLED"; + attribute GSR of FF_227 : label is "ENABLED"; + attribute GSR of FF_226 : label is "ENABLED"; + attribute GSR of FF_225 : label is "ENABLED"; + attribute GSR of FF_224 : label is "ENABLED"; + attribute GSR of FF_223 : label is "ENABLED"; + attribute GSR of FF_222 : label is "ENABLED"; + attribute GSR of FF_221 : label is "ENABLED"; + attribute GSR of FF_220 : label is "ENABLED"; + attribute GSR of FF_219 : label is "ENABLED"; + attribute GSR of FF_218 : label is "ENABLED"; + attribute GSR of FF_217 : label is "ENABLED"; + attribute GSR of FF_216 : label is "ENABLED"; + attribute GSR of FF_215 : label is "ENABLED"; + attribute GSR of FF_214 : label is "ENABLED"; + attribute GSR of FF_213 : label is "ENABLED"; + attribute GSR of FF_212 : label is "ENABLED"; + attribute GSR of FF_211 : label is "ENABLED"; + attribute GSR of FF_210 : label is "ENABLED"; + attribute GSR of FF_209 : label is "ENABLED"; + attribute GSR of FF_208 : label is "ENABLED"; + attribute GSR of FF_207 : label is "ENABLED"; + attribute GSR of FF_206 : label is "ENABLED"; + attribute GSR of FF_205 : label is "ENABLED"; + attribute GSR of FF_204 : label is "ENABLED"; + attribute GSR of FF_203 : label is "ENABLED"; + attribute GSR of FF_202 : label is "ENABLED"; + attribute GSR of FF_201 : label is "ENABLED"; + attribute GSR of FF_200 : label is "ENABLED"; + attribute GSR of FF_199 : label is "ENABLED"; + attribute GSR of FF_198 : label is "ENABLED"; + attribute GSR of FF_197 : label is "ENABLED"; + attribute GSR of FF_196 : label is "ENABLED"; + attribute GSR of FF_195 : label is "ENABLED"; + attribute GSR of FF_194 : label is "ENABLED"; + attribute GSR of FF_193 : label is "ENABLED"; + attribute GSR of FF_192 : label is "ENABLED"; + attribute GSR of FF_191 : label is "ENABLED"; + attribute GSR of FF_190 : label is "ENABLED"; + attribute GSR of FF_189 : label is "ENABLED"; + attribute GSR of FF_188 : label is "ENABLED"; + attribute GSR of FF_187 : label is "ENABLED"; + attribute GSR of FF_186 : label is "ENABLED"; + attribute GSR of FF_185 : label is "ENABLED"; + attribute GSR of FF_184 : label is "ENABLED"; + attribute GSR of FF_183 : label is "ENABLED"; + attribute GSR of FF_182 : label is "ENABLED"; + attribute GSR of FF_181 : label is "ENABLED"; + attribute GSR of FF_180 : label is "ENABLED"; + attribute GSR of FF_179 : label is "ENABLED"; + attribute GSR of FF_178 : label is "ENABLED"; + attribute GSR of FF_177 : label is "ENABLED"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + + FF_303 : FD1P3DX + port map (D => tsum(303), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(303)); + FF_302 : FD1P3DX + port map (D => tsum(302), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(302)); + FF_301 : FD1P3DX + port map (D => tsum(301), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(301)); + FF_300 : FD1P3DX + port map (D => tsum(300), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(300)); + FF_299 : FD1P3DX + port map (D => tsum(299), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(299)); + FF_298 : FD1P3DX + port map (D => tsum(298), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(298)); + FF_297 : FD1P3DX + port map (D => tsum(297), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(297)); + FF_296 : FD1P3DX + port map (D => tsum(296), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(296)); + FF_295 : FD1P3DX + port map (D => tsum(295), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(295)); + FF_294 : FD1P3DX + port map (D => tsum(294), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(294)); + FF_293 : FD1P3DX + port map (D => tsum(293), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(293)); + FF_292 : FD1P3DX + port map (D => tsum(292), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(292)); + FF_291 : FD1P3DX + port map (D => tsum(291), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(291)); + FF_290 : FD1P3DX + port map (D => tsum(290), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(290)); + FF_289 : FD1P3DX + port map (D => tsum(289), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(289)); + FF_288 : FD1P3DX + port map (D => tsum(288), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(288)); + FF_287 : FD1P3DX + port map (D => tsum(287), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(287)); + FF_286 : FD1P3DX + port map (D => tsum(286), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(286)); + FF_285 : FD1P3DX + port map (D => tsum(285), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(285)); + FF_284 : FD1P3DX + port map (D => tsum(284), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(284)); + FF_283 : FD1P3DX + port map (D => tsum(283), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(283)); + FF_282 : FD1P3DX + port map (D => tsum(282), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(282)); + FF_281 : FD1P3DX + port map (D => tsum(281), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(281)); + FF_280 : FD1P3DX + port map (D => tsum(280), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(280)); + FF_279 : FD1P3DX + port map (D => tsum(279), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(279)); + FF_278 : FD1P3DX + port map (D => tsum(278), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(278)); + FF_277 : FD1P3DX + port map (D => tsum(277), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(277)); + FF_276 : FD1P3DX + port map (D => tsum(276), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(276)); + FF_275 : FD1P3DX + port map (D => tsum(275), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(275)); + FF_274 : FD1P3DX + port map (D => tsum(274), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(274)); + FF_273 : FD1P3DX + port map (D => tsum(273), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(273)); + FF_272 : FD1P3DX + port map (D => tsum(272), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(272)); + FF_271 : FD1P3DX + port map (D => tsum(271), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(271)); + FF_270 : FD1P3DX + port map (D => tsum(270), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(270)); + FF_269 : FD1P3DX + port map (D => tsum(269), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(269)); + FF_268 : FD1P3DX + port map (D => tsum(268), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(268)); + FF_267 : FD1P3DX + port map (D => tsum(267), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(267)); + FF_266 : FD1P3DX + port map (D => tsum(266), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(266)); + FF_265 : FD1P3DX + port map (D => tsum(265), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(265)); + FF_264 : FD1P3DX + port map (D => tsum(264), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(264)); + FF_263 : FD1P3DX + port map (D => tsum(263), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(263)); + FF_262 : FD1P3DX + port map (D => tsum(262), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(262)); + FF_261 : FD1P3DX + port map (D => tsum(261), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(261)); + FF_260 : FD1P3DX + port map (D => tsum(260), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(260)); + FF_259 : FD1P3DX + port map (D => tsum(259), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(259)); + FF_258 : FD1P3DX + port map (D => tsum(258), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(258)); + FF_257 : FD1P3DX + port map (D => tsum(257), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(257)); + FF_256 : FD1P3DX + port map (D => tsum(256), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(256)); + FF_255 : FD1P3DX + port map (D => tsum(255), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(255)); + FF_254 : FD1P3DX + port map (D => tsum(254), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(254)); + FF_253 : FD1P3DX + port map (D => tsum(253), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(253)); + FF_252 : FD1P3DX + port map (D => tsum(252), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(252)); + FF_251 : FD1P3DX + port map (D => tsum(251), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(251)); + FF_250 : FD1P3DX + port map (D => tsum(250), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(250)); + FF_249 : FD1P3DX + port map (D => tsum(249), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(249)); + FF_248 : FD1P3DX + port map (D => tsum(248), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(248)); + FF_247 : FD1P3DX + port map (D => tsum(247), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(247)); + FF_246 : FD1P3DX + port map (D => tsum(246), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(246)); + FF_245 : FD1P3DX + port map (D => tsum(245), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(245)); + FF_244 : FD1P3DX + port map (D => tsum(244), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(244)); + FF_243 : FD1P3DX + port map (D => tsum(243), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(243)); + FF_242 : FD1P3DX + port map (D => tsum(242), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(242)); + FF_241 : FD1P3DX + port map (D => tsum(241), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(241)); + FF_240 : FD1P3DX + port map (D => tsum(240), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(240)); + FF_239 : FD1P3DX + port map (D => tsum(239), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(239)); + FF_238 : FD1P3DX + port map (D => tsum(238), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(238)); + FF_237 : FD1P3DX + port map (D => tsum(237), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(237)); + FF_236 : FD1P3DX + port map (D => tsum(236), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(236)); + FF_235 : FD1P3DX + port map (D => tsum(235), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(235)); + FF_234 : FD1P3DX + port map (D => tsum(234), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(234)); + FF_233 : FD1P3DX + port map (D => tsum(233), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(233)); + FF_232 : FD1P3DX + port map (D => tsum(232), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(232)); + FF_231 : FD1P3DX + port map (D => tsum(231), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(231)); + FF_230 : FD1P3DX + port map (D => tsum(230), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(230)); + FF_229 : FD1P3DX + port map (D => tsum(229), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(229)); + FF_228 : FD1P3DX + port map (D => tsum(228), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(228)); + FF_227 : FD1P3DX + port map (D => tsum(227), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(227)); + FF_226 : FD1P3DX + port map (D => tsum(226), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(226)); + FF_225 : FD1P3DX + port map (D => tsum(225), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(225)); + FF_224 : FD1P3DX + port map (D => tsum(224), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(224)); + FF_223 : FD1P3DX + port map (D => tsum(223), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(223)); + FF_222 : FD1P3DX + port map (D => tsum(222), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(222)); + FF_221 : FD1P3DX + port map (D => tsum(221), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(221)); + FF_220 : FD1P3DX + port map (D => tsum(220), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(220)); + FF_219 : FD1P3DX + port map (D => tsum(219), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(219)); + FF_218 : FD1P3DX + port map (D => tsum(218), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(218)); + FF_217 : FD1P3DX + port map (D => tsum(217), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(217)); + FF_216 : FD1P3DX + port map (D => tsum(216), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(216)); + FF_215 : FD1P3DX + port map (D => tsum(215), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(215)); + FF_214 : FD1P3DX + port map (D => tsum(214), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(214)); + FF_213 : FD1P3DX + port map (D => tsum(213), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(213)); + FF_212 : FD1P3DX + port map (D => tsum(212), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(212)); + FF_211 : FD1P3DX + port map (D => tsum(211), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(211)); + FF_210 : FD1P3DX + port map (D => tsum(210), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(210)); + FF_209 : FD1P3DX + port map (D => tsum(209), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(209)); + FF_208 : FD1P3DX + port map (D => tsum(208), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(208)); + FF_207 : FD1P3DX + port map (D => tsum(207), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(207)); + FF_206 : FD1P3DX + port map (D => tsum(206), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(206)); + FF_205 : FD1P3DX + port map (D => tsum(205), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(205)); + FF_204 : FD1P3DX + port map (D => tsum(204), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(204)); + FF_203 : FD1P3DX + port map (D => tsum(203), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(203)); + FF_202 : FD1P3DX + port map (D => tsum(202), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(202)); + FF_201 : FD1P3DX + port map (D => tsum(201), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(201)); + FF_200 : FD1P3DX + port map (D => tsum(200), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(200)); + FF_199 : FD1P3DX + port map (D => tsum(199), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(199)); + FF_198 : FD1P3DX + port map (D => tsum(198), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(198)); + FF_197 : FD1P3DX + port map (D => tsum(197), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(197)); + FF_196 : FD1P3DX + port map (D => tsum(196), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(196)); + FF_195 : FD1P3DX + port map (D => tsum(195), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(195)); + FF_194 : FD1P3DX + port map (D => tsum(194), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(194)); + FF_193 : FD1P3DX + port map (D => tsum(193), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(193)); + FF_192 : FD1P3DX + port map (D => tsum(192), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(192)); + FF_191 : FD1P3DX + port map (D => tsum(191), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(191)); + FF_190 : FD1P3DX + port map (D => tsum(190), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(190)); + FF_189 : FD1P3DX + port map (D => tsum(189), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(189)); + FF_188 : FD1P3DX + port map (D => tsum(188), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(188)); + FF_187 : FD1P3DX + port map (D => tsum(187), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(187)); + FF_186 : FD1P3DX + port map (D => tsum(186), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(186)); + FF_185 : FD1P3DX + port map (D => tsum(185), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(185)); + FF_184 : FD1P3DX + port map (D => tsum(184), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(184)); + FF_183 : FD1P3DX + port map (D => tsum(183), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(183)); + FF_182 : FD1P3DX + port map (D => tsum(182), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(182)); + FF_181 : FD1P3DX + port map (D => tsum(181), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(181)); + FF_180 : FD1P3DX + port map (D => tsum(180), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(180)); + FF_179 : FD1P3DX + port map (D => tsum(179), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(179)); + FF_178 : FD1P3DX + port map (D => tsum(178), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(178)); + FF_177 : FD1P3DX + port map (D => tsum(177), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(177)); + FF_176 : FD1P3DX + port map (D => tsum(176), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(176)); + FF_175 : FD1P3DX + port map (D => tsum(175), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(175)); + FF_174 : FD1P3DX + port map (D => tsum(174), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(174)); + FF_173 : FD1P3DX + port map (D => tsum(173), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(173)); + FF_172 : FD1P3DX + port map (D => tsum(172), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(172)); + FF_171 : FD1P3DX + port map (D => tsum(171), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(171)); + FF_170 : FD1P3DX + port map (D => tsum(170), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(170)); + FF_169 : FD1P3DX + port map (D => tsum(169), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(169)); + FF_168 : FD1P3DX + port map (D => tsum(168), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(168)); + FF_167 : FD1P3DX + port map (D => tsum(167), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(167)); + FF_166 : FD1P3DX + port map (D => tsum(166), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(166)); + FF_165 : FD1P3DX + port map (D => tsum(165), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(165)); + FF_164 : FD1P3DX + port map (D => tsum(164), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(164)); + FF_163 : FD1P3DX + port map (D => tsum(163), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(163)); + FF_162 : FD1P3DX + port map (D => tsum(162), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(162)); + FF_161 : FD1P3DX + port map (D => tsum(161), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(161)); + FF_160 : FD1P3DX + port map (D => tsum(160), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(160)); + FF_159 : FD1P3DX + port map (D => tsum(159), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(159)); + FF_158 : FD1P3DX + port map (D => tsum(158), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(158)); + FF_157 : FD1P3DX + port map (D => tsum(157), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(157)); + FF_156 : FD1P3DX + port map (D => tsum(156), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(156)); + FF_155 : FD1P3DX + port map (D => tsum(155), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(155)); + FF_154 : FD1P3DX + port map (D => tsum(154), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(154)); + FF_153 : FD1P3DX + port map (D => tsum(153), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(153)); + FF_152 : FD1P3DX + port map (D => tsum(152), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(152)); + FF_151 : FD1P3DX + port map (D => tsum(151), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(151)); + FF_150 : FD1P3DX + port map (D => tsum(150), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(150)); + FF_149 : FD1P3DX + port map (D => tsum(149), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(149)); + FF_148 : FD1P3DX + port map (D => tsum(148), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(148)); + FF_147 : FD1P3DX + port map (D => tsum(147), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(147)); + FF_146 : FD1P3DX + port map (D => tsum(146), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(146)); + FF_145 : FD1P3DX + port map (D => tsum(145), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(145)); + FF_144 : FD1P3DX + port map (D => tsum(144), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(144)); + FF_143 : FD1P3DX + port map (D => tsum(143), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(143)); + FF_142 : FD1P3DX + port map (D => tsum(142), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(142)); + FF_141 : FD1P3DX + port map (D => tsum(141), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(141)); + FF_140 : FD1P3DX + port map (D => tsum(140), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(140)); + FF_139 : FD1P3DX + port map (D => tsum(139), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(139)); + FF_138 : FD1P3DX + port map (D => tsum(138), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(138)); + FF_137 : FD1P3DX + port map (D => tsum(137), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(137)); + FF_136 : FD1P3DX + port map (D => tsum(136), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(136)); + FF_135 : FD1P3DX + port map (D => tsum(135), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(135)); + FF_134 : FD1P3DX + port map (D => tsum(134), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(134)); + FF_133 : FD1P3DX + port map (D => tsum(133), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(133)); + FF_132 : FD1P3DX + port map (D => tsum(132), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(132)); + FF_131 : FD1P3DX + port map (D => tsum(131), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(131)); + FF_130 : FD1P3DX + port map (D => tsum(130), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(130)); + FF_129 : FD1P3DX + port map (D => tsum(129), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(129)); + FF_128 : FD1P3DX + port map (D => tsum(128), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(128)); + FF_127 : FD1P3DX + port map (D => tsum(127), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(127)); + FF_126 : FD1P3DX + port map (D => tsum(126), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(126)); + FF_125 : FD1P3DX + port map (D => tsum(125), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(125)); + FF_124 : FD1P3DX + port map (D => tsum(124), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(124)); + FF_123 : FD1P3DX + port map (D => tsum(123), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(123)); + FF_122 : FD1P3DX + port map (D => tsum(122), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(122)); + FF_121 : FD1P3DX + port map (D => tsum(121), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(121)); + FF_120 : FD1P3DX + port map (D => tsum(120), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(120)); + FF_119 : FD1P3DX + port map (D => tsum(119), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(119)); + FF_118 : FD1P3DX + port map (D => tsum(118), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(118)); + FF_117 : FD1P3DX + port map (D => tsum(117), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(117)); + FF_116 : FD1P3DX + port map (D => tsum(116), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(116)); + FF_115 : FD1P3DX + port map (D => tsum(115), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(115)); + FF_114 : FD1P3DX + port map (D => tsum(114), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(114)); + FF_113 : FD1P3DX + port map (D => tsum(113), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(113)); + FF_112 : FD1P3DX + port map (D => tsum(112), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(112)); + FF_111 : FD1P3DX + port map (D => tsum(111), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(111)); + FF_110 : FD1P3DX + port map (D => tsum(110), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(110)); + FF_109 : FD1P3DX + port map (D => tsum(109), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(109)); + FF_108 : FD1P3DX + port map (D => tsum(108), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(108)); + FF_107 : FD1P3DX + port map (D => tsum(107), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(107)); + FF_106 : FD1P3DX + port map (D => tsum(106), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(106)); + FF_105 : FD1P3DX + port map (D => tsum(105), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(105)); + FF_104 : FD1P3DX + port map (D => tsum(104), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(104)); + FF_103 : FD1P3DX + port map (D => tsum(103), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(103)); + FF_102 : FD1P3DX + port map (D => tsum(102), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(102)); + FF_101 : FD1P3DX + port map (D => tsum(101), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(101)); + FF_100 : FD1P3DX + port map (D => tsum(100), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(100)); + FF_99 : FD1P3DX + port map (D => tsum(99), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(99)); + FF_98 : FD1P3DX + port map (D => tsum(98), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(98)); + FF_97 : FD1P3DX + port map (D => tsum(97), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(97)); + FF_96 : FD1P3DX + port map (D => tsum(96), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(96)); + FF_95 : FD1P3DX + port map (D => tsum(95), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(95)); + FF_94 : FD1P3DX + port map (D => tsum(94), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(94)); + FF_93 : FD1P3DX + port map (D => tsum(93), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(93)); + FF_92 : FD1P3DX + port map (D => tsum(92), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(92)); + FF_91 : FD1P3DX + port map (D => tsum(91), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(91)); + FF_90 : FD1P3DX + port map (D => tsum(90), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(90)); + FF_89 : FD1P3DX + port map (D => tsum(89), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(89)); + FF_88 : FD1P3DX + port map (D => tsum(88), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(88)); + FF_87 : FD1P3DX + port map (D => tsum(87), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(87)); + FF_86 : FD1P3DX + port map (D => tsum(86), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(86)); + FF_85 : FD1P3DX + port map (D => tsum(85), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(85)); + FF_84 : FD1P3DX + port map (D => tsum(84), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(84)); + FF_83 : FD1P3DX + port map (D => tsum(83), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(83)); + FF_82 : FD1P3DX + port map (D => tsum(82), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(82)); + FF_81 : FD1P3DX + port map (D => tsum(81), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(81)); + FF_80 : FD1P3DX + port map (D => tsum(80), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(80)); + FF_79 : FD1P3DX + port map (D => tsum(79), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(79)); + FF_78 : FD1P3DX + port map (D => tsum(78), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(78)); + FF_77 : FD1P3DX + port map (D => tsum(77), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(77)); + FF_76 : FD1P3DX + port map (D => tsum(76), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(76)); + FF_75 : FD1P3DX + port map (D => tsum(75), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(75)); + FF_74 : FD1P3DX + port map (D => tsum(74), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(74)); + FF_73 : FD1P3DX + port map (D => tsum(73), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(73)); + FF_72 : FD1P3DX + port map (D => tsum(72), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(72)); + FF_71 : FD1P3DX + port map (D => tsum(71), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(71)); + FF_70 : FD1P3DX + port map (D => tsum(70), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(70)); + FF_69 : FD1P3DX + port map (D => tsum(69), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(69)); + FF_68 : FD1P3DX + port map (D => tsum(68), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(68)); + FF_67 : FD1P3DX + port map (D => tsum(67), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(67)); + FF_66 : FD1P3DX + port map (D => tsum(66), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(66)); + FF_65 : FD1P3DX + port map (D => tsum(65), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(65)); + FF_64 : FD1P3DX + port map (D => tsum(64), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(64)); + FF_63 : FD1P3DX + port map (D => tsum(63), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(63)); + FF_62 : FD1P3DX + port map (D => tsum(62), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(62)); + FF_61 : FD1P3DX + port map (D => tsum(61), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(61)); + FF_60 : FD1P3DX + port map (D => tsum(60), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(60)); + FF_59 : FD1P3DX + port map (D => tsum(59), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(59)); + FF_58 : FD1P3DX + port map (D => tsum(58), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(58)); + FF_57 : FD1P3DX + port map (D => tsum(57), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(57)); + FF_56 : FD1P3DX + port map (D => tsum(56), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(56)); + FF_55 : FD1P3DX + port map (D => tsum(55), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(55)); + FF_54 : FD1P3DX + port map (D => tsum(54), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(54)); + FF_53 : FD1P3DX + port map (D => tsum(53), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(53)); + FF_52 : FD1P3DX + port map (D => tsum(52), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(52)); + FF_51 : FD1P3DX + port map (D => tsum(51), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(51)); + FF_50 : FD1P3DX + port map (D => tsum(50), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(50)); + FF_49 : FD1P3DX + port map (D => tsum(49), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(49)); + FF_48 : FD1P3DX + port map (D => tsum(48), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(48)); + FF_47 : FD1P3DX + port map (D => tsum(47), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(47)); + FF_46 : FD1P3DX + port map (D => tsum(46), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(46)); + FF_45 : FD1P3DX + port map (D => tsum(45), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(45)); + FF_44 : FD1P3DX + port map (D => tsum(44), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(44)); + FF_43 : FD1P3DX + port map (D => tsum(43), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(43)); + FF_42 : FD1P3DX + port map (D => tsum(42), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(42)); + FF_41 : FD1P3DX + port map (D => tsum(41), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(41)); + FF_40 : FD1P3DX + port map (D => tsum(40), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(40)); + FF_39 : FD1P3DX + port map (D => tsum(39), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(39)); + FF_38 : FD1P3DX + port map (D => tsum(38), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(38)); + FF_37 : FD1P3DX + port map (D => tsum(37), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(37)); + FF_36 : FD1P3DX + port map (D => tsum(36), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(36)); + FF_35 : FD1P3DX + port map (D => tsum(35), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(35)); + FF_34 : FD1P3DX + port map (D => tsum(34), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(34)); + FF_33 : FD1P3DX + port map (D => tsum(33), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(33)); + FF_32 : FD1P3DX + port map (D => tsum(32), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(32)); + FF_31 : FD1P3DX + port map (D => tsum(31), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(31)); + FF_30 : FD1P3DX + port map (D => tsum(30), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(30)); + FF_29 : FD1P3DX + port map (D => tsum(29), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(29)); + FF_28 : FD1P3DX + port map (D => tsum(28), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(28)); + FF_27 : FD1P3DX + port map (D => tsum(27), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(27)); + FF_26 : FD1P3DX + port map (D => tsum(26), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(26)); + FF_25 : FD1P3DX + port map (D => tsum(25), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(25)); + FF_24 : FD1P3DX + port map (D => tsum(24), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(24)); + FF_23 : FD1P3DX + port map (D => tsum(23), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(23)); + FF_22 : FD1P3DX + port map (D => tsum(22), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(22)); + FF_21 : FD1P3DX + port map (D => tsum(21), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(21)); + FF_20 : FD1P3DX + port map (D => tsum(20), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(20)); + FF_19 : FD1P3DX + port map (D => tsum(19), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(19)); + FF_18 : FD1P3DX + port map (D => tsum(18), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(18)); + FF_17 : FD1P3DX + port map (D => tsum(17), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(17)); + FF_16 : FD1P3DX + port map (D => tsum(16), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(16)); + FF_15 : FD1P3DX + port map (D => tsum(15), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(15)); + FF_14 : FD1P3DX + port map (D => tsum(14), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(14)); + FF_13 : FD1P3DX + port map (D => tsum(13), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(13)); + FF_12 : FD1P3DX + port map (D => tsum(12), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(12)); + FF_11 : FD1P3DX + port map (D => tsum(11), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(11)); + FF_10 : FD1P3DX + port map (D => tsum(10), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(10)); + FF_9 : FD1P3DX + port map (D => tsum(9), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(9)); + FF_8 : FD1P3DX + port map (D => tsum(8), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(8)); + FF_7 : FD1P3DX + port map (D => tsum(7), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(7)); + FF_6 : FD1P3DX + port map (D => tsum(6), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(6)); + FF_5 : FD1P3DX + port map (D => tsum(5), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(5)); + FF_4 : FD1P3DX + port map (D => tsum(4), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(4)); + FF_3 : FD1P3DX + port map (D => tsum(3), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(3)); + FF_2 : FD1P3DX + port map (D => tsum(2), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(2)); + FF_1 : FD1P3DX + port map (D => tsum(1), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(1)); + FF_0 : FD1P3DX + port map (D => tsum(0), SP => CLKEn, CK => CLK, CD => Reset, + Q => r0_sum(0)); + + GEN_0_ADD : FADD2B + port map (A0 => DataA(0), + A1 => DataA(1), + B0 => DataB(0), + B1 => DataB(1), + CI => scuba_vlo, + COUT => co(0), + S0 => tsum(0), + S1 => tsum(1)); + + GEN : for i in 1 to 151 generate + ADD : FADD2B + port map (A0 => DataA(2*i), + A1 => DataA(2*i+1), + B0 => DataB(2*i), + B1 => DataB(2*i+1), + CI => co(i-1), + COUT => co(i), + S0 => tsum(2*i), + S1 => tsum(2*i+1)); + end generate GEN; + + scuba_vlo_inst : VLO + port map (Z => scuba_vlo); + + Result <= r0_sum; + +end Structure; + + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of adder_304 is + for Structure + for all : FADD2B use entity ecp3.FADD2B(V); end for; + for all : FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all : VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; +-- synopsys translate_on diff --git a/tdc_releases/tdc_v1.6/BusHandler.vhd b/tdc_releases/tdc_v1.6/BusHandler.vhd new file mode 100644 index 0000000..932cfe8 --- /dev/null +++ b/tdc_releases/tdc_v1.6/BusHandler.vhd @@ -0,0 +1,89 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + +entity BusHandler is + generic ( + BUS_LENGTH : integer range 0 to 64 := 2); + port ( + RESET : in std_logic; + CLK : in std_logic; +-- + DATA_IN : in std_logic_vector_array_32(0 to BUS_LENGTH); + READ_EN_IN : in std_logic; + WRITE_EN_IN : in std_logic; + ADDR_IN : in std_logic_vector(6 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATAREADY_OUT : out std_logic; + UNKNOWN_ADDR_OUT : out std_logic); +end BusHandler; + +architecture Behavioral of BusHandler is + + --Output signals + signal data_out_reg : std_logic_vector(31 downto 0); + signal data_ready_reg : std_logic; + signal unknown_addr_reg : std_logic; + signal read_en_i : std_logic; + signal write_en_i : std_logic; + signal addr_i : std_logic_vector(6 downto 0); + +begin + + read_en_i <= READ_EN_IN when rising_edge(CLK); + write_en_i <= WRITE_EN_IN when rising_edge(CLK); + addr_i <= ADDR_IN when rising_edge(CLK); + + READ_WRITE_RESPONSE : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + data_out_reg <= (others => '0'); + data_ready_reg <= '0'; + unknown_addr_reg <= '0'; + elsif read_en_i = '1' then + if to_integer(unsigned(addr_i)) > BUS_LENGTH then -- if bigger than 64 + data_out_reg <= (others => '0'); + data_ready_reg <= '0'; + unknown_addr_reg <= '1'; + else + data_out_reg <= DATA_IN(to_integer(unsigned(addr_i))); + data_ready_reg <= '1'; + unknown_addr_reg <= '0'; + end if; + elsif write_en_i = '1' then + data_out_reg <= (others => '0'); + data_ready_reg <= '0'; + unknown_addr_reg <= '1'; + else + data_out_reg <= (others => '0'); + data_ready_reg <= '0'; + unknown_addr_reg <= '0'; + end if; + end if; + end process READ_WRITE_RESPONSE; + + + --FifoWriteSignal : process (CLK) + --begin + -- if rising_edge(CLK) then + -- if RESET = '1' then + -- unknown_addr_reg <= '0'; + -- else + -- unknown_addr_reg <= '1'; + -- end if; + -- end if; + --end process FifoWriteSignal; + + DATA_OUT <= data_out_reg; + DATAREADY_OUT <= data_ready_reg; + UNKNOWN_ADDR_OUT <= unknown_addr_reg; + +end Behavioral; + diff --git a/tdc_releases/tdc_v1.6/Channel.vhd b/tdc_releases/tdc_v1.6/Channel.vhd new file mode 100644 index 0000000..c4c95b3 --- /dev/null +++ b/tdc_releases/tdc_v1.6/Channel.vhd @@ -0,0 +1,336 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; + +entity Channel is + + generic ( + CHANNEL_ID : integer range 0 to 64; + DEBUG : integer range 0 to 1; + SIMULATION : integer range 0 to 1; + REFERENCE : integer range 0 to 1); + port ( + RESET_200 : in std_logic; + RESET_100 : in std_logic; + RESET_COUNTERS : in std_logic; + CLK_200 : in std_logic; + CLK_100 : in std_logic; +-- + HIT_IN : in std_logic; + TRIGGER_WIN_END_TDC : in std_logic; + TRIGGER_WIN_END_RDO : in std_logic; + READ_EN_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(35 downto 0); + FIFO_DATA_VALID_OUT : out std_logic; + FIFO_EMPTY_OUT : out std_logic; + FIFO_FULL_OUT : out std_logic; + FIFO_ALMOST_EMPTY_OUT : out std_logic; + FIFO_ALMOST_FULL_OUT : out std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); +-- + VALID_TIMING_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; +-- + EPOCH_WRITE_EN_IN : in std_logic; + LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); + HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0); + ENCODER_START_NUMBER : out std_logic_vector(23 downto 0); + ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0); + FIFO_WRITE_NUMBER : out std_logic_vector(23 downto 0); +-- + Channel_200_DEBUG : out std_logic_vector(31 downto 0); + Channel_DEBUG : out std_logic_vector(31 downto 0) + ); + +end Channel; + +architecture Channel of Channel is +------------------------------------------------------------------------------- +-- Signal Declarations +------------------------------------------------------------------------------- + + -- hit signals + signal hit_in_i : std_logic; + signal hit_buf : std_logic; + + -- time stamp + signal coarse_cntr_reg : std_logic_vector(10 downto 0); + signal trig_win_end_tdc_i : std_logic; + signal trig_win_end_rdo_i : std_logic; + + -- from channel + signal ch_data_i : std_logic_vector(35 downto 0); + signal ch_data_valid_i : std_logic; + signal ch_empty_i : std_logic; + signal ch_full_i : std_logic; + signal ch_almost_full_i : std_logic; + + -- from buffer + signal buf_data_i : std_logic_vector(35 downto 0); + signal buf_data_valid_i : std_logic; + signal buf_empty_i : std_logic; + signal buf_empty_reg : std_logic; + signal buf_full_i : std_logic; + signal buf_almost_empty_i : std_logic; + signal buf_almost_full_i : std_logic; + + -- fron readout + signal rd_en_reg : std_logic; + + -- debug + signal sync_q : std_logic_vector(2 downto 0); + signal hit_pulse : std_logic; + signal hit_pulse_100 : std_logic; + signal encoder_finished_i : std_logic; + signal encoder_finished_100 : std_logic; + signal encoder_start_i : std_logic; + signal encoder_start_100 : std_logic; + signal fifo_write_i : std_logic; + signal fifo_write_100 : std_logic; + signal lost_hit_cntr : unsigned(23 downto 0); + signal hit_detect_cntr : unsigned(23 downto 0); + signal encoder_start_cntr : unsigned(23 downto 0); + signal encoder_finished_cntr : unsigned(23 downto 0); + signal fifo_write_cntr : unsigned(23 downto 0); + signal channel_200_debug_i : std_logic_vector(31 downto 0); + + -- other + +-- signal data_finished_i : std_logic; + +------------------------------------------------------------------------------- + + attribute syn_keep : boolean; + attribute syn_keep of hit_buf : signal is true; + attribute syn_keep of trig_win_end_tdc_i : signal is true; + attribute syn_keep of trig_win_end_rdo_i : signal is true; + attribute syn_preserve : boolean; + attribute syn_preserve of coarse_cntr_reg : signal is true; + attribute syn_preserve of hit_buf : signal is true; + attribute syn_preserve of trig_win_end_tdc_i : signal is true; + attribute nomerge : string; + attribute nomerge of hit_buf : signal is "true"; + attribute nomerge of trig_win_end_tdc_i : signal is "true"; + attribute nomerge of trig_win_end_rdo_i : signal is "true"; + + +------------------------------------------------------------------------------- + +begin + + hit_in_i <= HIT_IN; + hit_buf <= not hit_in_i; + + Channel200 : Channel_200 + generic map ( + CHANNEL_ID => CHANNEL_ID, + SIMULATION => SIMULATION, + REFERENCE => REFERENCE) + port map ( + CLK_200 => CLK_200, + RESET_200 => RESET_200, + CLK_100 => CLK_100, + RESET_100 => RESET_100, + HIT_IN => hit_buf, + TRIGGER_WIN_END_TDC => trig_win_end_tdc_i, + TRIGGER_WIN_END_RDO => trig_win_end_rdo_i, + EPOCH_COUNTER_IN => EPOCH_COUNTER_IN, + COARSE_COUNTER_IN => coarse_cntr_reg, + READ_EN_IN => READ_EN_IN, + FIFO_DATA_OUT => ch_data_i, + FIFO_DATA_VALID_OUT => ch_data_valid_i, + FIFO_EMPTY_OUT => ch_empty_i, + FIFO_FULL_OUT => ch_full_i, + FIFO_ALMOST_FULL_OUT => ch_almost_full_i, + VALID_TIMING_TRG_IN => VALID_TIMING_TRG_IN, + SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, + MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, + EPOCH_WRITE_EN_IN => EPOCH_WRITE_EN_IN, + ENCODER_START_OUT => encoder_start_i, + ENCODER_FINISHED_OUT => encoder_finished_i, + FIFO_WRITE_OUT => fifo_write_i, + CHANNEL_200_DEBUG => channel_200_debug_i); + + The_Buffer : FIFO_36x128_OutReg + port map ( + Data => ch_data_i, + Clock => CLK_100, + WrEn => ch_data_valid_i, + RdEn => READ_EN_IN, + Reset => RESET_100, + Q => buf_data_i, + Empty => buf_empty_i, + Full => buf_full_i, + AlmostEmpty => buf_almost_empty_i); + + FIFO_DATA_OUT <= buf_data_i; + FIFO_DATA_VALID_OUT <= buf_data_valid_i; + FIFO_EMPTY_OUT <= buf_empty_i; + FIFO_ALMOST_EMPTY_OUT <= buf_almost_empty_i; + trig_win_end_tdc_i <= TRIGGER_WIN_END_TDC when rising_edge(CLK_200); + trig_win_end_rdo_i <= TRIGGER_WIN_END_RDO when rising_edge(CLK_100); + rd_en_reg <= READ_EN_IN when rising_edge(CLK_100); + buf_empty_reg <= buf_empty_i when rising_edge(CLK_100); + buf_data_valid_i <= rd_en_reg and not buf_empty_reg when rising_edge(CLK_100); + + pulse_sync_encoder_start : pulse_sync + port map ( + CLK_A_IN => CLK_200, + RESET_A_IN => RESET_200, + PULSE_A_IN => encoder_start_i, + CLK_B_IN => CLK_100, + RESET_B_IN => RESET_100, + PULSE_B_OUT => encoder_start_100); + + pulse_sync_encoder_finished : pulse_sync + port map ( + CLK_A_IN => CLK_200, + RESET_A_IN => RESET_200, + PULSE_A_IN => encoder_finished_i, + CLK_B_IN => CLK_100, + RESET_B_IN => RESET_100, + PULSE_B_OUT => encoder_finished_100); + + pulse_sync_fifo_write : pulse_sync + port map ( + CLK_A_IN => CLK_200, + RESET_A_IN => RESET_200, + PULSE_A_IN => fifo_write_i, + CLK_B_IN => CLK_100, + RESET_B_IN => RESET_100, + PULSE_B_OUT => fifo_write_100); + + CoarseCounter : ShiftRegisterSISO + generic map ( + DEPTH => 1, + WIDTH => 11) + port map ( + CLK => CLK_200, + D_IN => COARSE_COUNTER_IN, + D_OUT => coarse_cntr_reg); + +------------------------------------------------------------------------------- +-- DEBUG Counters +------------------------------------------------------------------------------- + gen_DEBUG : if DEBUG = c_YES generate + --purpose: Hit Signal Synchroniser + sync_q(0) <= HIT_IN when rising_edge(CLK_200); + sync_q(1) <= sync_q(0) when rising_edge(CLK_200); + sync_q(2) <= sync_q(1) when rising_edge(CLK_200); + + risingEdgeDetect_1 : risingEdgeDetect + port map ( + CLK => CLK_200, + SIGNAL_IN => sync_q(2), + PULSE_OUT => hit_pulse); + + pulse_sync_hit : pulse_sync + port map ( + CLK_A_IN => CLK_200, + RESET_A_IN => RESET_200, + PULSE_A_IN => hit_pulse, + CLK_B_IN => CLK_100, + RESET_B_IN => RESET_100, + PULSE_B_OUT => hit_pulse_100); + + --purpose: Counts the detected but unwritten hits + Lost_Hit_Counter : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + lost_hit_cntr <= (others => '0'); + elsif hit_pulse_100 = '1' then + lost_hit_cntr <= lost_hit_cntr + to_unsigned(1, 1); + elsif fifo_write_100 = '1' then + lost_hit_cntr <= lost_hit_cntr - to_unsigned(1, 1); + end if; + end if; + end process Lost_Hit_Counter; + + LOST_HIT_NUMBER <= std_logic_vector(lost_hit_cntr) when rising_edge(CLK_100); + + --purpose: Counts the detected hits + Hit_Detect_Counter : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + hit_detect_cntr <= (others => '0'); + elsif hit_pulse_100 = '1' then + hit_detect_cntr <= hit_detect_cntr + to_unsigned(1, 1); + end if; + end if; + end process Hit_Detect_Counter; + + HIT_DETECT_NUMBER <= std_logic_vector(hit_detect_cntr) when rising_edge(CLK_100); + + --purpose: Counts the encoder start times + Encoder_Start_Counter : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + encoder_start_cntr <= (others => '0'); + elsif encoder_start_100 = '1' then + encoder_start_cntr <= encoder_start_cntr + to_unsigned(1, 1); + end if; + end if; + end process Encoder_Start_Counter; + + ENCODER_START_NUMBER <= std_logic_vector(encoder_start_cntr) when rising_edge(CLK_100); + + --purpose: Counts the encoder finished signals + ENCODER_FINISHED_Counter : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + encoder_finished_cntr <= (others => '0'); + elsif encoder_finished_100 = '1' then + encoder_finished_cntr <= encoder_finished_cntr + to_unsigned(1, 1); + end if; + end if; + end process ENCODER_FINISHED_Counter; + + ENCODER_FINISHED_NUMBER <= std_logic_vector(encoder_finished_cntr) when rising_edge(CLK_100); + + --purpose: Counts the written hits + FIFO_WRITE_Counter : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + fifo_write_cntr <= (others => '0'); + elsif fifo_write_100 = '1' then + fifo_write_cntr <= fifo_write_cntr + to_unsigned(1, 1); + end if; + end if; + end process FIFO_WRITE_Counter; + + FIFO_WRITE_NUMBER <= std_logic_vector(fifo_write_cntr) when rising_edge(CLK_100); + end generate gen_DEBUG; + +------------------------------------------------------------------------------- +-- DEBUG +------------------------------------------------------------------------------- + Channel_DEBUG(7 downto 0) <= buf_data_i(35 downto 28); + Channel_DEBUG(8) <= buf_data_valid_i; + Channel_DEBUG(9) <= READ_EN_IN; + + + Channel_200_DEBUG <= channel_200_debug_i; + --Channel_DEBUG(0) <= fifo_write_100 when rising_edge(CLK_100); + --Channel_DEBUG(1) <= result_2_reg; + --Channel_DEBUG(2) <= hit_detect_i; + --Channel_DEBUG(3) <= hit_detect_reg; + --Channel_DEBUG(4) <= '0'; + --Channel_DEBUG(5) <= ff_array_en_i; + --Channel_DEBUG(6) <= encoder_start_i; + --Channel_DEBUG(7) <= encoder_finished_i; + --Channel_DEBUG(15 downto 8) <= result_i(7 downto 0); + --Channel_DEBUG(31 downto 16) <= (others => '0'); + +end Channel; diff --git a/tdc_releases/tdc_v1.6/Channel_200.vhd b/tdc_releases/tdc_v1.6/Channel_200.vhd new file mode 100644 index 0000000..a60bd9c --- /dev/null +++ b/tdc_releases/tdc_v1.6/Channel_200.vhd @@ -0,0 +1,739 @@ +------------------------------------------------------------------------------- +-- Title : Channel 200 MHz Part +-- Project : +------------------------------------------------------------------------------- +-- File : Channel_200.vhd +-- Author : c.ugur@gsi.de +-- Created : 2012-08-28 +-- Last update: 2014-01-20 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; + +entity Channel_200 is + + generic ( + CHANNEL_ID : integer range 0 to 64; + SIMULATION : integer range 0 to 1; + REFERENCE : integer range 0 to 1); + port ( + CLK_200 : in std_logic; -- 200 MHz clk + RESET_200 : in std_logic; -- reset sync with 200Mhz clk + CLK_100 : in std_logic; -- 100 MHz clk + RESET_100 : in std_logic; -- reset sync with 100Mhz clk +-- + HIT_IN : in std_logic; -- hit in + TRIGGER_WIN_END_TDC : in std_logic; -- trigger window end strobe + TRIGGER_WIN_END_RDO : in std_logic; -- trigger window end strobe + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); -- system coarse counter + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + READ_EN_IN : in std_logic; -- read en signal + FIFO_DATA_OUT : out std_logic_vector(35 downto 0); -- fifo data out + FIFO_DATA_VALID_OUT : out std_logic; -- fifo data valid signal + FIFO_EMPTY_OUT : out std_logic; -- fifo empty signal + FIFO_FULL_OUT : out std_logic; -- fifo full signal + FIFO_ALMOST_FULL_OUT : out std_logic; +-- + VALID_TIMING_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; +-- + EPOCH_WRITE_EN_IN : in std_logic; + ENCODER_START_OUT : out std_logic; + ENCODER_FINISHED_OUT : out std_logic; + FIFO_WRITE_OUT : out std_logic; + CHANNEL_200_DEBUG : out std_logic_vector(31 downto 0) + ); + +end Channel_200; + +architecture Channel_200 of Channel_200 is + + -- carry chain + signal data_a_i : std_logic_vector(303 downto 0); + signal data_b_i : std_logic_vector(303 downto 0); + signal result_i : std_logic_vector(303 downto 0); + signal ff_array_en_i : std_logic; + signal hit_i : std_logic; + + -- hit detection + signal result_2_reg : std_logic := '0'; + signal hit_detect_i : std_logic := '0'; + signal hit_detect_reg : std_logic; + signal hit_detect_2reg : std_logic; + + -- time stamp + signal time_stamp_i : std_logic_vector(10 downto 0); + signal coarse_cntr_reg : std_logic_vector(10 downto 0); + + -- encoder + signal encoder_start_i : std_logic; + signal encoder_finished_i : std_logic; + signal encoder_data_out_i : std_logic_vector(9 downto 0); + signal encoder_debug_i : std_logic_vector(31 downto 0); + + -- epoch counter + signal epoch_cntr : std_logic_vector(27 downto 0) := (others => '0'); + signal epoch_cntr_updated : std_logic := '0'; + signal epoch_capture_time : std_logic_vector(10 downto 0); + signal epoch_value : std_logic_vector(35 downto 0); + + -- fifo + signal fifo_data_out_i : std_logic_vector(35 downto 0); + signal fifo_data_in_i : std_logic_vector(35 downto 0); + signal fifo_empty_i : std_logic; + signal fifo_full_i : std_logic; + signal fifo_almost_full_sync : std_logic; + signal fifo_almost_full_sync1 : std_logic; + signal fifo_almost_full_sync2 : std_logic; + signal fifo_almost_full_i : std_logic := '0'; + signal fifo_almost_full_flag : std_logic := '0'; + signal fifo_wr_en_i : std_logic; + signal fifo_rd_en_i : std_logic; + signal fifo_rd_data_i : std_logic; + signal fifo_data_i : std_logic_vector(35 downto 0); + signal fifo_data_valid_i : std_logic; + + -- fsm + type FSM_WR is (WRITE_EPOCH, WRITE_DATA, WRITE_STOP_A, WRITE_STOP_B, WRITE_STOP_C, WRITE_STOP_D, WAIT_FOR_HIT, + WAIT_FOR_VALIDITY, EXCEPTION); + signal FSM_WR_CURRENT : FSM_WR := WRITE_EPOCH; + signal FSM_WR_NEXT : FSM_WR; + signal write_epoch_fsm : std_logic; + signal write_epoch_i : std_logic := '0'; + signal write_data_fsm : std_logic; + signal write_data_i : std_logic := '0'; + signal write_stop_a_fsm : std_logic; + signal write_stop_a_i : std_logic := '0'; + signal write_stop_b_fsm : std_logic; + signal write_stop_b_i : std_logic := '0'; + signal trig_win_end_tdc_flag_fsm : std_logic; + signal trig_win_end_tdc_flag_i : std_logic := '0'; + signal fsm_wr_debug_fsm : std_logic_vector(3 downto 0); + signal fsm_wr_debug_i : std_logic_vector(3 downto 0); + + type FSM_RD is (IDLE, FLUSH_A, FLUSH_B, FLUSH_C, FLUSH_D, READOUT_EPOCH, READOUT_DATA_A, READOUT_DATA_B, READOUT_DATA_C); + signal FSM_RD_STATE : FSM_RD; + signal trigger_win_end_rdo_flag_i : std_logic := '0'; + signal fsm_rd_debug_i : std_logic_vector(3 downto 0); + + ----------------------------------------------------------------------------- + -- debug + signal data_cnt_total : integer range 0 to 2147483647 := 0; + signal data_cnt_event : integer range 0 to 255 := 0; + signal epoch_cnt_total : integer range 0 to 65535 := 0; + signal epoch_cnt_event : integer range 0 to 127 := 0; + ----------------------------------------------------------------------------- + + attribute syn_keep : boolean; + attribute syn_keep of ff_array_en_i : signal is true; + +begin -- Channel_200 + + SimAdderYes : if SIMULATION = c_YES generate + --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition + FC : Adder_304 + port map ( + CLK => CLK_200, + RESET => RESET_200, + DataA => data_a_i, + DataB => data_b_i, + ClkEn => ff_array_en_i, + Result => result_i); + data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000FFFFFFF"&x"7FFFFFF"; + data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000"& not(HIT_IN) & x"000000"&"00" & HIT_IN; + end generate SimAdderYes; + SimAdderNo : if SIMULATION = c_NO generate + --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition + FC : Adder_304 + port map ( + CLK => CLK_200, + RESET => RESET_200, + DataA => data_a_i, + DataB => data_b_i, + ClkEn => ff_array_en_i, + Result => result_i); + data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"&x"7FFFFFF"; + data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000"& not(HIT_IN) & x"000000"&"00" & HIT_IN; + end generate SimAdderNo; + ff_array_en_i <= not(hit_detect_i or hit_detect_reg or hit_detect_2reg); + + result_2_reg <= result_i(2) when rising_edge(CLK_200); + hit_detect_i <= (not result_2_reg) and result_i(2); -- detects the hit by + -- comparing the + -- previous state of the + -- hit detection bit + hit_detect_reg <= hit_detect_i when rising_edge(CLK_200); + hit_detect_2reg <= hit_detect_reg when rising_edge(CLK_200); + coarse_cntr_reg <= COARSE_COUNTER_IN when rising_edge(CLK_200); + encoder_start_i <= hit_detect_reg; + ENCODER_START_OUT <= encoder_start_i; + + TimeStampCapture : process (CLK_200) + begin + if rising_edge(CLK_200) then + if encoder_finished_i = '1' then + time_stamp_i <= std_logic_vector(unsigned(coarse_cntr_reg) - to_unsigned(8, 11)); + end if; + end if; + end process TimeStampCapture; + + epoch_capture_time <= "00000001000"; + + EpochCounterCapture : process (CLK_200) + begin + if rising_edge(CLK_200) then + if coarse_cntr_reg = epoch_capture_time then --or TRIGGER_WIN_END_TDC = '1' then + epoch_cntr_updated <= '1'; + epoch_cntr <= EPOCH_COUNTER_IN; + elsif write_epoch_i = '1' then + epoch_cntr_updated <= '0'; + end if; + end if; + end process EpochCounterCapture; + + --purpose: Encoder + Encoder : Encoder_304_Bit + port map ( + RESET => RESET_200, + CLK => CLK_200, + START_IN => encoder_start_i, + THERMOCODE_IN => result_i, + FINISHED_OUT => encoder_finished_i, + BINARY_CODE_OUT => encoder_data_out_i, + ENCODER_DEBUG => encoder_debug_i); + + FIFO : FIFO_DC_36x128_OutReg + port map ( + Data => fifo_data_in_i, + WrClock => CLK_200, + RdClock => CLK_100, + WrEn => fifo_wr_en_i, + RdEn => fifo_rd_en_i, + Reset => RESET_100, + RPReset => RESET_200, + Q => fifo_data_out_i, + Empty => fifo_empty_i, + Full => fifo_full_i, + AlmostFull => fifo_almost_full_i); + + fifo_almost_full_sync <= fifo_almost_full_i when rising_edge(CLK_100); + fifo_almost_full_sync1 <= fifo_almost_full_sync when rising_edge(CLK_100); + fifo_almost_full_sync2 <= fifo_almost_full_sync1 when rising_edge(CLK_100); + fifo_rd_en_i <= fifo_rd_data_i or fifo_almost_full_sync when rising_edge(CLK_100); + + FifoAlmostmptyFlag : process (CLK_100) + begin + if rising_edge(CLK_100) then + if FSM_RD_STATE = READOUT_DATA_C then + fifo_almost_full_flag <= '0'; + elsif fifo_almost_full_sync = '1' then + fifo_almost_full_flag <= '1'; + end if; + end if; + end process FifoAlmostmptyFlag; + + +------------------------------------------------------------------------------- +-- Write Stage +------------------------------------------------------------------------------- + -- Readout fsm + FSM_CLK : process (CLK_200) + begin + if rising_edge(CLK_200) then + FSM_WR_CURRENT <= FSM_WR_NEXT; + write_epoch_i <= write_epoch_fsm; + write_data_i <= write_data_fsm; + write_stop_a_i <= write_stop_a_fsm; + write_stop_b_i <= write_stop_b_fsm; +-- trig_win_end_tdc_flag_i <= trig_win_end_tdc_flag_fsm; + fsm_wr_debug_i <= fsm_wr_debug_fsm; + end if; + end process FSM_CLK; + + isChannel : if REFERENCE = c_NO generate -- if it is a normal channel + FSM_PROC : process (FSM_WR_CURRENT, encoder_finished_i, epoch_cntr_updated, TRIGGER_WIN_END_TDC, + trig_win_end_tdc_flag_i) + begin + + FSM_WR_NEXT <= WRITE_EPOCH; + write_epoch_fsm <= '0'; + write_data_fsm <= '0'; + write_stop_a_fsm <= '0'; + write_stop_b_fsm <= '0'; +-- trig_win_end_tdc_flag_fsm <= trig_win_end_tdc_flag_i; + fsm_wr_debug_fsm <= x"0"; + + case (FSM_WR_CURRENT) is + when WRITE_EPOCH => + if encoder_finished_i = '1' then + write_epoch_fsm <= '1'; + FSM_WR_NEXT <= EXCEPTION; + elsif trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + write_epoch_fsm <= '0'; + FSM_WR_NEXT <= WRITE_EPOCH; + end if; + --if TRIGGER_WIN_END_TDC = '1' then + -- trig_win_end_tdc_flag_fsm <= '1'; + --end if; + fsm_wr_debug_fsm <= x"1"; +-- + when WRITE_DATA => + if epoch_cntr_updated = '1' then + write_epoch_fsm <= '1'; + FSM_WR_NEXT <= EXCEPTION; + else + write_data_fsm <= '1'; + if trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + FSM_WR_NEXT <= WAIT_FOR_HIT; + end if; + end if; + --if TRIGGER_WIN_END_TDC = '1' then + -- trig_win_end_tdc_flag_fsm <= '1'; + --end if; + fsm_wr_debug_fsm <= x"2"; +-- + when EXCEPTION => + write_data_fsm <= '1'; + if trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + FSM_WR_NEXT <= WAIT_FOR_HIT; + end if; + fsm_wr_debug_fsm <= x"3"; +-- + when WAIT_FOR_HIT => + if epoch_cntr_updated = '1' and encoder_finished_i = '0' then + FSM_WR_NEXT <= WRITE_EPOCH; + elsif epoch_cntr_updated = '0' and encoder_finished_i = '1' then + FSM_WR_NEXT <= WRITE_DATA; + elsif epoch_cntr_updated = '1' and encoder_finished_i = '1' then + write_epoch_fsm <= '1'; + FSM_WR_NEXT <= WRITE_DATA; + elsif trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + FSM_WR_NEXT <= WAIT_FOR_HIT; + end if; + --if TRIGGER_WIN_END_TDC = '1' then + -- trig_win_end_tdc_flag_fsm <= '1'; + --end if; + fsm_wr_debug_fsm <= x"4"; +-- + when WRITE_STOP_A => + write_stop_a_fsm <= '1'; + FSM_WR_NEXT <= WRITE_STOP_B; + fsm_wr_debug_fsm <= x"5"; +-- + when WRITE_STOP_B => + write_stop_a_fsm <= '1'; + FSM_WR_NEXT <= WRITE_STOP_C; + fsm_wr_debug_fsm <= x"5"; +-- + when WRITE_STOP_C => + write_stop_b_fsm <= '1'; + FSM_WR_NEXT <= WRITE_STOP_D; + fsm_wr_debug_fsm <= x"5"; +-- + when WRITE_STOP_D => + write_stop_b_fsm <= '1'; +-- trig_win_end_tdc_flag_fsm <= '0'; + FSM_WR_NEXT <= WRITE_EPOCH; + fsm_wr_debug_fsm <= x"5"; +-- + when others => + FSM_WR_NEXT <= WRITE_EPOCH; + write_epoch_fsm <= '0'; + write_data_fsm <= '0'; + write_stop_a_fsm <= '0'; + write_stop_b_fsm <= '0'; + fsm_wr_debug_fsm <= x"0"; + end case; + end process FSM_PROC; + end generate isChannel; -- if it is a normal channel + + isReference : if REFERENCE = c_YES generate -- if it is the reference channel + FSM_PROC : process (FSM_WR_CURRENT, encoder_finished_i, epoch_cntr_updated, TRIGGER_WIN_END_TDC, + trig_win_end_tdc_flag_i, VALID_TIMING_TRG_IN, MULTI_TMG_TRG_IN, SPIKE_DETECTED_IN) + begin + + FSM_WR_NEXT <= WRITE_EPOCH; + write_epoch_fsm <= '0'; + write_data_fsm <= '0'; + write_stop_a_fsm <= '0'; + write_stop_b_fsm <= '0'; +-- trig_win_end_tdc_flag_fsm <= trig_win_end_tdc_flag_i; + fsm_wr_debug_fsm <= x"0"; + + case (FSM_WR_CURRENT) is + when WRITE_EPOCH => + if encoder_finished_i = '1' then + FSM_WR_NEXT <= WAIT_FOR_VALIDITY; + elsif trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + write_epoch_fsm <= '0'; + FSM_WR_NEXT <= WRITE_EPOCH; + end if; + --if TRIGGER_WIN_END_TDC = '1' then + -- trig_win_end_tdc_flag_fsm <= '1'; + --end if; + fsm_wr_debug_fsm <= x"1"; +-- + when WAIT_FOR_VALIDITY => + if VALID_TIMING_TRG_IN = '1' then + write_epoch_fsm <= '1'; + FSM_WR_NEXT <= EXCEPTION; + elsif MULTI_TMG_TRG_IN = '1' or SPIKE_DETECTED_IN = '1' then + FSM_WR_NEXT <= WRITE_EPOCH; + else + FSM_WR_NEXT <= WAIT_FOR_VALIDITY; + end if; + fsm_wr_debug_fsm <= x"6"; +-- + when WRITE_DATA => + if epoch_cntr_updated = '1' then + write_epoch_fsm <= '1'; + FSM_WR_NEXT <= EXCEPTION; + else + write_data_fsm <= '1'; + if trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + FSM_WR_NEXT <= WAIT_FOR_HIT; + end if; + end if; + --if TRIGGER_WIN_END_TDC = '1' then + -- trig_win_end_tdc_flag_fsm <= '1'; + --end if; + fsm_wr_debug_fsm <= x"2"; +-- + when EXCEPTION => + write_data_fsm <= '1'; + if trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + FSM_WR_NEXT <= WAIT_FOR_HIT; + end if; + fsm_wr_debug_fsm <= x"3"; +-- + when WAIT_FOR_HIT => + if epoch_cntr_updated = '1' and encoder_finished_i = '0' then + FSM_WR_NEXT <= WRITE_EPOCH; + elsif epoch_cntr_updated = '0' and encoder_finished_i = '1' then + FSM_WR_NEXT <= WRITE_DATA; + elsif epoch_cntr_updated = '1' and encoder_finished_i = '1' then + write_epoch_fsm <= '1'; + FSM_WR_NEXT <= WRITE_DATA; + elsif trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + FSM_WR_NEXT <= WAIT_FOR_HIT; + end if; + --if TRIGGER_WIN_END_TDC = '1' then + -- trig_win_end_tdc_flag_fsm <= '1'; + --end if; + fsm_wr_debug_fsm <= x"4"; +-- + when WRITE_STOP_A => + write_stop_a_fsm <= '1'; + FSM_WR_NEXT <= WRITE_STOP_B; + fsm_wr_debug_fsm <= x"5"; +-- + when WRITE_STOP_B => + write_stop_a_fsm <= '1'; + FSM_WR_NEXT <= WRITE_STOP_C; + fsm_wr_debug_fsm <= x"5"; +-- + when WRITE_STOP_C => + write_stop_b_fsm <= '1'; + FSM_WR_NEXT <= WRITE_STOP_D; + fsm_wr_debug_fsm <= x"5"; +-- + when WRITE_STOP_D => + write_stop_b_fsm <= '1'; +-- trig_win_end_tdc_flag_fsm <= '0'; + FSM_WR_NEXT <= WRITE_EPOCH; + fsm_wr_debug_fsm <= x"5"; +-- + when others => + FSM_WR_NEXT <= WRITE_EPOCH; + write_epoch_fsm <= '0'; + write_data_fsm <= '0'; + write_stop_a_fsm <= '0'; + write_stop_b_fsm <= '0'; + fsm_wr_debug_fsm <= x"0"; + end case; + end process FSM_PROC; + end generate isReference; -- if it is the reference channel + + TriggerWindowFlag : process (CLK_200) + begin + if rising_edge(CLK_200) then + if TRIGGER_WIN_END_TDC = '1' then + trig_win_end_tdc_flag_i <= '1'; + elsif FSM_WR_CURRENT = WRITE_STOP_D then + trig_win_end_tdc_flag_i <= '0'; + end if; + end if; + end process TriggerWindowFlag; + + -- purpose: Generate Fifo Wr Signal + FifoWriteSignal : process (CLK_200) + begin + if rising_edge(CLK_200) then + if write_epoch_i = '1' and EPOCH_WRITE_EN_IN = '1' then + fifo_data_in_i(35 downto 32) <= x"1"; + fifo_data_in_i(31 downto 29) <= "011"; + fifo_data_in_i(28) <= '0'; + fifo_data_in_i(27 downto 0) <= epoch_cntr; + fifo_wr_en_i <= '1'; + elsif write_data_i = '1' then + fifo_data_in_i(35 downto 32) <= x"1"; + fifo_data_in_i(31) <= '1'; -- data marker + fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits + fifo_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number + fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder + fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge + fifo_data_in_i(10 downto 0) <= time_stamp_i; -- hit time stamp + fifo_wr_en_i <= '1'; + elsif write_stop_a_i = '1' then + fifo_data_in_i(35 downto 32) <= x"f"; + fifo_data_in_i(31 downto 0) <= (others => '0'); + fifo_wr_en_i <= '1'; + elsif write_stop_b_i = '1' then + fifo_data_in_i(35 downto 32) <= x"0"; + fifo_data_in_i(31 downto 0) <= (others => '0'); + fifo_wr_en_i <= '1'; + else + fifo_data_in_i(35 downto 32) <= x"e"; + fifo_data_in_i(31 downto 0) <= (others => '0'); + fifo_wr_en_i <= '0'; + end if; + end if; + end process FifoWriteSignal; + + FIFO_WRITE_OUT <= fifo_wr_en_i; + ENCODER_FINISHED_OUT <= encoder_finished_i; + +------------------------------------------------------------------------------- +-- Read Stage +------------------------------------------------------------------------------- + -- Determine the next state synchronously, based on the current state and the + -- input + FSM_DATA_STATE : process (CLK_100) + begin + if (rising_edge(CLK_100)) then + if RESET_100 = '1' then + FSM_RD_STATE <= IDLE; + else + + case FSM_RD_STATE is + when IDLE => + -- if the data readout is triggered by the end of the trigger window + if TRIGGER_WIN_END_RDO = '1' then + FSM_RD_STATE <= READOUT_DATA_A; + -- if the data readout is triggered by full fifo + elsif fifo_almost_full_flag = '1' then + FSM_RD_STATE <= FLUSH_A; + else + FSM_RD_STATE <= IDLE; + end if; +-- + when FLUSH_A => + FSM_RD_STATE <= FLUSH_B; +-- + when FLUSH_B => + FSM_RD_STATE <= FLUSH_C; +-- + when FLUSH_C => + FSM_RD_STATE <= FLUSH_D; +-- + when FLUSH_D => + -- wait until a readout request and register the last epoch word + if TRIGGER_WIN_END_RDO = '1' or trigger_win_end_rdo_flag_i = '1' then + FSM_RD_STATE <= READOUT_EPOCH; + else + FSM_RD_STATE <= FLUSH_D; + end if; +-- + when READOUT_EPOCH => + -- first epoch word should be readout + FSM_RD_STATE <= READOUT_DATA_C; +-- + when READOUT_DATA_A => + FSM_RD_STATE <= READOUT_DATA_B; +-- + when READOUT_DATA_B => + FSM_RD_STATE <= READOUT_DATA_C; + + when READOUT_DATA_C => + -- normal data readout until the end of the readout request + if fifo_data_out_i(35 downto 32) = x"f" then + FSM_RD_STATE <= IDLE; + else + FSM_RD_STATE <= READOUT_DATA_C; + end if; +-- + when others => + FSM_RD_STATE <= IDLE; + end case; + end if; + end if; + end process FSM_DATA_STATE; + + -- Determine the output based only on the current state and the input (do not wait for a clock + -- edge). + FSM_DATA_OUTPUT : process (FSM_RD_STATE, TRIGGER_WIN_END_RDO, fifo_data_out_i, epoch_value) + begin + trigger_win_end_rdo_flag_i <= trigger_win_end_rdo_flag_i; + epoch_value <= epoch_value; + + case FSM_RD_STATE is + when IDLE => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + fifo_rd_data_i <= '0'; + fsm_rd_debug_i <= x"1"; + when FLUSH_A => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + fifo_rd_data_i <= '0'; + if TRIGGER_WIN_END_RDO = '1' then + trigger_win_end_rdo_flag_i <= '1'; + end if; + fsm_rd_debug_i <= x"2"; + when FLUSH_B => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + fifo_rd_data_i <= '0'; + if TRIGGER_WIN_END_RDO = '1' then + trigger_win_end_rdo_flag_i <= '1'; + end if; + fsm_rd_debug_i <= x"3"; + when FLUSH_C => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + fifo_rd_data_i <= '0'; + if TRIGGER_WIN_END_RDO = '1' then + trigger_win_end_rdo_flag_i <= '1'; + end if; + fsm_rd_debug_i <= x"4"; + when FLUSH_D => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + fifo_rd_data_i <= '0'; + if fifo_data_out_i(31 downto 29) = "011" then + epoch_value <= fifo_data_out_i; + end if; + fsm_rd_debug_i <= x"5"; + when READOUT_EPOCH => + fifo_data_i <= epoch_value; + fifo_data_valid_i <= '1'; + fifo_rd_data_i <= '0'; + fsm_rd_debug_i <= x"6"; + when READOUT_DATA_A => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + fifo_rd_data_i <= '1'; + trigger_win_end_rdo_flag_i <= '0'; + fsm_rd_debug_i <= x"7"; + when READOUT_DATA_B => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + fifo_rd_data_i <= '1'; + fsm_rd_debug_i <= x"8"; + when READOUT_DATA_C => + fifo_data_i <= fifo_data_out_i; + if fifo_data_out_i(35 downto 32) = x"0" then + fifo_data_valid_i <= '0'; + else + fifo_data_valid_i <= '1'; + end if; + fifo_rd_data_i <= '1'; + fsm_rd_debug_i <= x"9"; + when others => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + fifo_rd_data_i <= '0'; + fsm_rd_debug_i <= x"0"; + end case; + end process FSM_DATA_OUTPUT; + + FIFO_DATA_OUT <= fifo_data_i; + FIFO_DATA_VALID_OUT <= fifo_data_valid_i; + + RegisterOutputs : process (CLK_100) + begin + if rising_edge(CLK_100) then + FIFO_EMPTY_OUT <= fifo_empty_i; + end if; + end process RegisterOutputs; + + FIFO_FULL_OUT <= fifo_full_i when rising_edge(CLK_200); + FIFO_ALMOST_FULL_OUT <= fifo_almost_full_i when rising_edge(CLK_200); + +------------------------------------------------------------------------------- +-- DEBUG +------------------------------------------------------------------------------- + CHANNEL_200_DEBUG(7 downto 0) <= fifo_data_in_i(35 downto 28); + CHANNEL_200_DEBUG(15 downto 8) <= fifo_data_i(35 downto 28); + CHANNEL_200_DEBUG(16) <= fifo_wr_en_i; + CHANNEL_200_DEBUG(17) <= fifo_data_valid_i; + CHANNEL_200_DEBUG(18) <= fifo_rd_en_i; + CHANNEL_200_DEBUG(23 downto 19) <= (others => '0'); + CHANNEL_200_DEBUG(27 downto 24) <= fsm_rd_debug_i; + CHANNEL_200_DEBUG(31 downto 28) <= fsm_wr_debug_i; + + gen_SIMULATION : if SIMULATION = c_YES generate + -- count data written + data_cntr : process + begin + wait until rising_edge(CLK_100); + if fifo_data_valid_i = '1' and fifo_data_i(31 downto 29) = "100" then + data_cnt_event <= data_cnt_event + 1; + elsif fifo_data_valid_i = '1' and fifo_data_i(31 downto 29) = "011" then + epoch_cnt_event <= epoch_cnt_event + 1; + elsif TRIGGER_WIN_END_RDO = '1' then + data_cnt_event <= 0; + epoch_cnt_event <= 0; + end if; + end process data_cntr; + + process(fifo_data_valid_i) + begin -- process + data_cnt_total <= data_cnt_total + data_cnt_event; + epoch_cnt_total <= epoch_cnt_total + epoch_cnt_event; + end process; + + -- check if data count per event is correct + --CheckEpochCounter : process + --begin + -- wait until falling_edge(fifo_data_valid_i); + -- wait for 1 ns; + -- if data_cnt_event /= 30 then + -- report "wrong number of hits in channel " & integer'image(CHANNEL_ID) severity error; + -- end if; + --end process CheckEpochCounter; + + + + + + + end generate gen_SIMULATION; + +end Channel_200; diff --git a/tdc_releases/tdc_v1.6/Encoder_304_Bit.vhd b/tdc_releases/tdc_v1.6/Encoder_304_Bit.vhd new file mode 100644 index 0000000..1a403e0 --- /dev/null +++ b/tdc_releases/tdc_v1.6/Encoder_304_Bit.vhd @@ -0,0 +1,428 @@ +------------------------------------------------------------------------------- +-- Title : Encoder 304 bits +------------------------------------------------------------------------------- +-- File : Encoder_304_Bit.vhd +-- Author : Cahit Ugur +-- Created : 2011-11-28 +-- Last update: 2013-03-17 +------------------------------------------------------------------------------- +-- Description: Encoder for 304 bits +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2011-11-28 1.0 ugur Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb3_components.all; + +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity Encoder_304_Bit is + port ( + RESET : in std_logic; -- system reset + CLK : in std_logic; -- system clock + START_IN : in std_logic; + THERMOCODE_IN : in std_logic_vector(303 downto 0); + FINISHED_OUT : out std_logic; + BINARY_CODE_OUT : out std_logic_vector(9 downto 0); + ENCODER_INFO_OUT : out std_logic_vector(1 downto 0); + ENCODER_DEBUG : out std_logic_vector(31 downto 0) + ); +end Encoder_304_Bit; + +architecture behavioral of Encoder_304_Bit is + +------------------------------------------------------------------------------- +-- Component Declarations +------------------------------------------------------------------------------- + component LUT4 + generic ( + INIT : std_logic_vector); + port ( + A, B, C, D : in std_ulogic; + Z : out std_ulogic); + end component; + +------------------------------------------------------------------------------- +-- Signal Declarations +------------------------------------------------------------------------------- + signal P_lut : std_logic_vector(37 downto 0); + signal P_one : std_logic_vector(37 downto 0); + signal mux_control : std_logic_vector(5 downto 0); + signal mux_control_reg : std_logic_vector(5 downto 0); + signal mux_control_2reg : std_logic_vector(5 downto 0); + signal mux_control_3reg : std_logic_vector(5 downto 0); + signal interval_reg : std_logic_vector(8 downto 0); + signal interval_binary : std_logic_vector(2 downto 0); + signal binary_code_f : std_logic_vector(8 downto 0); + signal binary_code_r : std_logic_vector(8 downto 0); + signal start_reg : std_logic; + signal start_2reg : std_logic; + signal address_i : std_logic_vector(9 downto 0); + signal q_reg : std_logic_vector(7 downto 0); + signal info : std_logic_vector(1 downto 0); + signal info_reg : std_logic_vector(1 downto 0); + signal info_2reg : std_logic_vector(1 downto 0); + signal info_3reg : std_logic_vector(1 downto 0); + signal info_4reg : std_logic_vector(1 downto 0); + +-- FSM signals + type FSM is (IDLE, START_CNT_2, START_CNT_3, START_CNT_4); + signal FSM_CURRENT, FSM_NEXT : FSM; + + signal start_cnt_1_fsm : std_logic; + signal start_cnt_2_fsm : std_logic; + signal start_cnt_3_fsm : std_logic; + signal start_cnt_4_fsm : std_logic; + signal start_cnt_1_i : std_logic; + signal start_cnt_2_i : std_logic; + signal start_cnt_3_i : std_logic; + signal start_cnt_4_i : std_logic; +-- + signal proc_cnt_1 : std_logic_vector(3 downto 0) := x"6"; + signal proc_cnt_2 : std_logic_vector(3 downto 0) := x"6"; + signal proc_cnt_3 : std_logic_vector(3 downto 0) := x"6"; + signal proc_cnt_4 : std_logic_vector(3 downto 0); + signal proc_finished_1 : std_logic; + signal proc_finished_2 : std_logic; + signal proc_finished_3 : std_logic; + signal proc_finished_4 : std_logic; + signal conv_finished_i : std_logic; + signal thermocode_i : std_logic_vector(304 downto 0); + + attribute syn_keep : boolean; + attribute syn_keep of mux_control : signal is true; + attribute syn_keep of mux_control_reg : signal is true; + attribute syn_keep of mux_control_2reg : signal is true; + attribute syn_keep of mux_control_3reg : signal is true; +------------------------------------------------------------------------------- +begin + + + thermocode_i(304 downto 1) <= THERMOCODE_IN; + thermocode_i(0) <= '1'; + start_reg <= START_IN when rising_edge(CLK); + start_2reg <= start_reg when rising_edge(CLK); + mux_control_reg <= mux_control when rising_edge(CLK); + mux_control_2reg <= mux_control_reg when rising_edge(CLK); + mux_control_3reg <= mux_control_2reg when rising_edge(CLK); + + Interval_Determination_First : LUT4 + generic map (INIT => X"15A8") + port map (A => '1', B => '1', C => THERMOCODE_IN(0), D => START_IN, + Z => P_lut(0)); + + Interval_Determination : for i in 1 to 37 generate + U : LUT4 + generic map (INIT => X"15A8") + port map (A => THERMOCODE_IN(8*i-2), B => THERMOCODE_IN(8*i-1), C => THERMOCODE_IN(8*i), D => START_IN, + Z => P_lut(i)); + end generate Interval_Determination; +------------------------------------------------------------------------------- + + Gen_P_one : for i in 0 to 36 generate + P_one(i) <= P_lut(i) and (not P_lut(i+1)) when rising_edge(CLK); + end generate Gen_P_one; + + P_one_assign : process (CLK) + begin + if rising_edge(CLK) then + if START_IN = '0' then + P_one(37) <= '0'; + else + P_one(37) <= P_lut(37); + end if; + end if; + end process P_one_assign; + + Interval_Number_to_Binary : process (CLK) + begin -- The interval number with the 0-1 transition is converted from 1-of-N code to binary + -- code for the control of the MUX. + if rising_edge(CLK) then + if start_2reg = '1' or start_reg = '1' then + mux_control(0) <= P_one(0) or P_one(2) or P_one(4) or P_one(6) or P_one(8) or P_one(10) or + P_one(12) or P_one(14) or P_one(16) or P_one(18) or P_one(20) or P_one(22) or + P_one(24) or P_one(26) or P_one(28) or P_one(30) or P_one(32) or P_one(34) or + P_one(36); + mux_control(1) <= P_one(1) or P_one(2) or P_one(5) or P_one(6) or P_one(9) or P_one(10) or + P_one(13) or P_one(14) or P_one(17) or P_one(18) or P_one(21) or P_one(22) or + P_one(25) or P_one(26) or P_one(29) or P_one(30) or P_one(33) or P_one(34) or + P_one(37); + mux_control(2) <= P_one(3) or P_one(4) or P_one(5) or P_one(6) or P_one(11) or P_one(12) or + P_one(13) or P_one(14) or P_one(19) or P_one(20) or P_one(21) or P_one(22) or + P_one(27) or P_one(28) or P_one(29) or P_one(30) or P_one(35) or P_one(36) or + P_one(37); + mux_control(3) <= P_one(7) or P_one(8) or P_one(9) or P_one(10) or P_one(11) or P_one(12) or + P_one(13) or P_one(14) or P_one(23) or P_one(24) or P_one(25) or P_one(26) or + P_one(27) or P_one(28) or P_one(29) or P_one(30); + mux_control(4) <= P_one(15) or P_one(16) or P_one(17) or P_one(18) or P_one(19) or P_one(20) or + P_one(21) or P_one(22) or P_one(23) or P_one(24) or P_one(25) or P_one(26) or + P_one(27) or P_one(28) or P_one(29) or P_one(30); + mux_control(5) <= P_one(31) or P_one(32) or P_one(33) or P_one(34) or P_one(35) or P_one(36) or + P_one(37); + else + mux_control <= (others => '0'); + end if; + end if; + end process Interval_Number_to_Binary; + + Interval_Selection : process (CLK) + variable tmp : std_logic_vector(9 downto 1); + begin -- The interval with the 0-1 transition is selected. + if rising_edge(CLK) then + tmp := (others => '0'); + make_mux : for i in 0 to 37 loop + make_mux_2 : for j in 1 to 9 loop + tmp(j) := tmp(j) or (thermocode_i(i*8-1+j) and P_one(i)); + end loop; + end loop; + interval_reg <= tmp; + end if; + end process Interval_Selection; + + ROM_Encoder_1 : ROM_Encoder + port map ( + Address => address_i, + OutClock => CLK, + OutClockEn => '1', + Reset => RESET, + Q => q_reg); + + --ROM4_Encoder_1 : ROM4_Encoder + -- port map ( + -- Address => address_i, + -- OutClock => CLK, + -- OutClockEn => '1', + -- Reset => RESET, + -- Q => q_reg); + address_i <= start_2reg & interval_reg; + interval_binary <= q_reg(2 downto 0) when rising_edge(CLK); + info <= q_reg(7 downto 6) when rising_edge(CLK); + info_reg <= info when rising_edge(CLK); + info_2reg <= info_reg when rising_edge(CLK); + info_3reg <= info_2reg when rising_edge(CLK); + info_4reg <= info_3reg when rising_edge(CLK); + + Binary_Code_Calculation_rf : process (CLK) + begin + if rising_edge(CLK) then + binary_code_r <= (mux_control_3reg - 1) & interval_binary; + binary_code_f <= binary_code_r; + end if; + end process Binary_Code_Calculation_rf; + + --purpose: FSMs the encoder + FSM_CLK : process (CLK) + begin + if rising_edge(CLK) then + FSM_CURRENT <= FSM_NEXT; + start_cnt_1_i <= start_cnt_1_fsm; + start_cnt_2_i <= start_cnt_2_fsm; + start_cnt_3_i <= start_cnt_3_fsm; + start_cnt_4_i <= start_cnt_4_fsm; + end if; + end process FSM_CLK; + + FSM_PROC : process (FSM_CURRENT, START_IN) + begin + + FSM_NEXT <= IDLE; + start_cnt_1_fsm <= '0'; + start_cnt_2_fsm <= '0'; + start_cnt_3_fsm <= '0'; + start_cnt_4_fsm <= '0'; + + case (FSM_CURRENT) is + when IDLE => + if START_IN = '1' then + FSM_NEXT <= START_CNT_2; + start_cnt_1_fsm <= '1'; + end if; + + when START_CNT_2 => + if START_IN = '1' then + FSM_NEXT <= START_CNT_3; + start_cnt_2_fsm <= '1'; + else + FSM_NEXT <= START_CNT_2; + end if; + + when START_CNT_3 => + if START_IN = '1' then + FSM_NEXT <= START_CNT_4; + start_cnt_3_fsm <= '1'; + else + FSM_NEXT <= START_CNT_3; + end if; + + when START_CNT_4 => + if START_IN = '1' then + FSM_NEXT <= IDLE; + start_cnt_4_fsm <= '1'; + else + FSM_NEXT <= START_CNT_4; + end if; + + when others => + FSM_NEXT <= IDLE; + end case; + end process FSM_PROC; + + --purpose : Conversion number 1 + Conv_1 : process (CLK) + begin + if rising_edge(CLK) then + if start_cnt_1_i = '1' then + proc_cnt_1 <= x"1"; + proc_finished_1 <= '0'; + elsif proc_cnt_1 = x"5" then + proc_cnt_1 <= proc_cnt_1 + 1; + proc_finished_1 <= '1'; + elsif proc_cnt_1 = x"6" then + proc_cnt_1 <= x"6"; + proc_finished_1 <= '0'; + else + proc_cnt_1 <= proc_cnt_1 + 1; + proc_finished_1 <= '0'; + end if; + end if; + end process Conv_1; + + --purpose : Conversion number 2 + Conv_2 : process (CLK) + begin + if rising_edge(CLK) then + if start_cnt_2_i = '1' then + proc_cnt_2 <= x"1"; + proc_finished_2 <= '0'; + elsif proc_cnt_2 = x"5" then + proc_cnt_2 <= proc_cnt_2 + 1; + proc_finished_2 <= '1'; + elsif proc_cnt_2 = x"6" then + proc_cnt_2 <= x"6"; + proc_finished_2 <= '0'; + else + proc_cnt_2 <= proc_cnt_2 + 1; + proc_finished_2 <= '0'; + end if; + end if; + end process Conv_2; + + --purpose : Conversion number 3 + Conv_3 : process (CLK) + begin + if rising_edge(CLK) then + if start_cnt_3_i = '1' then + proc_cnt_3 <= x"1"; + proc_finished_3 <= '0'; + elsif proc_cnt_3 = x"5" then + proc_cnt_3 <= proc_cnt_3 + 1; + proc_finished_3 <= '1'; + elsif proc_cnt_3 = x"6" then + proc_cnt_3 <= x"6"; + proc_finished_3 <= '0'; + else + proc_cnt_3 <= proc_cnt_3 + 1; + proc_finished_3 <= '0'; + end if; + end if; + end process Conv_3; + + --purpose : Conversion number 4 + Conv_4 : process (CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + proc_cnt_4 <= x"6"; + proc_finished_4 <= '0'; + elsif start_cnt_4_i = '1' then + proc_cnt_4 <= x"1"; + proc_finished_4 <= '0'; + elsif proc_cnt_4 = x"5" then + proc_cnt_4 <= proc_cnt_4 + 1; + proc_finished_4 <= '1'; + elsif proc_cnt_4 = x"6" then + proc_cnt_4 <= x"6"; + proc_finished_4 <= '0'; + else + proc_cnt_4 <= proc_cnt_4 + 1; + proc_finished_4 <= '0'; + end if; + end if; + end process Conv_4; + + Binary_Code_Calculation : process (CLK) + begin + if rising_edge(CLK) then + if conv_finished_i = '1' then + if info_reg(1) = '1' and info_2reg(1) = '1' then + BINARY_CODE_OUT <= ('0' & binary_code_r) + ('0' & binary_code_f); + else + BINARY_CODE_OUT <= (others => '1'); + end if; + ENCODER_INFO_OUT <= (others => '0'); --info_reg or info_2reg; + FINISHED_OUT <= '1'; + else + FINISHED_OUT <= '0'; + end if; + end if; + end process Binary_Code_Calculation; + + conv_finished_i <= proc_finished_1 or proc_finished_2 or proc_finished_3 or proc_finished_4; + + +------------------------------------------------------------------------------- +-- DEBUG +------------------------------------------------------------------------------- + ----purpose : Conversion number 1 + --Conv_1 : process (CLK, RESET) + --begin + -- if rising_edge(CLK) then + -- if RESET = '1' then + -- proc_cnt_1 <= x"3"; + -- proc_finished_1 <= '0'; + -- elsif START_IN = '1' then + -- proc_cnt_1 <= x"1"; + -- proc_finished_1 <= '0'; + -- elsif proc_cnt_1 = x"1" or proc_cnt_1 = x"2" then + -- proc_cnt_1 <= proc_cnt_1 + 1; + -- proc_finished_1 <= '1'; + -- elsif proc_cnt_1 = x"3" then + -- proc_cnt_1 <= x"3"; + -- proc_finished_1 <= '0'; + -- else + -- proc_cnt_1 <= proc_cnt_1 + 1; + -- proc_finished_1 <= '0'; + -- end if; + -- end if; + --end process Conv_1; + + --Binary_Code_Calculation : process (CLK, RESET) + --begin + -- if rising_edge(CLK) then + -- if RESET = '1' then + -- BINARY_CODE_OUT <= (others => '0'); + -- FINISHED_OUT <= '0'; + -- elsif proc_finished_1 = '1' then + -- BINARY_CODE_OUT <= address_i; --'0' & interval_reg; + -- FINISHED_OUT <= '1'; + -- else + -- BINARY_CODE_OUT <= (others => '0'); + -- FINISHED_OUT <= '0'; + -- end if; + -- end if; + --end process Binary_Code_Calculation; + + --ENCODER_DEBUG(8 downto 0) <= interval_reg; + +end behavioral; diff --git a/tdc_releases/tdc_v1.6/FIFO_36x128_OutReg_Counter.vhd b/tdc_releases/tdc_v1.6/FIFO_36x128_OutReg_Counter.vhd new file mode 100644 index 0000000..14b4942 --- /dev/null +++ b/tdc_releases/tdc_v1.6/FIFO_36x128_OutReg_Counter.vhd @@ -0,0 +1,1094 @@ +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 5.4 +--/opt/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -rdata_width 36 -regout -no_enable -pe -1 -pf -1 -fill -e + +-- Wed Jan 30 11:50:36 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity FIFO_36x128_OutReg_Counter is + port ( + Data : in std_logic_vector(35 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(7 downto 0); + Empty : out std_logic; + Full : out std_logic); +end FIFO_36x128_OutReg_Counter; + +architecture Structure of FIFO_36x128_OutReg_Counter is + + -- internal signal declarations + signal invout_1 : std_logic; + signal invout_0 : std_logic; + signal w_g2b_xor_cluster_1 : std_logic; + signal r_g2b_xor_cluster_1 : std_logic; + signal w_gdata_0 : std_logic; + signal w_gdata_1 : std_logic; + signal w_gdata_2 : std_logic; + signal w_gdata_3 : std_logic; + signal w_gdata_4 : std_logic; + signal w_gdata_5 : std_logic; + signal w_gdata_6 : std_logic; + signal wptr_7 : std_logic; + signal r_gdata_0 : std_logic; + signal r_gdata_1 : std_logic; + signal r_gdata_2 : std_logic; + signal r_gdata_3 : std_logic; + signal r_gdata_4 : std_logic; + signal r_gdata_5 : std_logic; + signal r_gdata_6 : std_logic; + signal rptr_0 : std_logic; + signal rptr_1 : std_logic; + signal rptr_2 : std_logic; + signal rptr_3 : std_logic; + signal rptr_4 : std_logic; + signal rptr_5 : std_logic; + signal rptr_6 : std_logic; + signal rptr_7 : std_logic; + signal w_gcount_0 : std_logic; + signal w_gcount_1 : std_logic; + signal w_gcount_2 : std_logic; + signal w_gcount_3 : std_logic; + signal w_gcount_4 : std_logic; + signal w_gcount_5 : std_logic; + signal w_gcount_6 : std_logic; + signal w_gcount_7 : std_logic; + signal r_gcount_0 : std_logic; + signal r_gcount_1 : std_logic; + signal r_gcount_2 : std_logic; + signal r_gcount_3 : std_logic; + signal r_gcount_4 : std_logic; + signal r_gcount_5 : std_logic; + signal r_gcount_6 : std_logic; + signal r_gcount_7 : std_logic; + signal w_gcount_r20 : std_logic; + signal w_gcount_r0 : std_logic; + signal w_gcount_r21 : std_logic; + signal w_gcount_r1 : std_logic; + signal w_gcount_r22 : std_logic; + signal w_gcount_r2 : std_logic; + signal w_gcount_r23 : std_logic; + signal w_gcount_r3 : std_logic; + signal w_gcount_r24 : std_logic; + signal w_gcount_r4 : std_logic; + signal w_gcount_r25 : std_logic; + signal w_gcount_r5 : std_logic; + signal w_gcount_r26 : std_logic; + signal w_gcount_r6 : std_logic; + signal w_gcount_r27 : std_logic; + signal w_gcount_r7 : std_logic; + signal r_gcount_w20 : std_logic; + signal r_gcount_w0 : std_logic; + signal r_gcount_w21 : std_logic; + signal r_gcount_w1 : std_logic; + signal r_gcount_w22 : std_logic; + signal r_gcount_w2 : std_logic; + signal r_gcount_w23 : std_logic; + signal r_gcount_w3 : std_logic; + signal r_gcount_w24 : std_logic; + signal r_gcount_w4 : std_logic; + signal r_gcount_w25 : std_logic; + signal r_gcount_w5 : std_logic; + signal r_gcount_w26 : std_logic; + signal r_gcount_w6 : std_logic; + signal r_gcount_w27 : std_logic; + signal r_gcount_w7 : std_logic; + signal empty_i : std_logic; + signal rRst : std_logic; + signal full_i : std_logic; + signal iwcount_0 : std_logic; + signal iwcount_1 : std_logic; + signal w_gctr_ci : std_logic; + signal iwcount_2 : std_logic; + signal iwcount_3 : std_logic; + signal co0 : std_logic; + signal iwcount_4 : std_logic; + signal iwcount_5 : std_logic; + signal co1 : std_logic; + signal iwcount_6 : std_logic; + signal iwcount_7 : std_logic; + signal co3 : std_logic; + signal wcount_7 : std_logic; + signal co2 : std_logic; + signal ircount_0 : std_logic; + signal ircount_1 : std_logic; + signal r_gctr_ci : std_logic; + signal ircount_2 : std_logic; + signal ircount_3 : std_logic; + signal co0_1 : std_logic; + signal ircount_4 : std_logic; + signal ircount_5 : std_logic; + signal co1_1 : std_logic; + signal ircount_6 : std_logic; + signal ircount_7 : std_logic; + signal co3_1 : std_logic; + signal rcount_7 : std_logic; + signal co2_1 : std_logic; + signal wfill_sub_0 : std_logic; + signal scuba_vhi : std_logic; + signal wptr_0 : std_logic; + signal wfill_sub_1 : std_logic; + signal wfill_sub_2 : std_logic; + signal co0_2 : std_logic; + signal wptr_1 : std_logic; + signal wptr_2 : std_logic; + signal wfill_sub_3 : std_logic; + signal wfill_sub_4 : std_logic; + signal co1_2 : std_logic; + signal wptr_3 : std_logic; + signal wptr_4 : std_logic; + signal wfill_sub_5 : std_logic; + signal wfill_sub_6 : std_logic; + signal co2_2 : std_logic; + signal wptr_5 : std_logic; + signal wptr_6 : std_logic; + signal wfill_sub_7 : std_logic; + signal co3_2 : std_logic; + signal wfill_sub_msb : std_logic; + signal rden_i : std_logic; + signal cmp_ci : std_logic; + signal wcount_r0 : std_logic; + signal wcount_r1 : std_logic; + signal rcount_0 : std_logic; + signal rcount_1 : std_logic; + signal co0_3 : std_logic; + signal wcount_r2 : std_logic; + signal wcount_r3 : std_logic; + signal rcount_2 : std_logic; + signal rcount_3 : std_logic; + signal co1_3 : std_logic; + signal w_g2b_xor_cluster_0 : std_logic; + signal wcount_r5 : std_logic; + signal rcount_4 : std_logic; + signal rcount_5 : std_logic; + signal co2_3 : std_logic; + signal wcount_r6 : std_logic; + signal empty_cmp_clr : std_logic; + signal rcount_6 : std_logic; + signal empty_cmp_set : std_logic; + signal empty_d : std_logic; + signal empty_d_c : std_logic; + signal wren_i : std_logic; + signal cmp_ci_1 : std_logic; + signal rcount_w0 : std_logic; + signal rcount_w1 : std_logic; + signal wcount_0 : std_logic; + signal wcount_1 : std_logic; + signal co0_4 : std_logic; + signal rcount_w2 : std_logic; + signal rcount_w3 : std_logic; + signal wcount_2 : std_logic; + signal wcount_3 : std_logic; + signal co1_4 : std_logic; + signal r_g2b_xor_cluster_0 : std_logic; + signal rcount_w5 : std_logic; + signal wcount_4 : std_logic; + signal wcount_5 : std_logic; + signal co2_4 : std_logic; + signal rcount_w6 : std_logic; + signal full_cmp_clr : std_logic; + signal wcount_6 : std_logic; + signal full_cmp_set : std_logic; + signal full_d : std_logic; + signal full_d_c : std_logic; + signal scuba_vlo : std_logic; + + -- local component declarations + component AGEB2 + port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; + B1 : in std_logic; CI : in std_logic; GE : out std_logic); + end component; + component AND2 + port (A : in std_logic; B : in std_logic; Z : out std_logic); + end component; + component CU2 + port (CI : in std_logic; PC0 : in std_logic; PC1 : in std_logic; + CO : out std_logic; NC0 : out std_logic; NC1 : out std_logic); + end component; + component FADD2B + port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; + B1 : in std_logic; CI : in std_logic; COUT : out std_logic; + S0 : out std_logic; S1 : out std_logic); + end component; + component FSUB2B + port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; + B1 : in std_logic; BI : in std_logic; BOUT : out std_logic; + S0 : out std_logic; S1 : out std_logic); + end component; + component FD1P3BX + port (D : in std_logic; SP : in std_logic; CK : in std_logic; + PD : in std_logic; Q : out std_logic); + end component; + component FD1P3DX + port (D : in std_logic; SP : in std_logic; CK : in std_logic; + CD : in std_logic; Q : out std_logic); + end component; + component FD1S3BX + port (D : in std_logic; CK : in std_logic; PD : in std_logic; + Q : out std_logic); + end component; + component FD1S3DX + port (D : in std_logic; CK : in std_logic; CD : in std_logic; + Q : out std_logic); + end component; + component INV + port (A : in std_logic; Z : out std_logic); + end component; + component OR2 + port (A : in std_logic; B : in std_logic; Z : out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3 : in std_logic; AD2 : in std_logic; AD1 : in std_logic; + AD0 : in std_logic; DO0 : out std_logic); + end component; + component VHI + port (Z : out std_logic); + end component; + component VLO + port (Z : out std_logic); + end component; + component XOR2 + port (A : in std_logic; B : in std_logic; Z : out std_logic); + end component; + component PDPW16KC + generic (GSR : in string; CSDECODE_R : in string; + CSDECODE_W : in string; REGMODE : in string; + DATA_WIDTH_R : in integer; DATA_WIDTH_W : in integer); + port (DI0 : in std_logic; DI1 : in std_logic; DI2 : in std_logic; + DI3 : in std_logic; DI4 : in std_logic; DI5 : in std_logic; + DI6 : in std_logic; DI7 : in std_logic; DI8 : in std_logic; + DI9 : in std_logic; DI10 : in std_logic; DI11 : in std_logic; + DI12 : in std_logic; DI13 : in std_logic; + DI14 : in std_logic; DI15 : in std_logic; + DI16 : in std_logic; DI17 : in std_logic; + DI18 : in std_logic; DI19 : in std_logic; + DI20 : in std_logic; DI21 : in std_logic; + DI22 : in std_logic; DI23 : in std_logic; + DI24 : in std_logic; DI25 : in std_logic; + DI26 : in std_logic; DI27 : in std_logic; + DI28 : in std_logic; DI29 : in std_logic; + DI30 : in std_logic; DI31 : in std_logic; + DI32 : in std_logic; DI33 : in std_logic; + DI34 : in std_logic; DI35 : in std_logic; + ADW0 : in std_logic; ADW1 : in std_logic; + ADW2 : in std_logic; ADW3 : in std_logic; + ADW4 : in std_logic; ADW5 : in std_logic; + ADW6 : in std_logic; ADW7 : in std_logic; + ADW8 : in std_logic; BE0 : in std_logic; BE1 : in std_logic; + BE2 : in std_logic; BE3 : in std_logic; CEW : in std_logic; + CLKW : in std_logic; CSW0 : in std_logic; + CSW1 : in std_logic; CSW2 : in std_logic; + ADR0 : in std_logic; ADR1 : in std_logic; + ADR2 : in std_logic; ADR3 : in std_logic; + ADR4 : in std_logic; ADR5 : in std_logic; + ADR6 : in std_logic; ADR7 : in std_logic; + ADR8 : in std_logic; ADR9 : in std_logic; + ADR10 : in std_logic; ADR11 : in std_logic; + ADR12 : in std_logic; ADR13 : in std_logic; + CER : in std_logic; CLKR : in std_logic; CSR0 : in std_logic; + CSR1 : in std_logic; CSR2 : in std_logic; RST : in std_logic; + DO0 : out std_logic; DO1 : out std_logic; + DO2 : out std_logic; DO3 : out std_logic; + DO4 : out std_logic; DO5 : out std_logic; + DO6 : out std_logic; DO7 : out std_logic; + DO8 : out std_logic; DO9 : out std_logic; + DO10 : out std_logic; DO11 : out std_logic; + DO12 : out std_logic; DO13 : out std_logic; + DO14 : out std_logic; DO15 : out std_logic; + DO16 : out std_logic; DO17 : out std_logic; + DO18 : out std_logic; DO19 : out std_logic; + DO20 : out std_logic; DO21 : out std_logic; + DO22 : out std_logic; DO23 : out std_logic; + DO24 : out std_logic; DO25 : out std_logic; + DO26 : out std_logic; DO27 : out std_logic; + DO28 : out std_logic; DO29 : out std_logic; + DO30 : out std_logic; DO31 : out std_logic; + DO32 : out std_logic; DO33 : out std_logic; + DO34 : out std_logic; DO35 : out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_36x128_OutReg_Counter.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t17 : AND2 + port map (A => WrEn, B => invout_1, Z => wren_i); + + INV_1 : INV + port map (A => full_i, Z => invout_1); + + AND2_t16 : AND2 + port map (A => RdEn, B => invout_0, Z => rden_i); + + INV_0 : INV + port map (A => empty_i, Z => invout_0); + + OR2_t15 : OR2 + port map (A => Reset, B => RPReset, Z => rRst); + + XOR2_t14 : XOR2 + port map (A => wcount_0, B => wcount_1, Z => w_gdata_0); + + XOR2_t13 : XOR2 + port map (A => wcount_1, B => wcount_2, Z => w_gdata_1); + + XOR2_t12 : XOR2 + port map (A => wcount_2, B => wcount_3, Z => w_gdata_2); + + XOR2_t11 : XOR2 + port map (A => wcount_3, B => wcount_4, Z => w_gdata_3); + + XOR2_t10 : XOR2 + port map (A => wcount_4, B => wcount_5, Z => w_gdata_4); + + XOR2_t9 : XOR2 + port map (A => wcount_5, B => wcount_6, Z => w_gdata_5); + + XOR2_t8 : XOR2 + port map (A => wcount_6, B => wcount_7, Z => w_gdata_6); + + XOR2_t7 : XOR2 + port map (A => rcount_0, B => rcount_1, Z => r_gdata_0); + + XOR2_t6 : XOR2 + port map (A => rcount_1, B => rcount_2, Z => r_gdata_1); + + XOR2_t5 : XOR2 + port map (A => rcount_2, B => rcount_3, Z => r_gdata_2); + + XOR2_t4 : XOR2 + port map (A => rcount_3, B => rcount_4, Z => r_gdata_3); + + XOR2_t3 : XOR2 + port map (A => rcount_4, B => rcount_5, Z => r_gdata_4); + + XOR2_t2 : XOR2 + port map (A => rcount_5, B => rcount_6, Z => r_gdata_5); + + XOR2_t1 : XOR2 + port map (A => rcount_6, B => rcount_7, Z => r_gdata_6); + + LUT4_19 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r24, AD2 => w_gcount_r25, + AD1 => w_gcount_r26, AD0 => w_gcount_r27, + DO0 => w_g2b_xor_cluster_0); + + LUT4_18 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r20, AD2 => w_gcount_r21, + AD1 => w_gcount_r22, AD0 => w_gcount_r23, + DO0 => w_g2b_xor_cluster_1); + + LUT4_17 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r26, AD2 => w_gcount_r27, AD1 => scuba_vlo, + AD0 => scuba_vlo, DO0 => wcount_r6); + + LUT4_16 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r25, AD2 => w_gcount_r26, + AD1 => w_gcount_r27, AD0 => scuba_vlo, DO0 => wcount_r5); + + LUT4_15 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r23, AD2 => w_gcount_r24, + AD1 => w_gcount_r25, AD0 => wcount_r6, DO0 => wcount_r3); + + LUT4_14 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r22, AD2 => w_gcount_r23, + AD1 => w_gcount_r24, AD0 => wcount_r5, DO0 => wcount_r2); + + LUT4_13 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r21, AD2 => w_gcount_r22, + AD1 => w_gcount_r23, AD0 => w_g2b_xor_cluster_0, DO0 => wcount_r1); + + LUT4_12 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_g2b_xor_cluster_0, AD2 => w_g2b_xor_cluster_1, + AD1 => scuba_vlo, AD0 => scuba_vlo, DO0 => wcount_r0); + + LUT4_11 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w24, AD2 => r_gcount_w25, + AD1 => r_gcount_w26, AD0 => r_gcount_w27, + DO0 => r_g2b_xor_cluster_0); + + LUT4_10 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w20, AD2 => r_gcount_w21, + AD1 => r_gcount_w22, AD0 => r_gcount_w23, + DO0 => r_g2b_xor_cluster_1); + + LUT4_9 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w26, AD2 => r_gcount_w27, AD1 => scuba_vlo, + AD0 => scuba_vlo, DO0 => rcount_w6); + + LUT4_8 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w25, AD2 => r_gcount_w26, + AD1 => r_gcount_w27, AD0 => scuba_vlo, DO0 => rcount_w5); + + LUT4_7 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w23, AD2 => r_gcount_w24, + AD1 => r_gcount_w25, AD0 => rcount_w6, DO0 => rcount_w3); + + LUT4_6 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w22, AD2 => r_gcount_w23, + AD1 => r_gcount_w24, AD0 => rcount_w5, DO0 => rcount_w2); + + LUT4_5 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w21, AD2 => r_gcount_w22, + AD1 => r_gcount_w23, AD0 => r_g2b_xor_cluster_0, DO0 => rcount_w1); + + LUT4_4 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_g2b_xor_cluster_0, AD2 => r_g2b_xor_cluster_1, + AD1 => scuba_vlo, AD0 => scuba_vlo, DO0 => rcount_w0); + + XOR2_t0 : XOR2 + port map (A => wptr_7, B => r_gcount_w27, Z => wfill_sub_msb); + + LUT4_3 : ROM16X1A + generic map (initval => X"0410") + port map (AD3 => rptr_7, AD2 => rcount_7, AD1 => w_gcount_r27, + AD0 => scuba_vlo, DO0 => empty_cmp_set); + + LUT4_2 : ROM16X1A + generic map (initval => X"1004") + port map (AD3 => rptr_7, AD2 => rcount_7, AD1 => w_gcount_r27, + AD0 => scuba_vlo, DO0 => empty_cmp_clr); + + LUT4_1 : ROM16X1A + generic map (initval => X"0140") + port map (AD3 => wptr_7, AD2 => wcount_7, AD1 => r_gcount_w27, + AD0 => scuba_vlo, DO0 => full_cmp_set); + + LUT4_0 : ROM16X1A + generic map (initval => X"4001") + port map (AD3 => wptr_7, AD2 => wcount_7, AD1 => r_gcount_w27, + AD0 => scuba_vlo, DO0 => full_cmp_clr); + + pdp_ram_0_0_0 : PDPW16KC + generic map (CSDECODE_R => "0b001", CSDECODE_W => "0b001", GSR => "DISABLED", + REGMODE => "OUTREG", DATA_WIDTH_R => 36, DATA_WIDTH_W => 36) + port map (DI0 => Data(0), DI1 => Data(1), DI2 => Data(2), DI3 => Data(3), + DI4 => Data(4), DI5 => Data(5), DI6 => Data(6), DI7 => Data(7), + DI8 => Data(8), DI9 => Data(9), DI10 => Data(10), DI11 => Data(11), + DI12 => Data(12), DI13 => Data(13), DI14 => Data(14), + DI15 => Data(15), DI16 => Data(16), DI17 => Data(17), + DI18 => Data(18), DI19 => Data(19), DI20 => Data(20), + DI21 => Data(21), DI22 => Data(22), DI23 => Data(23), + DI24 => Data(24), DI25 => Data(25), DI26 => Data(26), + DI27 => Data(27), DI28 => Data(28), DI29 => Data(29), + DI30 => Data(30), DI31 => Data(31), DI32 => Data(32), + DI33 => Data(33), DI34 => Data(34), DI35 => Data(35), ADW0 => wptr_0, + ADW1 => wptr_1, ADW2 => wptr_2, ADW3 => wptr_3, ADW4 => wptr_4, + ADW5 => wptr_5, ADW6 => wptr_6, ADW7 => scuba_vlo, ADW8 => scuba_vlo, + BE0 => scuba_vhi, BE1 => scuba_vhi, BE2 => scuba_vhi, + BE3 => scuba_vhi, CEW => wren_i, CLKW => WrClock, CSW0 => scuba_vhi, + CSW1 => scuba_vlo, CSW2 => scuba_vlo, ADR0 => scuba_vlo, + ADR1 => scuba_vlo, ADR2 => scuba_vlo, ADR3 => scuba_vlo, + ADR4 => scuba_vlo, ADR5 => rptr_0, ADR6 => rptr_1, ADR7 => rptr_2, + ADR8 => rptr_3, ADR9 => rptr_4, ADR10 => rptr_5, ADR11 => rptr_6, + ADR12 => scuba_vlo, ADR13 => scuba_vlo, CER => scuba_vhi, + CLKR => RdClock, CSR0 => rden_i, CSR1 => scuba_vlo, + CSR2 => scuba_vlo, RST => Reset, DO0 => Q(18), DO1 => Q(19), + DO2 => Q(20), DO3 => Q(21), DO4 => Q(22), DO5 => Q(23), DO6 => Q(24), + DO7 => Q(25), DO8 => Q(26), DO9 => Q(27), DO10 => Q(28), DO11 => Q(29), + DO12 => Q(30), DO13 => Q(31), DO14 => Q(32), DO15 => Q(33), + DO16 => Q(34), DO17 => Q(35), DO18 => Q(0), DO19 => Q(1), DO20 => Q(2), + DO21 => Q(3), DO22 => Q(4), DO23 => Q(5), DO24 => Q(6), DO25 => Q(7), + DO26 => Q(8), DO27 => Q(9), DO28 => Q(10), DO29 => Q(11), + DO30 => Q(12), DO31 => Q(13), DO32 => Q(14), DO33 => Q(15), + DO34 => Q(16), DO35 => Q(17)); + + FF_89 : FD1P3BX + port map (D => iwcount_0, SP => wren_i, CK => WrClock, PD => Reset, + Q => wcount_0); + + FF_88 : FD1P3DX + port map (D => iwcount_1, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_1); + + FF_87 : FD1P3DX + port map (D => iwcount_2, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_2); + + FF_86 : FD1P3DX + port map (D => iwcount_3, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_3); + + FF_85 : FD1P3DX + port map (D => iwcount_4, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_4); + + FF_84 : FD1P3DX + port map (D => iwcount_5, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_5); + + FF_83 : FD1P3DX + port map (D => iwcount_6, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_6); + + FF_82 : FD1P3DX + port map (D => iwcount_7, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_7); + + FF_81 : FD1P3DX + port map (D => w_gdata_0, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_0); + + FF_80 : FD1P3DX + port map (D => w_gdata_1, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_1); + + FF_79 : FD1P3DX + port map (D => w_gdata_2, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_2); + + FF_78 : FD1P3DX + port map (D => w_gdata_3, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_3); + + FF_77 : FD1P3DX + port map (D => w_gdata_4, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_4); + + FF_76 : FD1P3DX + port map (D => w_gdata_5, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_5); + + FF_75 : FD1P3DX + port map (D => w_gdata_6, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_6); + + FF_74 : FD1P3DX + port map (D => wcount_7, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_7); + + FF_73 : FD1P3DX + port map (D => wcount_0, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_0); + + FF_72 : FD1P3DX + port map (D => wcount_1, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_1); + + FF_71 : FD1P3DX + port map (D => wcount_2, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_2); + + FF_70 : FD1P3DX + port map (D => wcount_3, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_3); + + FF_69 : FD1P3DX + port map (D => wcount_4, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_4); + + FF_68 : FD1P3DX + port map (D => wcount_5, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_5); + + FF_67 : FD1P3DX + port map (D => wcount_6, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_6); + + FF_66 : FD1P3DX + port map (D => wcount_7, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_7); + + FF_65 : FD1P3BX + port map (D => ircount_0, SP => rden_i, CK => RdClock, PD => rRst, + Q => rcount_0); + + FF_64 : FD1P3DX + port map (D => ircount_1, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_1); + + FF_63 : FD1P3DX + port map (D => ircount_2, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_2); + + FF_62 : FD1P3DX + port map (D => ircount_3, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_3); + + FF_61 : FD1P3DX + port map (D => ircount_4, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_4); + + FF_60 : FD1P3DX + port map (D => ircount_5, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_5); + + FF_59 : FD1P3DX + port map (D => ircount_6, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_6); + + FF_58 : FD1P3DX + port map (D => ircount_7, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_7); + + FF_57 : FD1P3DX + port map (D => r_gdata_0, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_0); + + FF_56 : FD1P3DX + port map (D => r_gdata_1, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_1); + + FF_55 : FD1P3DX + port map (D => r_gdata_2, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_2); + + FF_54 : FD1P3DX + port map (D => r_gdata_3, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_3); + + FF_53 : FD1P3DX + port map (D => r_gdata_4, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_4); + + FF_52 : FD1P3DX + port map (D => r_gdata_5, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_5); + + FF_51 : FD1P3DX + port map (D => r_gdata_6, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_6); + + FF_50 : FD1P3DX + port map (D => rcount_7, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_7); + + FF_49 : FD1P3DX + port map (D => rcount_0, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_0); + + FF_48 : FD1P3DX + port map (D => rcount_1, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_1); + + FF_47 : FD1P3DX + port map (D => rcount_2, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_2); + + FF_46 : FD1P3DX + port map (D => rcount_3, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_3); + + FF_45 : FD1P3DX + port map (D => rcount_4, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_4); + + FF_44 : FD1P3DX + port map (D => rcount_5, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_5); + + FF_43 : FD1P3DX + port map (D => rcount_6, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_6); + + FF_42 : FD1P3DX + port map (D => rcount_7, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_7); + + FF_41 : FD1S3DX + port map (D => w_gcount_0, CK => RdClock, CD => Reset, Q => w_gcount_r0); + + FF_40 : FD1S3DX + port map (D => w_gcount_1, CK => RdClock, CD => Reset, Q => w_gcount_r1); + + FF_39 : FD1S3DX + port map (D => w_gcount_2, CK => RdClock, CD => Reset, Q => w_gcount_r2); + + FF_38 : FD1S3DX + port map (D => w_gcount_3, CK => RdClock, CD => Reset, Q => w_gcount_r3); + + FF_37 : FD1S3DX + port map (D => w_gcount_4, CK => RdClock, CD => Reset, Q => w_gcount_r4); + + FF_36 : FD1S3DX + port map (D => w_gcount_5, CK => RdClock, CD => Reset, Q => w_gcount_r5); + + FF_35 : FD1S3DX + port map (D => w_gcount_6, CK => RdClock, CD => Reset, Q => w_gcount_r6); + + FF_34 : FD1S3DX + port map (D => w_gcount_7, CK => RdClock, CD => Reset, Q => w_gcount_r7); + + FF_33 : FD1S3DX + port map (D => r_gcount_0, CK => WrClock, CD => rRst, Q => r_gcount_w0); + + FF_32 : FD1S3DX + port map (D => r_gcount_1, CK => WrClock, CD => rRst, Q => r_gcount_w1); + + FF_31 : FD1S3DX + port map (D => r_gcount_2, CK => WrClock, CD => rRst, Q => r_gcount_w2); + + FF_30 : FD1S3DX + port map (D => r_gcount_3, CK => WrClock, CD => rRst, Q => r_gcount_w3); + + FF_29 : FD1S3DX + port map (D => r_gcount_4, CK => WrClock, CD => rRst, Q => r_gcount_w4); + + FF_28 : FD1S3DX + port map (D => r_gcount_5, CK => WrClock, CD => rRst, Q => r_gcount_w5); + + FF_27 : FD1S3DX + port map (D => r_gcount_6, CK => WrClock, CD => rRst, Q => r_gcount_w6); + + FF_26 : FD1S3DX + port map (D => r_gcount_7, CK => WrClock, CD => rRst, Q => r_gcount_w7); + + FF_25 : FD1S3DX + port map (D => w_gcount_r0, CK => RdClock, CD => Reset, + Q => w_gcount_r20); + + FF_24 : FD1S3DX + port map (D => w_gcount_r1, CK => RdClock, CD => Reset, + Q => w_gcount_r21); + + FF_23 : FD1S3DX + port map (D => w_gcount_r2, CK => RdClock, CD => Reset, + Q => w_gcount_r22); + + FF_22 : FD1S3DX + port map (D => w_gcount_r3, CK => RdClock, CD => Reset, + Q => w_gcount_r23); + + FF_21 : FD1S3DX + port map (D => w_gcount_r4, CK => RdClock, CD => Reset, + Q => w_gcount_r24); + + FF_20 : FD1S3DX + port map (D => w_gcount_r5, CK => RdClock, CD => Reset, + Q => w_gcount_r25); + + FF_19 : FD1S3DX + port map (D => w_gcount_r6, CK => RdClock, CD => Reset, + Q => w_gcount_r26); + + FF_18 : FD1S3DX + port map (D => w_gcount_r7, CK => RdClock, CD => Reset, + Q => w_gcount_r27); + + FF_17 : FD1S3DX + port map (D => r_gcount_w0, CK => WrClock, CD => rRst, Q => r_gcount_w20); + + FF_16 : FD1S3DX + port map (D => r_gcount_w1, CK => WrClock, CD => rRst, Q => r_gcount_w21); + + FF_15 : FD1S3DX + port map (D => r_gcount_w2, CK => WrClock, CD => rRst, Q => r_gcount_w22); + + FF_14 : FD1S3DX + port map (D => r_gcount_w3, CK => WrClock, CD => rRst, Q => r_gcount_w23); + + FF_13 : FD1S3DX + port map (D => r_gcount_w4, CK => WrClock, CD => rRst, Q => r_gcount_w24); + + FF_12 : FD1S3DX + port map (D => r_gcount_w5, CK => WrClock, CD => rRst, Q => r_gcount_w25); + + FF_11 : FD1S3DX + port map (D => r_gcount_w6, CK => WrClock, CD => rRst, Q => r_gcount_w26); + + FF_10 : FD1S3DX + port map (D => r_gcount_w7, CK => WrClock, CD => rRst, Q => r_gcount_w27); + + FF_9 : FD1S3DX + port map (D => wfill_sub_0, CK => WrClock, CD => Reset, Q => WCNT(0)); + + FF_8 : FD1S3DX + port map (D => wfill_sub_1, CK => WrClock, CD => Reset, Q => WCNT(1)); + + FF_7 : FD1S3DX + port map (D => wfill_sub_2, CK => WrClock, CD => Reset, Q => WCNT(2)); + + FF_6 : FD1S3DX + port map (D => wfill_sub_3, CK => WrClock, CD => Reset, Q => WCNT(3)); + + FF_5 : FD1S3DX + port map (D => wfill_sub_4, CK => WrClock, CD => Reset, Q => WCNT(4)); + + FF_4 : FD1S3DX + port map (D => wfill_sub_5, CK => WrClock, CD => Reset, Q => WCNT(5)); + + FF_3 : FD1S3DX + port map (D => wfill_sub_6, CK => WrClock, CD => Reset, Q => WCNT(6)); + + FF_2 : FD1S3DX + port map (D => wfill_sub_7, CK => WrClock, CD => Reset, Q => WCNT(7)); + + FF_1 : FD1S3BX + port map (D => empty_d, CK => RdClock, PD => rRst, Q => empty_i); + + FF_0 : FD1S3DX + port map (D => full_d, CK => WrClock, CD => Reset, Q => full_i); + + w_gctr_cia : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo, + B1 => scuba_vhi, CI => scuba_vlo, COUT => w_gctr_ci, S0 => open, + S1 => open); + + w_gctr_0 : CU2 + port map (CI => w_gctr_ci, PC0 => wcount_0, PC1 => wcount_1, CO => co0, + NC0 => iwcount_0, NC1 => iwcount_1); + + w_gctr_1 : CU2 + port map (CI => co0, PC0 => wcount_2, PC1 => wcount_3, CO => co1, + NC0 => iwcount_2, NC1 => iwcount_3); + + w_gctr_2 : CU2 + port map (CI => co1, PC0 => wcount_4, PC1 => wcount_5, CO => co2, + NC0 => iwcount_4, NC1 => iwcount_5); + + w_gctr_3 : CU2 + port map (CI => co2, PC0 => wcount_6, PC1 => wcount_7, CO => co3, + NC0 => iwcount_6, NC1 => iwcount_7); + + r_gctr_cia : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo, + B1 => scuba_vhi, CI => scuba_vlo, COUT => r_gctr_ci, S0 => open, + S1 => open); + + r_gctr_0 : CU2 + port map (CI => r_gctr_ci, PC0 => rcount_0, PC1 => rcount_1, CO => co0_1, + NC0 => ircount_0, NC1 => ircount_1); + + r_gctr_1 : CU2 + port map (CI => co0_1, PC0 => rcount_2, PC1 => rcount_3, CO => co1_1, + NC0 => ircount_2, NC1 => ircount_3); + + r_gctr_2 : CU2 + port map (CI => co1_1, PC0 => rcount_4, PC1 => rcount_5, CO => co2_1, + NC0 => ircount_4, NC1 => ircount_5); + + r_gctr_3 : CU2 + port map (CI => co2_1, PC0 => rcount_6, PC1 => rcount_7, CO => co3_1, + NC0 => ircount_6, NC1 => ircount_7); + + scuba_vhi_inst : VHI + port map (Z => scuba_vhi); + + wfill_0 : FSUB2B + port map (A0 => scuba_vhi, A1 => wptr_0, B0 => scuba_vlo, + B1 => rcount_w0, BI => scuba_vlo, BOUT => co0_2, S0 => open, + S1 => wfill_sub_0); + + wfill_1 : FSUB2B + port map (A0 => wptr_1, A1 => wptr_2, B0 => rcount_w1, B1 => rcount_w2, + BI => co0_2, BOUT => co1_2, S0 => wfill_sub_1, S1 => wfill_sub_2); + + wfill_2 : FSUB2B + port map (A0 => wptr_3, A1 => wptr_4, B0 => rcount_w3, + B1 => r_g2b_xor_cluster_0, BI => co1_2, BOUT => co2_2, + S0 => wfill_sub_3, S1 => wfill_sub_4); + + wfill_3 : FSUB2B + port map (A0 => wptr_5, A1 => wptr_6, B0 => rcount_w5, B1 => rcount_w6, + BI => co2_2, BOUT => co3_2, S0 => wfill_sub_5, S1 => wfill_sub_6); + + wfill_4 : FSUB2B + port map (A0 => wfill_sub_msb, A1 => scuba_vlo, B0 => scuba_vlo, + B1 => scuba_vlo, BI => co3_2, BOUT => open, S0 => wfill_sub_7, + S1 => open); + + empty_cmp_ci_a : FADD2B + port map (A0 => scuba_vlo, A1 => rden_i, B0 => scuba_vlo, B1 => rden_i, + CI => scuba_vlo, COUT => cmp_ci, S0 => open, S1 => open); + + empty_cmp_0 : AGEB2 + port map (A0 => rcount_0, A1 => rcount_1, B0 => wcount_r0, + B1 => wcount_r1, CI => cmp_ci, GE => co0_3); + + empty_cmp_1 : AGEB2 + port map (A0 => rcount_2, A1 => rcount_3, B0 => wcount_r2, + B1 => wcount_r3, CI => co0_3, GE => co1_3); + + empty_cmp_2 : AGEB2 + port map (A0 => rcount_4, A1 => rcount_5, B0 => w_g2b_xor_cluster_0, + B1 => wcount_r5, CI => co1_3, GE => co2_3); + + empty_cmp_3 : AGEB2 + port map (A0 => rcount_6, A1 => empty_cmp_set, B0 => wcount_r6, + B1 => empty_cmp_clr, CI => co2_3, GE => empty_d_c); + + a0 : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo, + B1 => scuba_vlo, CI => empty_d_c, COUT => open, S0 => empty_d, + S1 => open); + + full_cmp_ci_a : FADD2B + port map (A0 => scuba_vlo, A1 => wren_i, B0 => scuba_vlo, B1 => wren_i, + CI => scuba_vlo, COUT => cmp_ci_1, S0 => open, S1 => open); + + full_cmp_0 : AGEB2 + port map (A0 => wcount_0, A1 => wcount_1, B0 => rcount_w0, + B1 => rcount_w1, CI => cmp_ci_1, GE => co0_4); + + full_cmp_1 : AGEB2 + port map (A0 => wcount_2, A1 => wcount_3, B0 => rcount_w2, + B1 => rcount_w3, CI => co0_4, GE => co1_4); + + full_cmp_2 : AGEB2 + port map (A0 => wcount_4, A1 => wcount_5, B0 => r_g2b_xor_cluster_0, + B1 => rcount_w5, CI => co1_4, GE => co2_4); + + full_cmp_3 : AGEB2 + port map (A0 => wcount_6, A1 => full_cmp_set, B0 => rcount_w6, + B1 => full_cmp_clr, CI => co2_4, GE => full_d_c); + + scuba_vlo_inst : VLO + port map (Z => scuba_vlo); + + a1 : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo, + B1 => scuba_vlo, CI => full_d_c, COUT => open, S0 => full_d, + S1 => open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of FIFO_36x128_OutReg_Counter is + for Structure + for all : AGEB2 use entity ecp3.AGEB2(V); end for; + for all : AND2 use entity ecp3.AND2(V); end for; + for all : CU2 use entity ecp3.CU2(V); end for; + for all : FADD2B use entity ecp3.FADD2B(V); end for; + for all : FSUB2B use entity ecp3.FSUB2B(V); end for; + for all : FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all : FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all : FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all : FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all : INV use entity ecp3.INV(V); end for; + for all : OR2 use entity ecp3.OR2(V); end for; + for all : ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all : VHI use entity ecp3.VHI(V); end for; + for all : VLO use entity ecp3.VLO(V); end for; + for all : XOR2 use entity ecp3.XOR2(V); end for; + for all : PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/tdc_releases/tdc_v1.6/LogicAnalyser.vhd b/tdc_releases/tdc_v1.6/LogicAnalyser.vhd new file mode 100644 index 0000000..f06bfc4 --- /dev/null +++ b/tdc_releases/tdc_v1.6/LogicAnalyser.vhd @@ -0,0 +1,79 @@ +------------------------------------------------------------------------------- +-- Title : Logic Analyser Signals +-- Project : +------------------------------------------------------------------------------- +-- File : LogicAnalyser.vhd +-- Author : cugur@gsi.de +-- Created : 2012-10-26 +-- Last update: 2013-03-01 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; + +entity LogicAnalyser is + generic ( + CHANNEL_NUMBER : integer range 2 to 65); + + port ( + CLK : in std_logic; + RESET : in std_logic; +-- + DATA_IN : in std_logic_vector(3*32-1 downto 0); + CONTROL_IN : in std_logic_vector(3 downto 0); + DATA_OUT : out std_logic_vector(15 downto 0) + ); + +end LogicAnalyser; + + +architecture behavioral of LogicAnalyser is + + signal mux_out : std_logic_vector(15 downto 0); + +begin -- behavioral + +------------------------------------------------------------------------------- +-- Logic Analyser Signals +------------------------------------------------------------------------------- + REG_LOGIC_ANALYSER_OUTPUT : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + mux_out <= (others => '0'); + elsif CONTROL_IN = x"1" then -- TRBNET connections debugging + mux_out(7 downto 0) <= DATA_IN(7 downto 0); --fsm_debug; + mux_out(8) <= DATA_IN(8); --REFERENCE_TIME; + mux_out(9) <= DATA_IN(9); --VALID_TIMING_TRG_IN; + mux_out(10) <= DATA_IN(10); --VALID_NOTIMING_TRG_IN; + mux_out(11) <= DATA_IN(11); --INVALID_TRG_IN; + mux_out(12) <= DATA_IN(12); --TRG_DATA_VALID_IN; + mux_out(13) <= DATA_IN(13); --data_wr_reg; + mux_out(14) <= DATA_IN(14); --data_finished_reg; + mux_out(15) <= DATA_IN(15); --trg_release_reg; + elsif CONTROL_IN = x"2" then -- Reference channel debugging + mux_out <= DATA_IN(31 downto 16); --ref_debug_i(15 downto 0); + elsif CONTROL_IN = x"3" then -- Data out + mux_out(7 downto 0) <= DATA_IN(7 downto 0); --fsm_debug; + mux_out(8) <= DATA_IN(8); --REFERENCE_TIME; + mux_out(9) <= DATA_IN(13); --data_wr_reg; + mux_out(15 downto 10) <= DATA_IN(37 downto 32); --data_out_reg(27 downto 22); + + --elsif CONTROL_IN = x"4" then -- channel debugging + -- mux_out <= DATA_IN(); --ch_debug_i(1)(15 downto 0); + end if; + end if; + end process REG_LOGIC_ANALYSER_OUTPUT; + + DATA_OUT <= mux_out; + + +end behavioral; diff --git a/tdc_releases/tdc_v1.6/ROM4_Encoder.vhd b/tdc_releases/tdc_v1.6/ROM4_Encoder.vhd new file mode 100644 index 0000000..e39b95c --- /dev/null +++ b/tdc_releases/tdc_v1.6/ROM4_Encoder.vhd @@ -0,0 +1,262 @@ +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 5.0 +--/opt/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 10 -data_width 8 -num_rows 1024 -outdata REGISTERED -memfile /home/cugur/Projects/encoder/encoder_304_ROM4/source/rom_encoder.mem -memformat orca -cascade -1 -e + +-- Mon Mar 4 14:23:33 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity ROM4_Encoder is + port ( + Address : in std_logic_vector(9 downto 0); + OutClock : in std_logic; + OutClockEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(7 downto 0)); +end ROM4_Encoder; + +architecture Structure of ROM4_Encoder is + + -- internal signal declarations + signal scuba_vhi : std_logic; + signal scuba_vlo : std_logic; + + -- local component declarations + component VHI + port (Z : out std_logic); + end component; + component VLO + port (Z : out std_logic); + end component; + component DP16KC + generic (INITVAL_3F : in string; INITVAL_3E : in string; + INITVAL_3D : in string; INITVAL_3C : in string; + INITVAL_3B : in string; INITVAL_3A : in string; + INITVAL_39 : in string; INITVAL_38 : in string; + INITVAL_37 : in string; INITVAL_36 : in string; + INITVAL_35 : in string; INITVAL_34 : in string; + INITVAL_33 : in string; INITVAL_32 : in string; + INITVAL_31 : in string; INITVAL_30 : in string; + INITVAL_2F : in string; INITVAL_2E : in string; + INITVAL_2D : in string; INITVAL_2C : in string; + INITVAL_2B : in string; INITVAL_2A : in string; + INITVAL_29 : in string; INITVAL_28 : in string; + INITVAL_27 : in string; INITVAL_26 : in string; + INITVAL_25 : in string; INITVAL_24 : in string; + INITVAL_23 : in string; INITVAL_22 : in string; + INITVAL_21 : in string; INITVAL_20 : in string; + INITVAL_1F : in string; INITVAL_1E : in string; + INITVAL_1D : in string; INITVAL_1C : in string; + INITVAL_1B : in string; INITVAL_1A : in string; + INITVAL_19 : in string; INITVAL_18 : in string; + INITVAL_17 : in string; INITVAL_16 : in string; + INITVAL_15 : in string; INITVAL_14 : in string; + INITVAL_13 : in string; INITVAL_12 : in string; + INITVAL_11 : in string; INITVAL_10 : in string; + INITVAL_0F : in string; INITVAL_0E : in string; + INITVAL_0D : in string; INITVAL_0C : in string; + INITVAL_0B : in string; INITVAL_0A : in string; + INITVAL_09 : in string; INITVAL_08 : in string; + INITVAL_07 : in string; INITVAL_06 : in string; + INITVAL_05 : in string; INITVAL_04 : in string; + INITVAL_03 : in string; INITVAL_02 : in string; + INITVAL_01 : in string; INITVAL_00 : in string; + GSR : in string; WRITEMODE_B : in string; + WRITEMODE_A : in string; CSDECODE_B : in string; + CSDECODE_A : in string; REGMODE_B : in string; + REGMODE_A : in string; DATA_WIDTH_B : in integer; + DATA_WIDTH_A : in integer); + port (DIA0 : in std_logic; DIA1 : in std_logic; + DIA2 : in std_logic; DIA3 : in std_logic; + DIA4 : in std_logic; DIA5 : in std_logic; + DIA6 : in std_logic; DIA7 : in std_logic; + DIA8 : in std_logic; DIA9 : in std_logic; + DIA10 : in std_logic; DIA11 : in std_logic; + DIA12 : in std_logic; DIA13 : in std_logic; + DIA14 : in std_logic; DIA15 : in std_logic; + DIA16 : in std_logic; DIA17 : in std_logic; + ADA0 : in std_logic; ADA1 : in std_logic; + ADA2 : in std_logic; ADA3 : in std_logic; + ADA4 : in std_logic; ADA5 : in std_logic; + ADA6 : in std_logic; ADA7 : in std_logic; + ADA8 : in std_logic; ADA9 : in std_logic; + ADA10 : in std_logic; ADA11 : in std_logic; + ADA12 : in std_logic; ADA13 : in std_logic; + CEA : in std_logic; CLKA : in std_logic; OCEA : in std_logic; + WEA : in std_logic; CSA0 : in std_logic; CSA1 : in std_logic; + CSA2 : in std_logic; RSTA : in std_logic; + DIB0 : in std_logic; DIB1 : in std_logic; + DIB2 : in std_logic; DIB3 : in std_logic; + DIB4 : in std_logic; DIB5 : in std_logic; + DIB6 : in std_logic; DIB7 : in std_logic; + DIB8 : in std_logic; DIB9 : in std_logic; + DIB10 : in std_logic; DIB11 : in std_logic; + DIB12 : in std_logic; DIB13 : in std_logic; + DIB14 : in std_logic; DIB15 : in std_logic; + DIB16 : in std_logic; DIB17 : in std_logic; + ADB0 : in std_logic; ADB1 : in std_logic; + ADB2 : in std_logic; ADB3 : in std_logic; + ADB4 : in std_logic; ADB5 : in std_logic; + ADB6 : in std_logic; ADB7 : in std_logic; + ADB8 : in std_logic; ADB9 : in std_logic; + ADB10 : in std_logic; ADB11 : in std_logic; + ADB12 : in std_logic; ADB13 : in std_logic; + CEB : in std_logic; CLKB : in std_logic; OCEB : in std_logic; + WEB : in std_logic; CSB0 : in std_logic; CSB1 : in std_logic; + CSB2 : in std_logic; RSTB : in std_logic; + DOA0 : out std_logic; DOA1 : out std_logic; + DOA2 : out std_logic; DOA3 : out std_logic; + DOA4 : out std_logic; DOA5 : out std_logic; + DOA6 : out std_logic; DOA7 : out std_logic; + DOA8 : out std_logic; DOA9 : out std_logic; + DOA10 : out std_logic; DOA11 : out std_logic; + DOA12 : out std_logic; DOA13 : out std_logic; + DOA14 : out std_logic; DOA15 : out std_logic; + DOA16 : out std_logic; DOA17 : out std_logic; + DOB0 : out std_logic; DOB1 : out std_logic; + DOB2 : out std_logic; DOB3 : out std_logic; + DOB4 : out std_logic; DOB5 : out std_logic; + DOB6 : out std_logic; DOB7 : out std_logic; + DOB8 : out std_logic; DOB9 : out std_logic; + DOB10 : out std_logic; DOB11 : out std_logic; + DOB12 : out std_logic; DOB13 : out std_logic; + DOB14 : out std_logic; DOB15 : out std_logic; + DOB16 : out std_logic; DOB17 : out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute MEM_LPC_FILE of ROM4_Encoder_0_0_0 : label is "ROM4_Encoder.lpc"; + attribute MEM_INIT_FILE of ROM4_Encoder_0_0_0 : label is "rom_encoder.mem"; + attribute RESETMODE of ROM4_Encoder_0_0_0 : label is "SYNC"; + +begin + -- component instantiation statements + scuba_vhi_inst : VHI + port map (Z => scuba_vhi); + + scuba_vlo_inst : VLO + port map (Z => scuba_vlo); + + ROM4_Encoder_0_0_0 : DP16KC + generic map (INITVAL_3F => "0x00080000400000000001000800000100001000020008000002000800000200080000020008000003", + INITVAL_3E => "0x00080000800008000003000800008000080000030008000080000800000300080000800008000004", + INITVAL_3D => "0x00080000800008000080000800008000080000040008000080000800008000080000800008000004", + INITVAL_3C => "0x00080000800008000080000800008000080000040008000080000800008000080000800008000005", + INITVAL_3B => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000005", + INITVAL_3A => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000005", + INITVAL_39 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000005", + INITVAL_38 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000046", + INITVAL_37 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_36 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000006", + INITVAL_35 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_34 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000006", + INITVAL_33 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_32 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000006", + INITVAL_31 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_30 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000047", + INITVAL_2F => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_2E => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_2D => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_2C => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000007", + INITVAL_2B => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_2A => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_29 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_28 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000047", + INITVAL_27 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_26 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_25 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_24 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_23 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_22 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_21 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_20 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_1F => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_1E => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_1D => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_1C => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_1B => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_1A => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_19 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_18 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_17 => "0x00047000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_16 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_15 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_14 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_13 => "0x00007000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_12 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_11 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_10 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_0F => "0x00047000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_0E => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_0D => "0x00006000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_0C => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_0B => "0x00006000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_0A => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_09 => "0x00006000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_08 => "0x00080000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_07 => "0x00046000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_06 => "0x00005000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_05 => "0x00005000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_04 => "0x00005000800008000080000800008000080000800008000080000800008000080000800008000080", + INITVAL_03 => "0x00005000800008000080000800008000080000800000400080000800008000080000800008000080", + INITVAL_02 => "0x00004000800008000080000800008000080000800000400080000800008000080000800008000080", + INITVAL_01 => "0x00004000800008000080000030008000080000800000300080000800008000003000800008000080", + INITVAL_00 => "0x00003000800000200080000020008000002000800000200001000010008000001000800004000080", + CSDECODE_B => "0b111", CSDECODE_A => "0b000", WRITEMODE_B => "NORMAL", + WRITEMODE_A => "NORMAL", GSR => "DISABLED", REGMODE_B => "NOREG", + REGMODE_A => "OUTREG", DATA_WIDTH_B => 18, DATA_WIDTH_A => 18) + port map (DIA0 => scuba_vlo, DIA1 => scuba_vlo, DIA2 => scuba_vlo, + DIA3 => scuba_vlo, DIA4 => scuba_vlo, DIA5 => scuba_vlo, + DIA6 => scuba_vlo, DIA7 => scuba_vlo, DIA8 => scuba_vlo, + DIA9 => scuba_vlo, DIA10 => scuba_vlo, DIA11 => scuba_vlo, + DIA12 => scuba_vlo, DIA13 => scuba_vlo, DIA14 => scuba_vlo, + DIA15 => scuba_vlo, DIA16 => scuba_vlo, DIA17 => scuba_vlo, + ADA0 => scuba_vlo, ADA1 => scuba_vlo, ADA2 => scuba_vlo, + ADA3 => scuba_vlo, ADA4 => Address(0), ADA5 => Address(1), + ADA6 => Address(2), ADA7 => Address(3), ADA8 => Address(4), + ADA9 => Address(5), ADA10 => Address(6), ADA11 => Address(7), + ADA12 => Address(8), ADA13 => Address(9), CEA => OutClockEn, + CLKA => OutClock, OCEA => OutClockEn, WEA => scuba_vlo, + CSA0 => scuba_vlo, CSA1 => scuba_vlo, CSA2 => scuba_vlo, + RSTA => Reset, DIB0 => scuba_vlo, DIB1 => scuba_vlo, + DIB2 => scuba_vlo, DIB3 => scuba_vlo, DIB4 => scuba_vlo, + DIB5 => scuba_vlo, DIB6 => scuba_vlo, DIB7 => scuba_vlo, + DIB8 => scuba_vlo, DIB9 => scuba_vlo, DIB10 => scuba_vlo, + DIB11 => scuba_vlo, DIB12 => scuba_vlo, DIB13 => scuba_vlo, + DIB14 => scuba_vlo, DIB15 => scuba_vlo, DIB16 => scuba_vlo, + DIB17 => scuba_vlo, ADB0 => scuba_vhi, ADB1 => scuba_vlo, + ADB2 => scuba_vlo, ADB3 => scuba_vlo, ADB4 => scuba_vlo, + ADB5 => scuba_vlo, ADB6 => scuba_vlo, ADB7 => scuba_vlo, + ADB8 => scuba_vlo, ADB9 => scuba_vlo, ADB10 => scuba_vlo, + ADB11 => scuba_vlo, ADB12 => scuba_vlo, ADB13 => scuba_vlo, + CEB => scuba_vhi, CLKB => scuba_vlo, OCEB => scuba_vhi, + WEB => scuba_vlo, CSB0 => scuba_vlo, CSB1 => scuba_vlo, + CSB2 => scuba_vlo, RSTB => scuba_vlo, DOA0 => Q(0), DOA1 => Q(1), + DOA2 => Q(2), DOA3 => Q(3), DOA4 => Q(4), DOA5 => Q(5), DOA6 => Q(6), + DOA7 => Q(7), DOA8 => open, DOA9 => open, DOA10 => open, DOA11 => open, + DOA12 => open, DOA13 => open, DOA14 => open, DOA15 => open, + DOA16 => open, DOA17 => open, DOB0 => open, DOB1 => open, DOB2 => open, + DOB3 => open, DOB4 => open, DOB5 => open, DOB6 => open, DOB7 => open, + DOB8 => open, DOB9 => open, DOB10 => open, DOB11 => open, + DOB12 => open, DOB13 => open, DOB14 => open, DOB15 => open, + DOB16 => open, DOB17 => open); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of ROM4_Encoder is + for Structure + for all : VHI use entity ecp3.VHI(V); end for; + for all : VLO use entity ecp3.VLO(V); end for; + for all : DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/tdc_releases/tdc_v1.6/ROM_encoder_3.vhd b/tdc_releases/tdc_v1.6/ROM_encoder_3.vhd new file mode 100644 index 0000000..765bf32 --- /dev/null +++ b/tdc_releases/tdc_v1.6/ROM_encoder_3.vhd @@ -0,0 +1,262 @@ +-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) +-- Module Version: 5.0 +--/opt/lattice/diamond/1.4/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 10 -data_width 8 -num_rows 1024 -outdata REGISTERED -memfile /home/ugur/projects/encoder/encoder_304_with_more_bbl_errors/source/rom_encoder.mem -memformat orca -cascade -1 -e + +-- Mon Apr 16 15:10:22 2012 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity ROM_Encoder is + port ( + Address : in std_logic_vector(9 downto 0); + OutClock : in std_logic; + OutClockEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(7 downto 0)); +end ROM_Encoder; + +architecture Structure of ROM_Encoder is + + -- internal signal declarations + signal scuba_vhi : std_logic; + signal scuba_vlo : std_logic; + + -- local component declarations + component VHI + port (Z : out std_logic); + end component; + component VLO + port (Z : out std_logic); + end component; + component DP16KC + generic (INITVAL_3F : in string; INITVAL_3E : in string; + INITVAL_3D : in string; INITVAL_3C : in string; + INITVAL_3B : in string; INITVAL_3A : in string; + INITVAL_39 : in string; INITVAL_38 : in string; + INITVAL_37 : in string; INITVAL_36 : in string; + INITVAL_35 : in string; INITVAL_34 : in string; + INITVAL_33 : in string; INITVAL_32 : in string; + INITVAL_31 : in string; INITVAL_30 : in string; + INITVAL_2F : in string; INITVAL_2E : in string; + INITVAL_2D : in string; INITVAL_2C : in string; + INITVAL_2B : in string; INITVAL_2A : in string; + INITVAL_29 : in string; INITVAL_28 : in string; + INITVAL_27 : in string; INITVAL_26 : in string; + INITVAL_25 : in string; INITVAL_24 : in string; + INITVAL_23 : in string; INITVAL_22 : in string; + INITVAL_21 : in string; INITVAL_20 : in string; + INITVAL_1F : in string; INITVAL_1E : in string; + INITVAL_1D : in string; INITVAL_1C : in string; + INITVAL_1B : in string; INITVAL_1A : in string; + INITVAL_19 : in string; INITVAL_18 : in string; + INITVAL_17 : in string; INITVAL_16 : in string; + INITVAL_15 : in string; INITVAL_14 : in string; + INITVAL_13 : in string; INITVAL_12 : in string; + INITVAL_11 : in string; INITVAL_10 : in string; + INITVAL_0F : in string; INITVAL_0E : in string; + INITVAL_0D : in string; INITVAL_0C : in string; + INITVAL_0B : in string; INITVAL_0A : in string; + INITVAL_09 : in string; INITVAL_08 : in string; + INITVAL_07 : in string; INITVAL_06 : in string; + INITVAL_05 : in string; INITVAL_04 : in string; + INITVAL_03 : in string; INITVAL_02 : in string; + INITVAL_01 : in string; INITVAL_00 : in string; + GSR : in string; WRITEMODE_B : in string; + WRITEMODE_A : in string; CSDECODE_B : in string; + CSDECODE_A : in string; REGMODE_B : in string; + REGMODE_A : in string; DATA_WIDTH_B : in integer; + DATA_WIDTH_A : in integer); + port (DIA0 : in std_logic; DIA1 : in std_logic; + DIA2 : in std_logic; DIA3 : in std_logic; + DIA4 : in std_logic; DIA5 : in std_logic; + DIA6 : in std_logic; DIA7 : in std_logic; + DIA8 : in std_logic; DIA9 : in std_logic; + DIA10 : in std_logic; DIA11 : in std_logic; + DIA12 : in std_logic; DIA13 : in std_logic; + DIA14 : in std_logic; DIA15 : in std_logic; + DIA16 : in std_logic; DIA17 : in std_logic; + ADA0 : in std_logic; ADA1 : in std_logic; + ADA2 : in std_logic; ADA3 : in std_logic; + ADA4 : in std_logic; ADA5 : in std_logic; + ADA6 : in std_logic; ADA7 : in std_logic; + ADA8 : in std_logic; ADA9 : in std_logic; + ADA10 : in std_logic; ADA11 : in std_logic; + ADA12 : in std_logic; ADA13 : in std_logic; + CEA : in std_logic; CLKA : in std_logic; OCEA : in std_logic; + WEA : in std_logic; CSA0 : in std_logic; CSA1 : in std_logic; + CSA2 : in std_logic; RSTA : in std_logic; + DIB0 : in std_logic; DIB1 : in std_logic; + DIB2 : in std_logic; DIB3 : in std_logic; + DIB4 : in std_logic; DIB5 : in std_logic; + DIB6 : in std_logic; DIB7 : in std_logic; + DIB8 : in std_logic; DIB9 : in std_logic; + DIB10 : in std_logic; DIB11 : in std_logic; + DIB12 : in std_logic; DIB13 : in std_logic; + DIB14 : in std_logic; DIB15 : in std_logic; + DIB16 : in std_logic; DIB17 : in std_logic; + ADB0 : in std_logic; ADB1 : in std_logic; + ADB2 : in std_logic; ADB3 : in std_logic; + ADB4 : in std_logic; ADB5 : in std_logic; + ADB6 : in std_logic; ADB7 : in std_logic; + ADB8 : in std_logic; ADB9 : in std_logic; + ADB10 : in std_logic; ADB11 : in std_logic; + ADB12 : in std_logic; ADB13 : in std_logic; + CEB : in std_logic; CLKB : in std_logic; OCEB : in std_logic; + WEB : in std_logic; CSB0 : in std_logic; CSB1 : in std_logic; + CSB2 : in std_logic; RSTB : in std_logic; + DOA0 : out std_logic; DOA1 : out std_logic; + DOA2 : out std_logic; DOA3 : out std_logic; + DOA4 : out std_logic; DOA5 : out std_logic; + DOA6 : out std_logic; DOA7 : out std_logic; + DOA8 : out std_logic; DOA9 : out std_logic; + DOA10 : out std_logic; DOA11 : out std_logic; + DOA12 : out std_logic; DOA13 : out std_logic; + DOA14 : out std_logic; DOA15 : out std_logic; + DOA16 : out std_logic; DOA17 : out std_logic; + DOB0 : out std_logic; DOB1 : out std_logic; + DOB2 : out std_logic; DOB3 : out std_logic; + DOB4 : out std_logic; DOB5 : out std_logic; + DOB6 : out std_logic; DOB7 : out std_logic; + DOB8 : out std_logic; DOB9 : out std_logic; + DOB10 : out std_logic; DOB11 : out std_logic; + DOB12 : out std_logic; DOB13 : out std_logic; + DOB14 : out std_logic; DOB15 : out std_logic; + DOB16 : out std_logic; DOB17 : out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute MEM_LPC_FILE of ROM_Encoder_0_0_0 : label is "ROM_Encoder.lpc"; + attribute MEM_INIT_FILE of ROM_Encoder_0_0_0 : label is "rom_encoder.mem"; + attribute RESETMODE of ROM_Encoder_0_0_0 : label is "SYNC"; + +begin + -- component instantiation statements + scuba_vhi_inst : VHI + port map (Z => scuba_vhi); + + scuba_vlo_inst : VLO + port map (Z => scuba_vlo); + + ROM_Encoder_0_0_0 : DP16KC + generic map (INITVAL_3F => "0x00000000800008000081000000000000000000820000000081000820008200000000000008200083", + INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000084", + INITVAL_3D => "0x00000000000000000000000000000000000000000000000083000830008300000000000008400084", + INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000840008400000000000008500085", + INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085", + INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000008500000000000008600086", + INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085", + INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000008600000000000008600086", + INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000086", + INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000008700000000000008700087", + INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17 => "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12 => "0x00084000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10 => "0x00083000000000000000000000000000000000000008200000000000000000081000800000000000", + INITVAL_0F => "0x00087000000000000000000870000000000000000000000000000000000000000000000000000000", + INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B => "0x00086000000000000000000860000000000000000000000000000000000000000000000000000000", + INITVAL_0A => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07 => "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04 => "0x00084000000000000000000840000000000000000000000000000000000000083000830000000000", + INITVAL_03 => "0x00085000000000000000000840000000000000000000000000000000000000000000000000000000", + INITVAL_02 => "0x00084000000000000000000840008400000000000000000000000000000000000000000000000000", + INITVAL_01 => "0x00084000000000000000000830000000000000000000000000000000000000082000820000000000", + INITVAL_00 => "0x00083000000000000000000820008200081000000008200082000810000000081000800008000000", + CSDECODE_B => "0b111", CSDECODE_A => "0b000", WRITEMODE_B => "NORMAL", + WRITEMODE_A => "NORMAL", GSR => "DISABLED", REGMODE_B => "NOREG", + REGMODE_A => "OUTREG", DATA_WIDTH_B => 18, DATA_WIDTH_A => 18) + port map (DIA0 => scuba_vlo, DIA1 => scuba_vlo, DIA2 => scuba_vlo, + DIA3 => scuba_vlo, DIA4 => scuba_vlo, DIA5 => scuba_vlo, + DIA6 => scuba_vlo, DIA7 => scuba_vlo, DIA8 => scuba_vlo, + DIA9 => scuba_vlo, DIA10 => scuba_vlo, DIA11 => scuba_vlo, + DIA12 => scuba_vlo, DIA13 => scuba_vlo, DIA14 => scuba_vlo, + DIA15 => scuba_vlo, DIA16 => scuba_vlo, DIA17 => scuba_vlo, + ADA0 => scuba_vlo, ADA1 => scuba_vlo, ADA2 => scuba_vlo, + ADA3 => scuba_vlo, ADA4 => Address(0), ADA5 => Address(1), + ADA6 => Address(2), ADA7 => Address(3), ADA8 => Address(4), + ADA9 => Address(5), ADA10 => Address(6), ADA11 => Address(7), + ADA12 => Address(8), ADA13 => Address(9), CEA => OutClockEn, + CLKA => OutClock, OCEA => OutClockEn, WEA => scuba_vlo, + CSA0 => scuba_vlo, CSA1 => scuba_vlo, CSA2 => scuba_vlo, + RSTA => Reset, DIB0 => scuba_vlo, DIB1 => scuba_vlo, + DIB2 => scuba_vlo, DIB3 => scuba_vlo, DIB4 => scuba_vlo, + DIB5 => scuba_vlo, DIB6 => scuba_vlo, DIB7 => scuba_vlo, + DIB8 => scuba_vlo, DIB9 => scuba_vlo, DIB10 => scuba_vlo, + DIB11 => scuba_vlo, DIB12 => scuba_vlo, DIB13 => scuba_vlo, + DIB14 => scuba_vlo, DIB15 => scuba_vlo, DIB16 => scuba_vlo, + DIB17 => scuba_vlo, ADB0 => scuba_vlo, ADB1 => scuba_vlo, + ADB2 => scuba_vlo, ADB3 => scuba_vlo, ADB4 => scuba_vlo, + ADB5 => scuba_vlo, ADB6 => scuba_vlo, ADB7 => scuba_vlo, + ADB8 => scuba_vlo, ADB9 => scuba_vlo, ADB10 => scuba_vlo, + ADB11 => scuba_vlo, ADB12 => scuba_vlo, ADB13 => scuba_vlo, + CEB => scuba_vhi, CLKB => scuba_vlo, OCEB => scuba_vhi, + WEB => scuba_vlo, CSB0 => scuba_vlo, CSB1 => scuba_vlo, + CSB2 => scuba_vlo, RSTB => scuba_vlo, DOA0 => Q(0), DOA1 => Q(1), + DOA2 => Q(2), DOA3 => Q(3), DOA4 => Q(4), DOA5 => Q(5), DOA6 => Q(6), + DOA7 => Q(7), DOA8 => open, DOA9 => open, DOA10 => open, DOA11 => open, + DOA12 => open, DOA13 => open, DOA14 => open, DOA15 => open, + DOA16 => open, DOA17 => open, DOB0 => open, DOB1 => open, DOB2 => open, + DOB3 => open, DOB4 => open, DOB5 => open, DOB6 => open, DOB7 => open, + DOB8 => open, DOB9 => open, DOB10 => open, DOB11 => open, + DOB12 => open, DOB13 => open, DOB14 => open, DOB15 => open, + DOB16 => open, DOB17 => open); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of ROM_Encoder is + for Structure + for all : VHI use entity ecp3.VHI(V); end for; + for all : VLO use entity ecp3.VLO(V); end for; + for all : DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/tdc_releases/tdc_v1.6/Readout.vhd b/tdc_releases/tdc_v1.6/Readout.vhd new file mode 100644 index 0000000..8870b0d --- /dev/null +++ b/tdc_releases/tdc_v1.6/Readout.vhd @@ -0,0 +1,1025 @@ +------------------------------------------------------------------------------- +-- Title : Readout Entity +-- Project : +------------------------------------------------------------------------------- +-- File : Readout.vhd +-- Author : cugur@gsi.de +-- Created : 2012-10-25 +-- Last update: 2014-01-20 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +------------------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; + +entity Readout is + generic ( + CHANNEL_NUMBER : integer range 2 to 65; + TDC_VERSION : std_logic_vector(11 downto 0)); + port ( + RESET_100 : in std_logic; + RESET_200 : in std_logic; + RESET_COUNTERS : in std_logic; + CLK_100 : in std_logic; + CLK_200 : in std_logic; +-- from the channels + CH_DATA_IN : in std_logic_vector_array_36(0 to CHANNEL_NUMBER); + CH_DATA_VALID_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_ALMOST_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_ALMOST_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); +-- from the endpoint + TRG_DATA_VALID_IN : in std_logic; + VALID_TIMING_TRG_IN : in std_logic; + VALID_NOTIMING_TRG_IN : in std_logic; + INVALID_TRG_IN : in std_logic; + TMGTRG_TIMEOUT_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + SPURIOUS_TRG_IN : in std_logic; + TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + TRG_CODE_IN : in std_logic_vector(7 downto 0); + TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + TRG_TYPE_IN : in std_logic_vector(3 downto 0); + DATA_LIMIT_IN : in unsigned(7 downto 0); +-- to the endpoint + TRG_RELEASE_OUT : out std_logic; + TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATA_WRITE_OUT : out std_logic; + DATA_FINISHED_OUT : out std_logic; +-- to the channels + READ_EN_OUT : out std_logic_vector(CHANNEL_NUMBER-1 downto 0); +-- trigger window settings + TRG_WIN_PRE : in std_logic_vector(10 downto 0); + TRG_WIN_POST : in std_logic_vector(10 downto 0); + TRIGGER_WIN_EN_IN : in std_logic; +-- from the trigger handler + TRIGGER_RDO_IN : in std_logic; + TRIGGER_TDC_IN : in std_logic; + TRIG_WIN_END_TDC_IN : in std_logic; + TRIG_WIN_END_RDO_IN : in std_logic; +-- miscellaneous + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + DEBUG_MODE_EN_IN : in std_logic; + STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to 20); + READOUT_DEBUG : out std_logic_vector(31 downto 0); + REFERENCE_TIME : in std_logic; +-- ports not used after tdc_v1.5.2 + TRIGGER_WIN_END_OUT : out std_logic; + CH_WCNT_IN : in unsigned_array_8(0 to CHANNEL_NUMBER-1); + TRIGGER_TIME_IN : in std_logic_vector(38 downto 0)); +end entity Readout; + +architecture behavioral of Readout is + +------------------------------------------------------------------------------- +-- Signal Declarations +------------------------------------------------------------------------------- + + -- slow control + signal slow_control_ch_empty_i : std_logic_vector(63 downto 0); + + -- trigger window + signal trig_win_pre : unsigned(10 downto 0); + signal trig_win_post : unsigned(10 downto 0); + signal trig_win_en : std_logic; + signal trig_time_i : std_logic_vector(38 downto 0); + signal coarse_cntr_reg : std_logic_vector(10 downto 0); + signal coarse_cntr_2reg : std_logic_vector(10 downto 0); + signal coarse_cntr_3reg : std_logic_vector(10 downto 0); + signal coarse_cntr_4reg : std_logic_vector(10 downto 0); + signal coarse_cntr_5reg : std_logic_vector(10 downto 0); + signal coarse_cntr_6reg : std_logic_vector(10 downto 0); + signal coarse_cntr_7reg : std_logic_vector(10 downto 0); + signal coarse_cntr_8reg : std_logic_vector(10 downto 0); + signal coarse_cntr_9reg : std_logic_vector(10 downto 0); + signal coarse_cntr_10reg : std_logic_vector(10 downto 0); + signal coarse_cntr_11reg : std_logic_vector(10 downto 0); + signal coarse_cntr_12reg : std_logic_vector(10 downto 0); + signal epoch_cntr_reg : std_logic_vector(27 downto 0); + signal epoch_cntr_2reg : std_logic_vector(27 downto 0); + signal epoch_cntr_3reg : std_logic_vector(27 downto 0); + signal epoch_cntr_4reg : std_logic_vector(27 downto 0); + signal epoch_cntr_5reg : std_logic_vector(27 downto 0); + signal epoch_cntr_6reg : std_logic_vector(27 downto 0); + signal epoch_cntr_7reg : std_logic_vector(27 downto 0); + signal epoch_cntr_8reg : std_logic_vector(27 downto 0); + signal epoch_cntr_9reg : std_logic_vector(27 downto 0); + signal epoch_cntr_10reg : std_logic_vector(27 downto 0); + signal epoch_cntr_11reg : std_logic_vector(27 downto 0); + signal epoch_cntr_12reg : std_logic_vector(27 downto 0); + signal TW_pre : std_logic_vector(38 downto 0); + signal TW_post : std_logic_vector(38 downto 0); + signal trig_win_l : std_logic; + signal trig_win_r : std_logic; + + + + + signal start_trig_win_cnt : std_logic := '0'; + signal start_trig_win_cnt_200_p : std_logic; + signal trig_win_post_200 : std_logic_vector(10 downto 0); + signal trig_win_cnt : std_logic_vector(11 downto 0); + signal trig_win_end_200 : std_logic := '0'; + signal trig_win_end_200_p : std_logic; + signal trig_win_end_100_p : std_logic; + signal trig_win_end_100_reg : std_logic; + signal trig_win_end_100_2reg : std_logic; + signal trig_win_end_100_3reg : std_logic; + signal trig_win_end_100_4reg : std_logic; + + -- channel signals + signal ch_data_reg : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + signal ch_data_2reg : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + signal ch_data_3reg : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + signal ch_data_4reg : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + --signal ch_data_3reg : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + signal ch_empty_reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal ch_empty_2reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal ch_empty_3reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal ch_empty_4reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal ch_hit_time : std_logic_vector(38 downto 0); + signal ch_epoch_cntr_i : std_logic_vector(27 downto 0); + -- readout fsm + type FSM_READ is (IDLE, WAIT_FOR_TRIG_WIND_END, RD_CH, WAIT_FOR_LVL1_TRIG_A, WAIT_FOR_LVL1_TRIG_B, + WAIT_FOR_LVL1_TRIG_C, SEND_STATUS, SEND_TRIG_RELEASE_A, SEND_TRIG_RELEASE_B, + WAIT_FOR_BUFFER_TRANSFER); + signal RD_CURRENT : FSM_READ := IDLE; + signal RD_NEXT : FSM_READ; + type FSM_WRITE is (IDLE, WR_CH, WAIT_A, WAIT_B, WAIT_C, WAIT_D); + signal WR_CURRENT : FSM_WRITE := IDLE; + signal WR_NEXT : FSM_WRITE; + + signal start_trig_win_cnt_fsm : std_logic; + signal rd_fsm_debug_fsm : std_logic_vector(3 downto 0); + signal wr_fsm_debug_fsm : std_logic_vector(3 downto 0); + signal rd_en_fsm : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal data_finished_fsm : std_logic; + signal wr_finished_fsm : std_logic; + signal trig_release_fsm : std_logic; + signal wr_header_fsm : std_logic; + signal wr_ch_data_fsm : std_logic; + signal wr_status_fsm : std_logic; + signal wrong_readout_fsm : std_logic; + signal wr_number_fsm : unsigned(7 downto 0); + signal wr_number : unsigned(7 downto 0); + signal fifo_nr_rd_fsm : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_fsm : integer range 0 to CHANNEL_NUMBER := 0; + signal buf_delay_fsm : integer range 0 to 15 := 0; + signal buf_delay_i : integer range 0 to 15 := 0; + signal start_ch_fsm : integer range 0 to CHANNEL_NUMBER := 0; +-- signal wr_trailer_fsm : std_logic; + signal idle_fsm : std_logic; + signal readout_fsm : std_logic; + signal wait_fsm : std_logic; + -- fifo number + type Std_Logic_8_array is array (0 to 8) of std_logic_vector(3 downto 0); + signal empty_channels : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal fifo_nr_rd : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_reg : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_2reg : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_3reg : integer range 0 to CHANNEL_NUMBER := 0; + -- fifo read + signal rd_en : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + -- data mux + signal start_write : std_logic := '0'; + signal wr_header : std_logic; + signal wr_ch_data_i : std_logic; + signal wr_ch_data_reg : std_logic; + signal wr_ch_data_2reg : std_logic; + signal wr_ch_data_3reg : std_logic; + signal wr_ch_data_4reg : std_logic; + signal wr_status : std_logic; +-- signal wr_trailer : std_logic; + signal stop_status_i : std_logic; + signal start_ch_i : integer range 0 to CHANNEL_NUMBER := 0; + signal start_ch_reg : integer range 0 to CHANNEL_NUMBER := 0; + signal start_ch_2reg : integer range 0 to CHANNEL_NUMBER := 0; + signal start_ch_3reg : integer range 0 to CHANNEL_NUMBER := 0; + signal start_ch_4reg : integer range 0 to CHANNEL_NUMBER := 0; + -- to endpoint + signal data_out_reg : std_logic_vector(31 downto 0); + signal data_wr_reg : std_logic; + signal data_finished : std_logic; + signal wr_finished : std_logic; + signal wr_finished_reg : std_logic; + signal wr_finished_2reg : std_logic; + signal trig_release_reg : std_logic; + -- statistics + signal trig_number : unsigned(23 downto 0) := (others => '0'); + signal release_number : unsigned(23 downto 0) := (others => '0'); + signal valid_tmg_trig_number : unsigned(23 downto 0) := (others => '0'); + signal valid_NOtmg_trig_number : unsigned(23 downto 0) := (others => '0'); + signal invalid_trig_number : unsigned(23 downto 0) := (others => '0'); + signal multi_tmg_trig_number : unsigned(23 downto 0) := (others => '0'); + signal spurious_trig_number : unsigned(23 downto 0) := (others => '0'); + signal wrong_readout_number : unsigned(23 downto 0) := (others => '0'); + signal spike_number : unsigned(23 downto 0) := (others => '0'); + signal timeout_number : unsigned(23 downto 0) := (others => '0'); + signal total_empty_channel : unsigned(23 downto 0) := (others => '0'); + signal idle_time : unsigned(23 downto 0) := (others => '0'); + signal readout_time : unsigned(23 downto 0) := (others => '0'); + signal wait_time : unsigned(23 downto 0) := (others => '0'); + signal finished_number : unsigned(23 downto 0) := (others => '0'); + signal valid_timing_trig_p : std_logic; + signal valid_notiming_trig_p : std_logic; + signal invalid_trig_p : std_logic; + signal multi_tmg_trig_p : std_logic; + signal spurious_trig_p : std_logic; + signal spike_detected_p : std_logic; + signal timeout_detected_p : std_logic; + signal idle_time_up : std_logic; + signal readout_time_up : std_logic; + signal wait_time_up : std_logic; + signal wrong_readout_up : std_logic; + signal finished_i : std_logic; + -- debug + signal header_error_bits : std_logic_vector(15 downto 0); + signal trailer_error_bits : std_logic_vector(15 downto 0); + signal ch_full_i : std_logic; + signal ch_almost_full_i : std_logic; + signal rd_fsm_debug : std_logic_vector(3 downto 0); + signal wr_fsm_debug : std_logic_vector(3 downto 0); + +begin -- behavioral + + trig_win_pre <= unsigned(TRG_WIN_PRE); + trig_win_post <= unsigned(TRG_WIN_POST); + trig_win_en <= TRIGGER_WIN_EN_IN when rising_edge(CLK_100); + +------------------------------------------------------------------------------- +-- Trigger window +------------------------------------------------------------------------------- +-- Trigger window borders + TrigWinCalculation : process (CLK_100) + begin + if rising_edge(CLK_100) then + TW_pre <= std_logic_vector(unsigned(trig_time_i)-unsigned(trig_win_pre)); + TW_post <= std_logic_vector(unsigned(trig_time_i)+unsigned(trig_win_post)); + end if; + end process TrigWinCalculation; + +-- Trigger Time Determination + DefineTriggerTime : process (CLK_200) + begin + if rising_edge(CLK_200) then + if TRIGGER_TDC_IN = '1' then + trig_time_i <= epoch_cntr_12reg & coarse_cntr_12reg; + end if; + end if; + end process DefineTriggerTime; + coarse_cntr_reg <= COARSE_COUNTER_IN when rising_edge(CLK_200); + coarse_cntr_2reg <= coarse_cntr_reg when rising_edge(CLK_200); + coarse_cntr_3reg <= coarse_cntr_2reg when rising_edge(CLK_200); + coarse_cntr_4reg <= coarse_cntr_3reg when rising_edge(CLK_200); + coarse_cntr_5reg <= coarse_cntr_4reg when rising_edge(CLK_200); + coarse_cntr_6reg <= coarse_cntr_5reg when rising_edge(CLK_200); + coarse_cntr_7reg <= coarse_cntr_6reg when rising_edge(CLK_200); + coarse_cntr_8reg <= coarse_cntr_7reg when rising_edge(CLK_200); + coarse_cntr_9reg <= coarse_cntr_8reg when rising_edge(CLK_200); + coarse_cntr_10reg <= coarse_cntr_9reg when rising_edge(CLK_200); + coarse_cntr_11reg <= coarse_cntr_10reg when rising_edge(CLK_200); + coarse_cntr_12reg <= coarse_cntr_11reg when rising_edge(CLK_200); + + epoch_cntr_reg <= EPOCH_COUNTER_IN when rising_edge(CLK_200); + epoch_cntr_2reg <= epoch_cntr_reg when rising_edge(CLK_200); + epoch_cntr_3reg <= epoch_cntr_2reg when rising_edge(CLK_200); + epoch_cntr_4reg <= epoch_cntr_3reg when rising_edge(CLK_200); + epoch_cntr_5reg <= epoch_cntr_4reg when rising_edge(CLK_200); + epoch_cntr_6reg <= epoch_cntr_5reg when rising_edge(CLK_200); + epoch_cntr_7reg <= epoch_cntr_6reg when rising_edge(CLK_200); + epoch_cntr_8reg <= epoch_cntr_7reg when rising_edge(CLK_200); + epoch_cntr_9reg <= epoch_cntr_8reg when rising_edge(CLK_200); + epoch_cntr_10reg <= epoch_cntr_9reg when rising_edge(CLK_200); + epoch_cntr_11reg <= epoch_cntr_10reg when rising_edge(CLK_200); + epoch_cntr_12reg <= epoch_cntr_11reg when rising_edge(CLK_200); + + +-- Channel Hit Time Determination + ChannelHitTime : process (CLK_100) + begin + if rising_edge(CLK_100) then + if ch_data_2reg(fifo_nr_wr)(35 downto 32) = x"1" and ch_data_2reg(fifo_nr_wr)(31 downto 29) = "011" then + ch_epoch_cntr_i <= ch_data_2reg(fifo_nr_wr)(27 downto 0); + end if; + + if ch_data_2reg(fifo_nr_wr)(35 downto 32) = x"1" and ch_data_2reg(fifo_nr_wr)(31) = '1' then + ch_hit_time <= ch_epoch_cntr_i & ch_data_2reg(fifo_nr_wr)(10 downto 0); + elsif ch_data_2reg(fifo_nr_wr)(35 downto 32) = x"1" and ch_data_2reg(fifo_nr_wr)(31 downto 29) = "011" then + ch_hit_time <= (others => '0'); + end if; + end if; + end process ChannelHitTime; + +-- Controls if the data coming from the channel is greater than the trigger window pre-edge + Check_Trig_Win_Left : process (CLK_100) + begin + if rising_edge(CLK_100) then + if unsigned(TW_pre) <= unsigned(ch_hit_time) then + trig_win_l <= '1'; + else + trig_win_l <= '0'; + end if; + end if; + end process Check_Trig_Win_Left; + +-- Controls if the data coming from the channel is smaller than the trigger window post-edge + Check_Trig_Win_Right : process (CLK_100) + begin + if rising_edge(CLK_100) then + if unsigned(ch_hit_time) <= unsigned(TW_post) then + trig_win_r <= '1'; + else + trig_win_r <= '0'; + end if; + end if; + end process Check_Trig_Win_Right; + +------------------------------------------------------------------------------- +-- Readout +------------------------------------------------------------------------------- +-- Readout fsm + RD_FSM_CLK : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_100 = '1' then + RD_CURRENT <= IDLE; + start_ch_i <= 0; + fifo_nr_rd <= 0; + else + RD_CURRENT <= RD_NEXT; + rd_en <= rd_en_fsm; + wr_header <= wr_header_fsm; + wr_status <= wr_status_fsm; + data_finished <= data_finished_fsm; + trig_release_reg <= trig_release_fsm; + start_ch_i <= start_ch_fsm; + buf_delay_i <= buf_delay_fsm; + wrong_readout_up <= wrong_readout_fsm; + idle_time_up <= idle_fsm; + readout_time_up <= readout_fsm; + wait_time_up <= wait_fsm; + fifo_nr_rd <= fifo_nr_rd_fsm; + rd_fsm_debug <= rd_fsm_debug_fsm; + end if; + end if; + end process RD_FSM_CLK; + READ_EN_OUT <= rd_en; + + RD_FSM_PROC : process (RD_CURRENT, VALID_TIMING_TRG_IN, VALID_NOTIMING_TRG_IN, TRG_DATA_VALID_IN, + INVALID_TRG_IN, TMGTRG_TIMEOUT_IN, TRG_TYPE_IN, + SPURIOUS_TRG_IN, stop_status_i, DEBUG_MODE_EN_IN, fifo_nr_rd, + TRIG_WIN_END_RDO_IN, buf_delay_i, CH_EMPTY_IN, start_ch_i) + begin + + rd_en_fsm <= (others => '0'); + wr_header_fsm <= '0'; + data_finished_fsm <= '0'; + trig_release_fsm <= '0'; + start_ch_fsm <= start_ch_i; + wrong_readout_fsm <= '0'; + idle_fsm <= '0'; + readout_fsm <= '0'; + wait_fsm <= '0'; + wr_status_fsm <= '0'; + fifo_nr_rd_fsm <= fifo_nr_rd; + rd_fsm_debug_fsm <= x"0"; + RD_NEXT <= RD_CURRENT; + + case (RD_CURRENT) is + when IDLE => + if VALID_TIMING_TRG_IN = '1' then + RD_NEXT <= WAIT_FOR_TRIG_WIND_END; --WR_HEADER_A; + wr_header_fsm <= '1'; + readout_fsm <= '1'; + elsif VALID_NOTIMING_TRG_IN = '1' then + if TRG_TYPE_IN = x"E" then + wr_header_fsm <= '1'; + RD_NEXT <= SEND_STATUS; + elsif TRG_TYPE_IN = x"D" then + RD_NEXT <= WAIT_FOR_TRIG_WIND_END; --WR_HEADER_A; + wr_header_fsm <= '1'; + readout_fsm <= '1'; + else + data_finished_fsm <= '1'; + RD_NEXT <= SEND_TRIG_RELEASE_A; + end if; + elsif INVALID_TRG_IN = '1' then + RD_NEXT <= SEND_TRIG_RELEASE_A; + data_finished_fsm <= '1'; + end if; + start_ch_fsm <= 0; + idle_fsm <= '1'; + rd_fsm_debug_fsm <= x"1"; + + --when WR_HEADER_A => + -- RD_NEXT <= WAIT_FOR_TRIG_WIND_END; + -- wr_header_fsm <= '1'; + -- readout_fsm <= '1'; + -- rd_fsm_debug_fsm <= x"3"; + + when WAIT_FOR_TRIG_WIND_END => + if TRIG_WIN_END_RDO_IN = '1' then + RD_NEXT <= WAIT_FOR_BUFFER_TRANSFER; --RD_CH; + end if; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"2"; + + when WAIT_FOR_BUFFER_TRANSFER => -- the data from channel fifo is written to the buffer + if buf_delay_i = 15 then + RD_NEXT <= RD_CH; + buf_delay_fsm <= 0; + else + buf_delay_fsm <= buf_delay_i + 1; + end if; + rd_fsm_debug_fsm <= x"3"; + + when RD_CH => + if CH_EMPTY_IN(fifo_nr_rd) = '0' then + rd_en_fsm(fifo_nr_rd) <= '1'; + fifo_nr_rd_fsm <= fifo_nr_rd; + rd_fsm_debug_fsm <= x"B"; + elsif fifo_nr_rd = CHANNEL_NUMBER-1 then + rd_en_fsm(fifo_nr_rd) <= '0'; + if DEBUG_MODE_EN_IN = '1' then + RD_NEXT <= SEND_STATUS; + else + RD_NEXT <= WAIT_FOR_LVL1_TRIG_A; + end if; + rd_fsm_debug_fsm <= x"C"; + else + fifo_nr_rd_fsm <= fifo_nr_rd + 1; + start_ch_fsm <= start_ch_i + 1; + rd_fsm_debug_fsm <= x"D"; + end if; + readout_fsm <= '1'; +-- rd_fsm_debug_fsm <= x"4"; + + when WAIT_FOR_LVL1_TRIG_A => + if TRG_DATA_VALID_IN = '1' then + RD_NEXT <= WAIT_FOR_LVL1_TRIG_B; + elsif TMGTRG_TIMEOUT_IN = '1' then + RD_NEXT <= IDLE; + end if; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"5"; + + when WAIT_FOR_LVL1_TRIG_B => + RD_NEXT <= WAIT_FOR_LVL1_TRIG_C; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"6"; + + when WAIT_FOR_LVL1_TRIG_C => + if SPURIOUS_TRG_IN = '1' then + wrong_readout_fsm <= '1'; + end if; + RD_NEXT <= SEND_TRIG_RELEASE_A; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"7"; + + when SEND_STATUS => + if stop_status_i = '1' then + if DEBUG_MODE_EN_IN = '1' then + RD_NEXT <= WAIT_FOR_LVL1_TRIG_A; + else + RD_NEXT <= SEND_TRIG_RELEASE_A; + end if; + data_finished_fsm <= '1'; + else + wr_status_fsm <= '1'; + end if; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"8"; + + when SEND_TRIG_RELEASE_A => + RD_NEXT <= SEND_TRIG_RELEASE_B; + trig_release_fsm <= '1'; + fifo_nr_rd_fsm <= 0; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"9"; + + when SEND_TRIG_RELEASE_B => + RD_NEXT <= IDLE; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"A"; + + when others => + RD_NEXT <= IDLE; + rd_fsm_debug_fsm <= x"F"; + end case; + end process RD_FSM_PROC; + + start_ch_reg <= start_ch_i when rising_edge(CLK_100); + start_ch_2reg <= start_ch_reg when rising_edge(CLK_100); + start_ch_3reg <= start_ch_2reg when rising_edge(CLK_100); + start_ch_4reg <= start_ch_3reg when rising_edge(CLK_100); + + --purpose: FSM for writing data to endpoint buffer + WR_FSM_CLK : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_100 = '1' then + WR_CURRENT <= IDLE; + else + WR_CURRENT <= WR_NEXT; + wr_ch_data_i <= wr_ch_data_fsm; + wr_number <= wr_number_fsm; + fifo_nr_wr <= fifo_nr_wr_fsm; + wr_finished <= wr_finished_fsm; + wr_fsm_debug <= wr_fsm_debug_fsm; + start_write <= or_all(CH_DATA_VALID_IN); + end if; + end if; + end process WR_FSM_CLK; + + WR_FSM : process (WR_CURRENT, wr_number, fifo_nr_wr, DATA_LIMIT_IN, start_write, CH_DATA_VALID_IN, + start_ch_4reg) + + begin + + WR_NEXT <= WR_CURRENT; + wr_ch_data_fsm <= '0'; + wr_number_fsm <= (others => '0'); + fifo_nr_wr_fsm <= 0; + wr_finished_fsm <= '0'; + + case (WR_CURRENT) is + when IDLE => + if start_write = '1' then + fifo_nr_wr_fsm <= start_ch_4reg; + WR_NEXT <= WR_CH; + end if; + wr_fsm_debug_fsm <= x"1"; +-- + when WR_CH => + if ch_data_2reg(fifo_nr_wr)(35 downto 32) /= x"f" then + if wr_number >= DATA_LIMIT_IN then + wr_ch_data_fsm <= '0'; + else + wr_ch_data_fsm <= '1'; + end if; + wr_number_fsm <= wr_number + to_unsigned(1, 1); + fifo_nr_wr_fsm <= fifo_nr_wr; + wr_fsm_debug_fsm <= x"4"; + elsif fifo_nr_wr = CHANNEL_NUMBER-1 then + wr_number_fsm <= (others => '0'); + wr_finished_fsm <= '1'; + WR_NEXT <= IDLE; + wr_fsm_debug_fsm <= x"5"; + elsif CH_DATA_VALID_IN(fifo_nr_wr) = '1' then + wr_number_fsm <= wr_number; + fifo_nr_wr_fsm <= fifo_nr_wr; + wr_fsm_debug_fsm <= x"6"; + else + wr_number_fsm <= (others => '0'); + fifo_nr_wr_fsm <= fifo_nr_wr + 1; + WR_NEXT <= WAIT_A; + wr_fsm_debug_fsm <= x"7"; + end if; +-- wr_fsm_debug_fsm <= x"2"; +-- + when WAIT_A => + WR_NEXT <= WAIT_B; + fifo_nr_wr_fsm <= fifo_nr_wr; + wr_fsm_debug_fsm <= x"3"; +-- + when WAIT_B => + WR_NEXT <= WR_CH; --WAIT_C; + fifo_nr_wr_fsm <= fifo_nr_wr; + wr_fsm_debug_fsm <= x"3"; +-- + when WAIT_C => + WR_NEXT <= WAIT_D; + fifo_nr_wr_fsm <= fifo_nr_wr; + wr_fsm_debug_fsm <= x"3"; +-- + when WAIT_D => + WR_NEXT <= WR_CH; + fifo_nr_wr_fsm <= fifo_nr_wr; + wr_fsm_debug_fsm <= x"3"; +-- + when others => + WR_NEXT <= IDLE; + wr_fsm_debug_fsm <= x"F"; + + end case; + end process WR_FSM; + + fifo_nr_wr_reg <= fifo_nr_wr when rising_edge(CLK_100); + fifo_nr_wr_2reg <= fifo_nr_wr_reg when rising_edge(CLK_100); + fifo_nr_wr_3reg <= fifo_nr_wr_2reg when rising_edge(CLK_100); + wr_ch_data_reg <= wr_ch_data_i when rising_edge(CLK_100); + wr_ch_data_2reg <= wr_ch_data_reg when rising_edge(CLK_100); + wr_finished_reg <= wr_finished when rising_edge(CLK_100); + wr_finished_2reg <= wr_finished_reg when rising_edge(CLK_100); + +------------------------------------------------------------------------------- +-- Data out mux +------------------------------------------------------------------------------- + Data_Out_MUX : process (CLK_100) + variable i : integer := 0; + begin + if rising_edge(CLK_100) then + if wr_header = '1' then + data_out_reg <= "001" & "0" & TRG_TYPE_IN & TRG_CODE_IN & header_error_bits; + data_wr_reg <= '1'; + stop_status_i <= '0'; + elsif wr_ch_data_reg = '1' then + if TRIGGER_WIN_EN_IN = '1' then -- trigger window enabled + if ch_data_4reg(fifo_nr_wr_2reg)(35 downto 32) = x"1" and ch_data_4reg(fifo_nr_wr_2reg)(31 downto 29) = "011" then -- epoch counter + data_out_reg <= ch_data_4reg(fifo_nr_wr_2reg)(31 downto 0); + data_wr_reg <= '1'; + --elsif (TW_pre(10) = '1' and ref_time_coarse(10) = '0') or (TW_post(10) = '0' and ref_time_coarse(10) = '1') then -- if one of the trigger window edges has an overflow + -- if (trig_win_l = '0' and trig_win_r = '1') or (trig_win_l = '1' and trig_win_r = '0') then + -- data_out_reg <= ch_data_4reg(fifo_nr); + -- data_wr_reg <= '1'; + -- else + -- data_out_reg <= (others => '1'); + -- data_wr_reg <= '0'; + -- end if; + elsif ch_data_4reg(fifo_nr_wr_2reg)(35 downto 32) = x"1" and ch_data_4reg(fifo_nr_wr_2reg)(31) = '1' and trig_win_l = '1' and trig_win_r = '1' then -- if both of the trigger window edges are in the coarse counter boundries + data_out_reg <= ch_data_4reg(fifo_nr_wr_2reg)(31 downto 0); + data_wr_reg <= '1'; + else + data_out_reg <= (others => '1'); + data_wr_reg <= '0'; + end if; + stop_status_i <= '0'; + else -- trigger window disabled + data_out_reg <= ch_data_4reg(fifo_nr_wr_2reg)(31 downto 0); + data_wr_reg <= '1'; + stop_status_i <= '0'; + end if; + elsif wr_status = '1' then + case i is + when 0 => data_out_reg <= "010" & "00000" & std_logic_vector(trig_number); + when 1 => data_out_reg <= "010" & "00001" & std_logic_vector(release_number); + when 2 => data_out_reg <= "010" & "00010" & std_logic_vector(valid_tmg_trig_number); + when 3 => data_out_reg <= "010" & "00011" & std_logic_vector(valid_NOtmg_trig_number); + when 4 => data_out_reg <= "010" & "00100" & std_logic_vector(invalid_trig_number); + when 5 => data_out_reg <= "010" & "00101" & std_logic_vector(multi_tmg_trig_number); + when 6 => data_out_reg <= "010" & "00110" & std_logic_vector(spurious_trig_number); + when 7 => data_out_reg <= "010" & "00111" & std_logic_vector(wrong_readout_number); + when 8 => data_out_reg <= "010" & "01000" & std_logic_vector(spike_number); + when 9 => data_out_reg <= "010" & "01001" & std_logic_vector(idle_time); + when 10 => data_out_reg <= "010" & "01010" & std_logic_vector(wait_time); + when 11 => data_out_reg <= "010" & "01011" & std_logic_vector(total_empty_channel); + when 12 => data_out_reg <= "010" & "01100" & std_logic_vector(readout_time); + stop_status_i <= '1'; + when 13 => data_out_reg <= "010" & "01101" & std_logic_vector(timeout_number); + i := -1; + when others => null; + end case; + data_wr_reg <= '1'; + i := i+1; + --elsif wr_trailer = '1' then + -- data_out_reg <= "011" & "0000000000000" & trailer_error_bits; + -- data_wr_reg <= '1'; + -- stop_status_i <= '0'; + else + data_out_reg <= (others => '1'); + data_wr_reg <= '0'; + stop_status_i <= '0'; + end if; + end if; + end process Data_Out_MUX; + + DATA_OUT <= data_out_reg; + DATA_WRITE_OUT <= data_wr_reg; + finished_i <= (data_finished or wr_finished_2reg) when rising_edge(CLK_100); + DATA_FINISHED_OUT <= finished_i; + TRG_RELEASE_OUT <= trig_release_reg; + TRG_STATUSBIT_OUT <= (others => '0'); + READOUT_DEBUG(3 downto 0) <= rd_fsm_debug; + READOUT_DEBUG(7 downto 4) <= wr_fsm_debug; + READOUT_DEBUG(8) <= data_wr_reg; + READOUT_DEBUG(9) <= finished_i; + READOUT_DEBUG(10) <= trig_release_reg; + READOUT_DEBUG(16 downto 11) <= data_out_reg(27 downto 22); + READOUT_DEBUG(31 downto 17) <= (others => '0'); + + -- Error, warning bits set in the header + header_error_bits(15 downto 3) <= (others => '0'); + header_error_bits(0) <= '0'; +--header_error_bits(0) <= lost_hit_i; -- if there is at least one lost hit (can be more if the FIFO is full). + header_error_bits(1) <= '0'; -- ch_full_i; + header_error_bits(2) <= '0'; -- ch_almost_full_i; + + -- Error, warning bits set in the trailer + trailer_error_bits <= (others => '0'); + -- trailer_error_bits (0) <= wrong_readout_i; -- if there is a wrong readout because of a spurious timing trigger + + ch_full_i <= or_all(CH_FULL_IN); + ch_almost_full_i <= or_all(CH_ALMOST_FULL_IN); + + + +------------------------------------------------------------------------------- +-- Debug and statistics words +------------------------------------------------------------------------------- + + edge_to_pulse_1 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => VALID_TIMING_TRG_IN, + pulse => valid_timing_trig_p); + + edge_to_pulse_2 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => VALID_NOTIMING_TRG_IN, + pulse => valid_notiming_trig_p); + + edge_to_pulse_3 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => INVALID_TRG_IN, + pulse => invalid_trig_p); + + edge_to_pulse_4 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => MULTI_TMG_TRG_IN, + pulse => multi_tmg_trig_p); + + edge_to_pulse_5 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => SPURIOUS_TRG_IN, + pulse => spurious_trig_p); + + edge_to_pulse_6 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => SPIKE_DETECTED_IN, + pulse => spike_detected_p); + + edge_to_pulse_7 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => TMGTRG_TIMEOUT_IN, + pulse => timeout_detected_p); + +-- Internal trigger number counter (only valid triggers) + Statistics_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + trig_number <= (others => '0'); + elsif valid_timing_trig_p = '1' or valid_notiming_trig_p = '1' then + trig_number <= trig_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Trigger_Number; + +-- Internal release number counter + Statistics_Release_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + release_number <= (others => '0'); + elsif trig_release_reg = '1' then + release_number <= release_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Release_Number; + +-- Internal valid timing trigger number counter + Statistics_Valid_Timing_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + valid_tmg_trig_number <= (others => '0'); + elsif valid_timing_trig_p = '1' then + valid_tmg_trig_number <= valid_tmg_trig_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Valid_Timing_Trigger_Number; + +-- Internal valid NOtiming trigger number counter + Statistics_Valid_NoTiming_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + valid_NOtmg_trig_number <= (others => '0'); + elsif valid_notiming_trig_p = '1' then + valid_NOtmg_trig_number <= valid_NOtmg_trig_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Valid_NoTiming_Trigger_Number; + +-- Internal invalid trigger number counter + Statistics_Invalid_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + invalid_trig_number <= (others => '0'); + elsif invalid_trig_p = '1' then + invalid_trig_number <= invalid_trig_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Invalid_Trigger_Number; + +-- Internal multi timing trigger number counter + Statistics_Multi_Timing_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + multi_tmg_trig_number <= (others => '0'); + elsif multi_tmg_trig_p = '1' then + multi_tmg_trig_number <= multi_tmg_trig_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Multi_Timing_Trigger_Number; + +-- Internal spurious trigger number counter + Statistics_Spurious_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + spurious_trig_number <= (others => '0'); + elsif spurious_trig_p = '1' then + spurious_trig_number <= spurious_trig_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Spurious_Trigger_Number; + +-- Number of wrong readout becasue of spurious trigger + Statistics_Wrong_Readout_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + wrong_readout_number <= (others => '0'); + elsif wrong_readout_up = '1' then + wrong_readout_number <= wrong_readout_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Wrong_Readout_Number; + +-- Internal spike number counter + Statistics_Spike_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + spike_number <= (others => '0'); + elsif spike_detected_p = '1' then + spike_number <= spike_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Spike_Number; + +-- Internal timeout number counter + Statistics_Timeout_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + timeout_number <= (others => '0'); + elsif timeout_detected_p = '1' then + timeout_number <= timeout_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Timeout_Number; + +-- IDLE time of the TDC readout + Statistics_Idle_Time : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + idle_time <= (others => '0'); + elsif idle_time_up = '1' then + idle_time <= idle_time + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Idle_Time; + +-- Readout and Wait time of the TDC readout + Statistics_Readout_Wait_Time : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + readout_time <= (others => '0'); + wait_time <= (others => '0'); + elsif readout_time_up = '1' then + readout_time <= readout_time + to_unsigned(1, 1); + elsif wait_time_up = '1' then + wait_time <= wait_time + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Readout_Wait_Time; + +-- Empty channel number + Statistics_Empty_Channel_Number : process (CLK_100) + variable i : integer := CHANNEL_NUMBER; + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + total_empty_channel <= (others => '0'); + i := CHANNEL_NUMBER; + elsif trig_win_end_100_p = '1' then + empty_channels(CHANNEL_NUMBER-1 downto 0) <= CH_EMPTY_IN(CHANNEL_NUMBER-1 downto 0); + i := 0; + elsif i = CHANNEL_NUMBER then + i := i; + elsif empty_channels(i) = '1' then + total_empty_channel <= total_empty_channel + to_unsigned(1, 1); + i := i + 1; + else + i := i + 1; + end if; + end if; + end process Statistics_Empty_Channel_Number; + + -- Number of sent data finished + Statistics_Finished_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + finished_number <= (others => '0'); + elsif finished_i = '1' then + finished_number <= finished_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Finished_Number; + + +------------------------------------------------------------------------------- +-- STATUS REGISTERS BUS +------------------------------------------------------------------------------- + STATUS_REGISTERS_BUS_OUT(0)(3 downto 0) <= rd_fsm_debug; + STATUS_REGISTERS_BUS_OUT(0)(7 downto 4) <= wr_fsm_debug; + STATUS_REGISTERS_BUS_OUT(0)(15 downto 8) <= std_logic_vector(to_unsigned(CHANNEL_NUMBER-1, 8)); + STATUS_REGISTERS_BUS_OUT(0)(16) <= REFERENCE_TIME when rising_edge(CLK_100); + STATUS_REGISTERS_BUS_OUT(0)(27 downto 17) <= TDC_VERSION(10 downto 0); + STATUS_REGISTERS_BUS_OUT(0)(31 downto 28) <= TRG_TYPE_IN when rising_edge(CLK_100); + + STATUS_REGISTERS_BUS_OUT(1) <= slow_control_ch_empty_i(31 downto 0); + STATUS_REGISTERS_BUS_OUT(2) <= slow_control_ch_empty_i(63 downto 32); + STATUS_REGISTERS_BUS_OUT(3)(10 downto 0) <= TRG_WIN_PRE; + STATUS_REGISTERS_BUS_OUT(3)(15 downto 11) <= (others => '0'); + STATUS_REGISTERS_BUS_OUT(3)(26 downto 16) <= TRG_WIN_POST; + STATUS_REGISTERS_BUS_OUT(3)(30 downto 27) <= (others => '0'); + STATUS_REGISTERS_BUS_OUT(3)(31) <= TRIGGER_WIN_EN_IN; + STATUS_REGISTERS_BUS_OUT(4)(23 downto 0) <= std_logic_vector(trig_number); + STATUS_REGISTERS_BUS_OUT(5)(23 downto 0) <= std_logic_vector(valid_tmg_trig_number); + STATUS_REGISTERS_BUS_OUT(6)(23 downto 0) <= std_logic_vector(valid_NOtmg_trig_number); + STATUS_REGISTERS_BUS_OUT(7)(23 downto 0) <= std_logic_vector(invalid_trig_number); + STATUS_REGISTERS_BUS_OUT(8)(23 downto 0) <= std_logic_vector(multi_tmg_trig_number); + STATUS_REGISTERS_BUS_OUT(9)(23 downto 0) <= std_logic_vector(spurious_trig_number); + STATUS_REGISTERS_BUS_OUT(10)(23 downto 0) <= std_logic_vector(wrong_readout_number); + STATUS_REGISTERS_BUS_OUT(11)(23 downto 0) <= std_logic_vector(spike_number); + STATUS_REGISTERS_BUS_OUT(12)(23 downto 0) <= std_logic_vector(idle_time); + STATUS_REGISTERS_BUS_OUT(13)(23 downto 0) <= std_logic_vector(wait_time); + STATUS_REGISTERS_BUS_OUT(14)(23 downto 0) <= std_logic_vector(total_empty_channel); + STATUS_REGISTERS_BUS_OUT(15)(23 downto 0) <= std_logic_vector(release_number); + STATUS_REGISTERS_BUS_OUT(16)(23 downto 0) <= std_logic_vector(readout_time); + STATUS_REGISTERS_BUS_OUT(17)(23 downto 0) <= std_logic_vector(timeout_number); + STATUS_REGISTERS_BUS_OUT(18)(23 downto 0) <= std_logic_vector(finished_number); + + STATUS_REGISTERS_BUS_OUT(19)(4 downto 0) <= CH_EMPTY_IN; + STATUS_REGISTERS_BUS_OUT(19)(11 downto 8) <= std_logic_vector(to_unsigned(fifo_nr_rd, 4)); + STATUS_REGISTERS_BUS_OUT(20)(0) <= wr_ch_data_reg; + STATUS_REGISTERS_BUS_OUT(20)(11 downto 8) <= std_logic_vector(to_unsigned(fifo_nr_wr, 4)); + STATUS_REGISTERS_BUS_OUT(20)(31 downto 16) <= ch_data_2reg(fifo_nr_wr)(35 downto 20); + + FILL_BUS1 : for i in 4 to 18 generate + STATUS_REGISTERS_BUS_OUT(i)(31 downto 24) <= (others => '0'); + end generate FILL_BUS1; + + slow_control_ch_empty_i(63 downto CHANNEL_NUMBER-1) <= (others => '1'); + slow_control_ch_empty_i(CHANNEL_NUMBER-2 downto 0) <= ch_empty_2reg(CHANNEL_NUMBER-1 downto 1); + +------------------------------------------------------------------------------- +-- Registering +------------------------------------------------------------------------------- + ch_data_reg <= CH_DATA_IN when rising_edge(CLK_100); + ch_data_2reg <= ch_data_reg when rising_edge(CLK_100); + ch_data_3reg <= ch_data_2reg when rising_edge(CLK_100); + ch_data_4reg <= ch_data_3reg when rising_edge(CLK_100); + ch_empty_reg <= CH_EMPTY_IN when rising_edge(CLK_100); + ch_empty_2reg <= ch_empty_reg when rising_edge(CLK_100); + ch_empty_3reg <= ch_empty_2reg when rising_edge(CLK_100); + ch_empty_4reg <= ch_empty_3reg when rising_edge(CLK_100); + + trig_win_post_200 <= std_logic_vector(unsigned(TRIG_WIN_POST)-8) when rising_edge(CLK_200); + +end behavioral; diff --git a/tdc_releases/tdc_v1.6/ShiftRegisterSISO.vhd b/tdc_releases/tdc_v1.6/ShiftRegisterSISO.vhd new file mode 100644 index 0000000..a82160b --- /dev/null +++ b/tdc_releases/tdc_v1.6/ShiftRegisterSISO.vhd @@ -0,0 +1,54 @@ +------------------------------------------------------------------------------- +-- Title : Register.vhd +-- Project : +------------------------------------------------------------------------------- +-- File : Register.vhd +-- Author : c.ugur@gsi.de +-- Created : 2012-10-02 +-- Last update: 2013-03-06 +------------------------------------------------------------------------------- +-- Description: Used to register signals n levels. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity ShiftRegisterSISO is + + generic ( + DEPTH : integer range 1 to 32 := 1; -- defines the number register level + WIDTH : integer range 1 to 32 := 1); -- defines the register size + + port ( + CLK : in std_logic; -- register clock + D_IN : in std_logic_vector(WIDTH-1 downto 0); -- register input + D_OUT : out std_logic_vector(WIDTH-1 downto 0)); -- register out + +end ShiftRegisterSISO; + +architecture Behavioral of ShiftRegisterSISO is + + type RegisterArray is array (0 to DEPTH) of std_logic_vector(WIDTH-1 downto 0); + signal reg : RegisterArray; + + attribute syn_preserve : boolean; + attribute syn_preserve of reg : signal is true; + +begin -- RTL + + reg(0) <= D_IN; + + GEN_Registers : for i in 1 to DEPTH generate + Registers : process (CLK) + begin + if rising_edge(CLK) then + reg(i) <= reg(i-1); + end if; + end process Registers; + end generate GEN_Registers; + + D_OUT <= reg(DEPTH); + +end Behavioral; diff --git a/tdc_releases/tdc_v1.6/TDC.vhd b/tdc_releases/tdc_v1.6/TDC.vhd new file mode 100644 index 0000000..637d9f0 --- /dev/null +++ b/tdc_releases/tdc_v1.6/TDC.vhd @@ -0,0 +1,609 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + +entity TDC is + generic ( + CHANNEL_NUMBER : integer range 2 to 65; + CONTROL_REG_NR : integer range 0 to 6; + TDC_VERSION : std_logic_vector(11 downto 0); + DEBUG : integer range 0 to 1 := c_YES; + SIMULATION : integer range 0 to 1 := c_NO); + port ( + RESET : in std_logic; + CLK_TDC : in std_logic; + CLK_READOUT : in std_logic; + REFERENCE_TIME : in std_logic; + HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1); + HIT_CALIBRATION : in std_logic; + TRG_WIN_PRE : in std_logic_vector(10 downto 0); + TRG_WIN_POST : in std_logic_vector(10 downto 0); +-- + -- Trigger signals from handler + TRG_DATA_VALID_IN : in std_logic := '0'; + VALID_TIMING_TRG_IN : in std_logic := '0'; + VALID_NOTIMING_TRG_IN : in std_logic := '0'; + INVALID_TRG_IN : in std_logic := '0'; + TMGTRG_TIMEOUT_IN : in std_logic := '0'; + SPIKE_DETECTED_IN : in std_logic := '0'; + MULTI_TMG_TRG_IN : in std_logic := '0'; + SPURIOUS_TRG_IN : in std_logic := '0'; +-- + TRG_NUMBER_IN : in std_logic_vector(15 downto 0) := (others => '0'); + TRG_CODE_IN : in std_logic_vector(7 downto 0) := (others => '0'); + TRG_INFORMATION_IN : in std_logic_vector(23 downto 0) := (others => '0'); + TRG_TYPE_IN : in std_logic_vector(3 downto 0) := (others => '0'); +-- + --Response to handler + TRG_RELEASE_OUT : out std_logic; + TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATA_WRITE_OUT : out std_logic; + DATA_FINISHED_OUT : out std_logic; +-- + --To Bus Handler + HCB_READ_EN_IN : in std_logic; + HCB_WRITE_EN_IN : in std_logic; + HCB_ADDR_IN : in std_logic_vector(6 downto 0); + HCB_DATA_OUT : out std_logic_vector(31 downto 0); + HCB_DATAREADY_OUT : out std_logic; + HCB_UNKNOWN_ADDR_OUT : out std_logic; + SRB_READ_EN_IN : in std_logic; + SRB_WRITE_EN_IN : in std_logic; + SRB_ADDR_IN : in std_logic_vector(6 downto 0); + SRB_DATA_OUT : out std_logic_vector(31 downto 0); + SRB_DATAREADY_OUT : out std_logic; + SRB_UNKNOWN_ADDR_OUT : out std_logic; + ESB_READ_EN_IN : in std_logic; + ESB_WRITE_EN_IN : in std_logic; + ESB_ADDR_IN : in std_logic_vector(6 downto 0); + ESB_DATA_OUT : out std_logic_vector(31 downto 0); + ESB_DATAREADY_OUT : out std_logic; + ESB_UNKNOWN_ADDR_OUT : out std_logic; + EFB_READ_EN_IN : in std_logic; + EFB_WRITE_EN_IN : in std_logic; + EFB_ADDR_IN : in std_logic_vector(6 downto 0); + EFB_DATA_OUT : out std_logic_vector(31 downto 0); + EFB_DATAREADY_OUT : out std_logic; + EFB_UNKNOWN_ADDR_OUT : out std_logic; + LHB_READ_EN_IN : in std_logic; + LHB_WRITE_EN_IN : in std_logic; + LHB_ADDR_IN : in std_logic_vector(6 downto 0); + LHB_DATA_OUT : out std_logic_vector(31 downto 0); + LHB_DATAREADY_OUT : out std_logic; + LHB_UNKNOWN_ADDR_OUT : out std_logic; +-- + LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0); + CONTROL_REG_IN : in std_logic_vector(32*CONTROL_REG_NR-1 downto 0) + ); +end TDC; + +architecture TDC of TDC is + +------------------------------------------------------------------------------- +-- Signal Declarations +------------------------------------------------------------------------------- +-- Reset Signals + signal reset_rdo : std_logic; + signal reset_rdo_i : std_logic; + signal reset_tdc : std_logic; + signal reset_tdc_i : std_logic; +-- Coarse counters + signal coarse_cntr : std_logic_vector_array_11(1 to 4); + signal coarse_cntr_reset : std_logic; + signal coarse_cntr_reset_r : std_logic_vector(4 downto 1); +-- Slow control + signal logic_anal_control : std_logic_vector(3 downto 0); + signal debug_mode_en_i : std_logic; + signal reset_counters_i : std_logic; + signal run_mode_i : std_logic; -- 1: cc reset every trigger + -- 0: free running mode + signal run_mode_200 : std_logic; + signal run_mode_edge_200 : std_logic; + signal reset_coarse_cntr_i : std_logic; + signal reset_coarse_cntr_200 : std_logic; + signal reset_coarse_cntr_edge_200 : std_logic; + signal reset_coarse_cntr_flag : std_logic := '0'; + signal ch_en_i : std_logic_vector(64 downto 1); + signal data_limit_i : unsigned(7 downto 0); + signal calibration_on : std_logic; -- turns on calibration for trig type 0xC +-- Logic analyser + signal logic_anal_data_i : std_logic_vector(3*32-1 downto 0); +-- Hit signals + signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 1); + signal hit_latch : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0'); + signal hit_reg : std_logic_vector(CHANNEL_NUMBER-1 downto 1); + signal hit_2reg : std_logic_vector(CHANNEL_NUMBER-1 downto 1); +-- To the channels + signal rd_en_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal trg_win_end_i : std_logic; +-- From the channels + signal ch_data_i : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + signal ch_data_valid_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal ch_wcnt_i : unsigned_array_8(0 to CHANNEL_NUMBER-1); + signal ch_empty_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal ch_full_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal ch_almost_empty_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal ch_almost_full_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal trg_time_i : std_logic_vector(38 downto 0); + signal ch_lost_hit_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); + signal ch_hit_detect_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); + signal ch_encoder_start_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); + signal ch_encoder_finished_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); + signal ch_level_hit_number : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); + signal ch_lost_hit_bus_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); + signal ch_encoder_start_bus_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); + signal ch_encoder_finished_bus_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); + signal ch_fifo_write_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); +-- To the endpoint + signal data_finished_i : std_logic; +-- Epoch counter + signal epoch_cntr : std_logic_vector(27 downto 0); + signal epoch_cntr_up_i : std_logic; + signal epoch_cntr_reset_i : std_logic; +-- Trigger Handler signals + signal trig_rdo_i : std_logic; + signal trig_tdc_i : std_logic; + signal trig_win_en_i : std_logic; + signal trig_win_end_rdo : std_logic; + signal trig_win_end_tdc : std_logic; + +-- Debug signals + signal ref_debug_i : std_logic_vector(31 downto 0); + signal ch_debug_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); + signal ch_200_debug_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); + signal readout_debug_i : std_logic_vector(31 downto 0); +-- Bus signals + signal status_registers_bus_i : std_logic_vector_array_32(0 to 21); + + attribute syn_keep : boolean; + attribute syn_keep of reset_tdc : signal is true; + attribute syn_keep of coarse_cntr : signal is true; + attribute syn_preserve : boolean; + attribute syn_preserve of coarse_cntr : signal is true; + +begin + +-- Slow control signals + logic_anal_control <= CONTROL_REG_IN(3 downto 0) when rising_edge(CLK_READOUT); + debug_mode_en_i <= CONTROL_REG_IN(4); + reset_counters_i <= CONTROL_REG_IN(8) or reset_tdc when rising_edge(CLK_TDC); + run_mode_i <= CONTROL_REG_IN(12); + run_mode_200 <= run_mode_i when rising_edge(CLK_TDC); -- Run mode control register synchronised to the coarse counter clk + reset_coarse_cntr_i <= CONTROL_REG_IN(13); + reset_coarse_cntr_200 <= reset_coarse_cntr_i when rising_edge(CLK_TDC); -- Reset coarse counter control register synchronised to the coarse counter clk + + trig_win_en_i <= CONTROL_REG_IN(1*32+31); + ch_en_i <= CONTROL_REG_IN(3*32+31 downto 2*32+0); + data_limit_i <= unsigned(CONTROL_REG_IN(4*32+7 downto 4*32+0)); + +-- Reset signals + reset_tdc_i <= RESET when rising_edge(CLK_TDC); + reset_tdc <= reset_tdc_i when rising_edge(CLK_TDC); + reset_rdo_i <= RESET when rising_edge(CLK_READOUT); + reset_rdo <= reset_rdo_i when rising_edge(CLK_READOUT); + + + -- Blocks the input after the rising edge against short pulses + GEN_HitBlock : for i in 1 to CHANNEL_NUMBER-1 generate + TheStretcher : process (HIT_IN, hit_2reg) + begin + if hit_2reg(i) = '1' then + hit_latch(i) <= '0'; + elsif rising_edge(HIT_IN(i)) then + hit_latch(i) <= '1'; + end if; + end process TheStretcher; + end generate GEN_HitBlock; + hit_reg <= hit_latch when rising_edge(CLK_TDC); + hit_2reg <= hit_reg when rising_edge(CLK_TDC); + +-- Channel and calibration enable signals + GEN_Channel_Enable : for i in 1 to CHANNEL_NUMBER-1 generate + process (ch_en_i, calibration_on, HIT_CALIBRATION, hit_latch) + begin + if ch_en_i(i) = '1' then + if calibration_on = '1' then + hit_in_i(i) <= HIT_CALIBRATION; + else + hit_in_i(i) <= hit_latch(i); + end if; + else + hit_in_i(i) <= '0'; + end if; + end process; + end generate GEN_Channel_Enable; + + CalibrationSwitch : process (CLK_READOUT) + begin + if rising_edge(CLK_READOUT) then + if TRG_TYPE_IN = x"D" then + calibration_on <= '1'; + else + calibration_on <= '0'; + end if; + end if; + end process CalibrationSwitch; + + -- Reference channel + --The_Reference_Channel : Reference_Channel + -- generic map ( + -- CHANNEL_ID => 0) + -- port map ( + -- RESET_200 => reset_tdc, + -- RESET_100 => reset_rdo, + -- CLK_200 => CLK_TDC, + -- CLK_100 => CLK_READOUT, + -- HIT_IN => REFERENCE_TIME, + -- READ_EN_IN => rd_en_i(0), + -- VALID_TMG_TRG_IN => VALID_TIMING_TRG_IN, + -- SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, + -- MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, + -- FIFO_DATA_OUT => open, --ch_data_i(0), + -- FIFO_WCNT_OUT => open, --ch_wcnt_i(0), + -- FIFO_EMPTY_OUT => open, --ch_empty_i(0), + -- FIFO_FULL_OUT => open, --ch_full_i(0), + -- FIFO_ALMOST_FULL_OUT => ch_almost_full_i(0), + -- COARSE_COUNTER_IN => coarse_cntr(1), + -- EPOCH_COUNTER_IN => epoch_cntr, + -- TRIGGER_WINDOW_END_IN => trg_win_end_i, + -- DATA_FINISHED_IN => data_finished_i, + -- RUN_MODE => run_mode_i, + -- TRIGGER_TIME_STAMP_OUT => open, -- not used after tdc_v1.5.2 --trg_time_i, + -- REF_DEBUG_OUT => ref_debug_i); + --ch_data_i(0) <= x"F00000000"; + --ch_data_valid_i(0) <= '0'; + --ch_empty_i(0) <= '1'; + --ch_full_i(0) <= '0'; + --ch_almost_empty_i(0) <= '0'; + --ch_almost_full_i(0) <= '0'; + + ReferenceChannel : Channel + generic map ( + CHANNEL_ID => 0, + DEBUG => DEBUG, + SIMULATION => SIMULATION, + REFERENCE => c_YES) + port map ( + RESET_200 => reset_tdc, + RESET_100 => reset_rdo, + RESET_COUNTERS => reset_counters_i, + CLK_200 => CLK_TDC, + CLK_100 => CLK_READOUT, + HIT_IN => REFERENCE_TIME, + TRIGGER_WIN_END_TDC => trig_win_end_tdc, + TRIGGER_WIN_END_RDO => trig_win_end_rdo, + EPOCH_COUNTER_IN => epoch_cntr, + COARSE_COUNTER_IN => coarse_cntr(1), + READ_EN_IN => rd_en_i(0), + FIFO_DATA_OUT => ch_data_i(0), + FIFO_DATA_VALID_OUT => ch_data_valid_i(0), + FIFO_EMPTY_OUT => ch_empty_i(0), + FIFO_FULL_OUT => ch_full_i(0), + FIFO_ALMOST_EMPTY_OUT => ch_almost_empty_i(0), + FIFO_ALMOST_FULL_OUT => ch_almost_full_i(0), + VALID_TIMING_TRG_IN => VALID_TIMING_TRG_IN, + SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, + MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, + EPOCH_WRITE_EN_IN => '1', + LOST_HIT_NUMBER => ch_lost_hit_number_i(0), + HIT_DETECT_NUMBER => ch_hit_detect_number_i(0), + ENCODER_START_NUMBER => ch_encoder_start_number_i(0), + ENCODER_FINISHED_NUMBER => ch_encoder_finished_number_i(0), + FIFO_WRITE_NUMBER => ch_fifo_write_number_i(0), + Channel_200_DEBUG => ch_200_debug_i(0), + Channel_DEBUG => ch_debug_i(0)); + + GEN_Channels : for i in 1 to CHANNEL_NUMBER-1 generate + Channels : Channel + generic map ( + CHANNEL_ID => i, + DEBUG => DEBUG, + SIMULATION => SIMULATION, + REFERENCE => c_NO) + port map ( + RESET_200 => reset_tdc, + RESET_100 => reset_rdo, + RESET_COUNTERS => reset_counters_i, + CLK_200 => CLK_TDC, + CLK_100 => CLK_READOUT, + HIT_IN => hit_in_i(i), + TRIGGER_WIN_END_TDC => trig_win_end_tdc, + TRIGGER_WIN_END_RDO => trig_win_end_rdo, + EPOCH_COUNTER_IN => epoch_cntr, + COARSE_COUNTER_IN => coarse_cntr(integer(floor(real(i)/real(16)))+1), + READ_EN_IN => rd_en_i(i), + FIFO_DATA_OUT => ch_data_i(i), + FIFO_DATA_VALID_OUT => ch_data_valid_i(i), + FIFO_EMPTY_OUT => ch_empty_i(i), + FIFO_FULL_OUT => ch_full_i(i), + FIFO_ALMOST_EMPTY_OUT => ch_almost_empty_i(i), + FIFO_ALMOST_FULL_OUT => ch_almost_full_i(i), + VALID_TIMING_TRG_IN => VALID_TIMING_TRG_IN, + SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, + MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, + EPOCH_WRITE_EN_IN => '1', + LOST_HIT_NUMBER => ch_lost_hit_number_i(i), + HIT_DETECT_NUMBER => ch_hit_detect_number_i(i), + ENCODER_START_NUMBER => ch_encoder_start_number_i(i), + ENCODER_FINISHED_NUMBER => ch_encoder_finished_number_i(i), + FIFO_WRITE_NUMBER => ch_fifo_write_number_i(i), + Channel_200_DEBUG => ch_200_debug_i(i), + Channel_DEBUG => ch_debug_i(i)); + end generate GEN_Channels; + ch_data_i(CHANNEL_NUMBER) <= (others => '1'); + + -- Trigger handler + TheTriggerHandler : TriggerHandler + generic map ( + TRIGGER_NUM => 1, + PHYSICAL_EVENT_TRG_NUM => 0) + port map ( + CLK_TRG => CLK_READOUT, + CLK_RDO => CLK_READOUT, + CLK_TDC => CLK_TDC, + RESET_TRG => reset_rdo, + RESET_RDO => reset_rdo, + RESET_TDC => reset_tdc, + TRIGGER_IN(0) => REFERENCE_TIME, + TRIGGER_RDO_OUT(0) => trig_rdo_i, + TRIGGER_TDC_OUT(0) => trig_tdc_i, + TRIGGER_WIN_EN_IN => trig_win_en_i, + TRIGGER_WIN_POST_IN => unsigned(TRG_WIN_POST), + TRIGGER_WIN_END_RDO_OUT => trig_win_end_rdo, + TRIGGER_WIN_END_TDC_OUT => trig_win_end_tdc); + + -- Readout + TheReadout : Readout + generic map ( + CHANNEL_NUMBER => CHANNEL_NUMBER, + TDC_VERSION => TDC_VERSION) + port map ( + RESET_100 => reset_rdo, + RESET_200 => reset_tdc, + RESET_COUNTERS => reset_counters_i, + CLK_100 => CLK_READOUT, + CLK_200 => CLK_TDC, + TRIGGER_RDO_IN => trig_rdo_i, + TRIGGER_TDC_IN => trig_tdc_i, + CH_DATA_IN => ch_data_i, + CH_DATA_VALID_IN => ch_data_valid_i, + CH_EMPTY_IN => ch_empty_i, + CH_FULL_IN => ch_full_i, + CH_ALMOST_EMPTY_IN => ch_almost_empty_i, + CH_ALMOST_FULL_IN => ch_almost_full_i, + TRG_DATA_VALID_IN => TRG_DATA_VALID_IN, + VALID_TIMING_TRG_IN => VALID_TIMING_TRG_IN, + VALID_NOTIMING_TRG_IN => VALID_NOTIMING_TRG_IN, + INVALID_TRG_IN => INVALID_TRG_IN, + TMGTRG_TIMEOUT_IN => TMGTRG_TIMEOUT_IN, + SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, + MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, + SPURIOUS_TRG_IN => SPURIOUS_TRG_IN, + TRG_NUMBER_IN => TRG_NUMBER_IN, + TRG_CODE_IN => TRG_CODE_IN, + TRG_INFORMATION_IN => TRG_INFORMATION_IN, + TRG_TYPE_IN => TRG_TYPE_IN, + DATA_LIMIT_IN => data_limit_i, + TRG_RELEASE_OUT => TRG_RELEASE_OUT, + TRG_STATUSBIT_OUT => TRG_STATUSBIT_OUT, + DATA_OUT => DATA_OUT, + DATA_WRITE_OUT => DATA_WRITE_OUT, + DATA_FINISHED_OUT => data_finished_i, + READ_EN_OUT => rd_en_i, + TRG_WIN_PRE => TRG_WIN_PRE, + TRG_WIN_POST => TRG_WIN_POST, + TRIGGER_WIN_EN_IN => trig_win_en_i, + TRIG_WIN_END_TDC_IN => trig_win_end_tdc, + TRIG_WIN_END_RDO_IN => trig_win_end_rdo, + COARSE_COUNTER_IN => coarse_cntr(1), + EPOCH_COUNTER_IN => epoch_cntr, + DEBUG_MODE_EN_IN => debug_mode_en_i, + STATUS_REGISTERS_BUS_OUT => status_registers_bus_i(0 to 20), + READOUT_DEBUG => readout_debug_i, + REFERENCE_TIME => REFERENCE_TIME, +-- ports not used after tdc_v1.5.2 + TRIGGER_WIN_END_OUT => trg_win_end_i, -- obselete + CH_WCNT_IN => (others => (others => '0')), + TRIGGER_TIME_IN => (others => '0') + ); + DATA_FINISHED_OUT <= data_finished_i; + +-- Coarse counter + GenCoarseCounter : for i in 1 to 4 generate + TheCoarseCounter : up_counter + generic map ( + NUMBER_OF_BITS => 11) + port map ( + CLK => CLK_TDC, + RESET => coarse_cntr_reset_r(i), + COUNT_OUT => coarse_cntr(i), + UP_IN => '1'); + end generate GenCoarseCounter; + + Coarse_Counter_Reset : process (CLK_TDC) + begin + if rising_edge(CLK_TDC) then + if reset_tdc = '1' then + coarse_cntr_reset <= '1'; + elsif run_mode_200 = '0' then + coarse_cntr_reset <= trig_win_end_tdc; + elsif run_mode_edge_200 = '1' then + coarse_cntr_reset <= '1'; + elsif reset_coarse_cntr_flag = '1' and (VALID_TIMING_TRG_IN = '1' or VALID_NOTIMING_TRG_IN = '1') then + coarse_cntr_reset <= '1'; + else + coarse_cntr_reset <= '0'; + end if; + if reset_coarse_cntr_edge_200 = '1' then + reset_coarse_cntr_flag <= '1'; + elsif VALID_TIMING_TRG_IN = '1' or VALID_NOTIMING_TRG_IN = '1' then + reset_coarse_cntr_flag <= '0'; + end if; + end if; + end process Coarse_Counter_Reset; + + Run_Mode_Edge_Detect : risingEdgeDetect + port map ( + CLK => CLK_TDC, + SIGNAL_IN => run_mode_200, + PULSE_OUT => run_mode_edge_200); + + Reset_Coarse_Counter_Edge_Detect : risingEdgeDetect + port map ( + CLK => CLK_TDC, + SIGNAL_IN => reset_coarse_cntr_200, + PULSE_OUT => reset_coarse_cntr_edge_200); + + GenCoarseCounterReset : for i in 1 to 4 generate + coarse_cntr_reset_r(i) <= coarse_cntr_reset when rising_edge(CLK_TDC); + end generate GenCoarseCounterReset; + +-- EPOCH counter + TheEpochCounter : up_counter + generic map ( + NUMBER_OF_BITS => 28) + port map ( + CLK => CLK_TDC, + RESET => epoch_cntr_reset_i, + COUNT_OUT => epoch_cntr, + UP_IN => epoch_cntr_up_i); + epoch_cntr_up_i <= and_all(coarse_cntr(1)); + epoch_cntr_reset_i <= coarse_cntr_reset_r(1); + +-- Bus handler entities + TheHitCounterBus : BusHandler + generic map ( + BUS_LENGTH => CHANNEL_NUMBER-1) + port map ( + RESET => reset_rdo, + CLK => CLK_READOUT, + DATA_IN => ch_level_hit_number, + READ_EN_IN => HCB_READ_EN_IN, + WRITE_EN_IN => HCB_WRITE_EN_IN, + ADDR_IN => HCB_ADDR_IN, + DATA_OUT => HCB_DATA_OUT, + DATAREADY_OUT => HCB_DATAREADY_OUT, + UNKNOWN_ADDR_OUT => HCB_UNKNOWN_ADDR_OUT); + + ch_level_hit_number(0)(31) <= REFERENCE_TIME when rising_edge(CLK_READOUT); + ch_level_hit_number(0)(30 downto 24) <= (others => '0'); + ch_level_hit_number(0)(23 downto 0) <= ch_hit_detect_number_i(0) when rising_edge(CLK_READOUT); + GenHitDetectNumber : for i in 1 to CHANNEL_NUMBER-1 generate + ch_level_hit_number(i)(31) <= HIT_IN(i) and ch_en_i(i) when rising_edge(CLK_READOUT); + ch_level_hit_number(i)(30 downto 24) <= (others => '0'); + ch_level_hit_number(i)(23 downto 0) <= ch_hit_detect_number_i(i) when rising_edge(CLK_READOUT); + end generate GenHitDetectNumber; + + TheStatusRegistersBus : BusHandler + generic map ( + BUS_LENGTH => 21) + port map ( + RESET => reset_rdo, + CLK => CLK_READOUT, + DATA_IN => status_registers_bus_i, + READ_EN_IN => SRB_READ_EN_IN, + WRITE_EN_IN => SRB_WRITE_EN_IN, + ADDR_IN => SRB_ADDR_IN, + DATA_OUT => SRB_DATA_OUT, + DATAREADY_OUT => SRB_DATAREADY_OUT, + UNKNOWN_ADDR_OUT => SRB_UNKNOWN_ADDR_OUT); + + status_registers_bus_i(21) <= ch_200_debug_i(0); + + --TheLostHitBus : BusHandler + -- generic map ( + -- BUS_LENGTH => CHANNEL_NUMBER-1) + -- port map ( + -- RESET => reset_rdo, + -- CLK => CLK_READOUT, + -- DATA_IN => ch_lost_hit_bus_i, + -- READ_EN_IN => LHB_READ_EN_IN, + -- WRITE_EN_IN => LHB_WRITE_EN_IN, + -- ADDR_IN => LHB_ADDR_IN, + -- DATA_OUT => LHB_DATA_OUT, + -- DATAREADY_OUT => LHB_DATAREADY_OUT, + -- UNKNOWN_ADDR_OUT => LHB_UNKNOWN_ADDR_OUT); + + --GenLostHitNumber : for i in 1 to CHANNEL_NUMBER-1 generate + -- ch_lost_hit_bus_i(i) <= x"00" & ch_lost_hit_number_i(i) when rising_edge(CLK_READOUT); + --end generate GenLostHitNumber; + + --TheEncoderStartBus : BusHandler + -- generic map ( + -- BUS_LENGTH => CHANNEL_NUMBER-1) + -- port map ( + -- RESET => reset_rdo, + -- CLK => CLK_READOUT, + -- DATA_IN => ch_encoder_start_bus_i, + -- READ_EN_IN => ESB_READ_EN_IN, + -- WRITE_EN_IN => ESB_WRITE_EN_IN, + -- ADDR_IN => ESB_ADDR_IN, + -- DATA_OUT => ESB_DATA_OUT, + -- DATAREADY_OUT => ESB_DATAREADY_OUT, + -- UNKNOWN_ADDR_OUT => ESB_UNKNOWN_ADDR_OUT); + + --GenEncoderStartNumber : for i in 1 to CHANNEL_NUMBER-1 generate + -- ch_encoder_start_bus_i(i) <= x"00" & ch_encoder_start_number_i(i) when rising_edge(CLK_READOUT); + --end generate GenEncoderStartNumber; + + ESB_DATA_OUT <= (others => '0'); + ESB_DATAREADY_OUT <= '0'; + ESB_UNKNOWN_ADDR_OUT <= '0'; + + --TheEncoderFinishedBus : BusHandler + -- generic map ( + -- BUS_LENGTH => CHANNEL_NUMBER-1) + -- port map ( + -- RESET => reset_rdo, + -- CLK => CLK_READOUT, + -- DATA_IN => ch_encoder_finished_bus_i, + -- READ_EN_IN => EFB_READ_EN_IN, + -- WRITE_EN_IN => EFB_WRITE_EN_IN, + -- ADDR_IN => EFB_ADDR_IN, + -- DATA_OUT => EFB_DATA_OUT, + -- DATAREADY_OUT => EFB_DATAREADY_OUT, + -- UNKNOWN_ADDR_OUT => EFB_UNKNOWN_ADDR_OUT); + + --GenFifoWriteNumber : for i in 1 to CHANNEL_NUMBER-1 generate + -- ch_encoder_finished_bus_i(i) <= x"00" & ch_encoder_finished_number_i(i) when rising_edge(CLK_READOUT); + --end generate GenFifoWriteNumber; + + EFB_DATA_OUT <= (others => '0'); + EFB_DATAREADY_OUT <= '0'; + EFB_UNKNOWN_ADDR_OUT <= '0'; + +-- Logic Analyser + TheLogicAnalyser : LogicAnalyser + generic map ( + CHANNEL_NUMBER => CHANNEL_NUMBER) + port map ( + CLK => CLK_READOUT, + RESET => reset_rdo, + DATA_IN => logic_anal_data_i, + CONTROL_IN => logic_anal_control, + DATA_OUT => LOGIC_ANALYSER_OUT); + + logic_anal_data_i(7 downto 0) <= readout_debug_i(7 downto 0); + logic_anal_data_i(8) <= REFERENCE_TIME; + logic_anal_data_i(9) <= VALID_TIMING_TRG_IN; + logic_anal_data_i(10) <= VALID_NOTIMING_TRG_IN; + logic_anal_data_i(11) <= INVALID_TRG_IN; + logic_anal_data_i(12) <= TRG_DATA_VALID_IN; + logic_anal_data_i(13) <= readout_debug_i(8); --data_wr_reg; + logic_anal_data_i(14) <= readout_debug_i(9); --data_finished_reg; + logic_anal_data_i(15) <= readout_debug_i(10); --trg_release_reg; + logic_anal_data_i(31 downto 16) <= ref_debug_i(15 downto 0); + logic_anal_data_i(37 downto 32) <= readout_debug_i(16 downto 11); --data_out_reg(27 downto 22); + logic_anal_data_i(47 downto 38) <= (others => '0'); + logic_anal_data_i(63 downto 48) <= ch_debug_i(1)(15 downto 0); + logic_anal_data_i(95 downto 64) <= (others => '0'); + +end TDC; diff --git a/tdc_releases/tdc_v1.6/TriggerHandler.vhd b/tdc_releases/tdc_v1.6/TriggerHandler.vhd new file mode 100644 index 0000000..e0d5931 --- /dev/null +++ b/tdc_releases/tdc_v1.6/TriggerHandler.vhd @@ -0,0 +1,174 @@ +------------------------------------------------------------------------------- +-- Title : TriggerHandler +------------------------------------------------------------------------------- +-- File : TriggerHandler.vhd +-- Author : Cahit Ugur c.ugur@gsi.de +-- Created : 2013-03-13 +-- Last update: 2014-01-20 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +--use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; + + +entity TriggerHandler is + generic ( + TRIGGER_NUM : integer := 2; -- number of trigger signals sent + PHYSICAL_EVENT_TRG_NUM : integer := 0); -- physical event trigger input number for the trigger window calculations + port ( + CLK_TRG : in std_logic; -- trigger clock domain + CLK_RDO : in std_logic; -- readout clock domain + CLK_TDC : in std_logic; -- tdc clock domain + RESET_TRG : in std_logic; + RESET_RDO : in std_logic; + RESET_TDC : in std_logic; + TRIGGER_IN : in std_logic_vector(TRIGGER_NUM-1 downto 0); + TRIGGER_RDO_OUT : out std_logic_vector(TRIGGER_NUM-1 downto 0); + TRIGGER_TDC_OUT : out std_logic_vector(TRIGGER_NUM-1 downto 0); + TRIGGER_WIN_EN_IN : in std_logic; + TRIGGER_WIN_POST_IN : in unsigned(10 downto 0); + TRIGGER_WIN_END_RDO_OUT : out std_logic; + TRIGGER_WIN_END_TDC_OUT : out std_logic); + +end entity TriggerHandler; + +architecture behavioral of TriggerHandler is + + -- trigger signals + signal trigger_in_reg : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trigger_in_2reg : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trigger_in_3reg : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trigger_pulse_trg : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trigger_pulse_rdo : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trigger_pulse_tdc : std_logic_vector(TRIGGER_NUM-1 downto 0); + -- trigger window signals + type TriggerWinCounter_FSM is (IDLE, COUNT, WIN_END); + signal TrigWin_STATE : TriggerWinCounter_FSM; + signal trig_win_cnt_f : unsigned(10 downto 0); + signal trig_win_cnt_r : unsigned(10 downto 0); + signal trig_win_end_f : std_logic; + signal trig_win_end_tdc : std_logic; + signal trig_win_end_rdo : std_logic; + + +begin -- architecture behavioral + + -- the trigger signals have to be synced + trigger_in_reg <= TRIGGER_IN when rising_edge(CLK_TRG); + trigger_in_2reg <= trigger_in_reg when rising_edge(CLK_TRG); + trigger_in_3reg <= trigger_in_2reg when rising_edge(CLK_TRG); + + -- generate strobes out of trigger signals + GEN_Pulse : for i in 0 to TRIGGER_NUM-1 generate + TheRisingEdgeDetect : risingEdgeDetect + port map ( + CLK => CLK_TRG, + SIGNAL_IN => trigger_in_3reg(i), + PULSE_OUT => trigger_pulse_trg(i)); + end generate GEN_Pulse; + + -- sync the strobes to the readout clock domain + GEN_RDO : for i in 0 to TRIGGER_NUM-1 generate + ThePulseSync : pulse_sync + port map ( + CLK_A_IN => CLK_TRG, + RESET_A_IN => RESET_TRG, + PULSE_A_IN => trigger_pulse_trg(i), + CLK_B_IN => CLK_RDO, + RESET_B_IN => RESET_RDO, + PULSE_B_OUT => trigger_pulse_rdo(i)); + end generate GEN_RDO; + + -- sync the strobes to the tdc clock domain + GEN_TDC : for i in 0 to TRIGGER_NUM-1 generate + ThePulseSync : pulse_sync + port map ( + CLK_A_IN => CLK_TRG, + RESET_A_IN => RESET_TRG, + PULSE_A_IN => trigger_pulse_trg(i), + CLK_B_IN => CLK_TDC, + RESET_B_IN => RESET_TDC, + PULSE_B_OUT => trigger_pulse_tdc(i)); + end generate GEN_TDC; + + TRIGGER_RDO_OUT <= trigger_pulse_rdo; + TRIGGER_TDC_OUT <= trigger_pulse_tdc; + + -- A Moore machine's outputs are dependent only on the current state. + -- The output is written only when the state changes. (State + -- transitions are synchronous.) + -- Logic to advance to the next state + TrigWinState : process (CLK_TDC) + begin + if rising_edge(CLK_TDC) then + if RESET_TDC = '1' then + TrigWin_STATE <= IDLE; + else + case TrigWin_STATE is + when IDLE => + if trigger_pulse_tdc(0) = '1' then + if TRIGGER_WIN_EN_IN = '1' then + TrigWin_STATE <= COUNT; + else + TrigWin_STATE <= WIN_END; + end if; + --elsif trigger_pulse_tdc(1) = '1' then + -- TrigWin_STATE <= WIN_END; + else + TrigWin_STATE <= IDLE; + end if; + when COUNT => + if trig_win_cnt_r = TRIGGER_WIN_POST_IN + to_unsigned(4,11) then + TrigWin_STATE <= WIN_END; + else + TrigWin_STATE <= COUNT; + end if; + when WIN_END => + TrigWin_STATE <= IDLE; + when others => + TrigWin_STATE <= IDLE; + end case; + end if; + end if; + end process TrigWinState; + + -- Output depends solely on the current state + TrigWinOutput : process (TrigWin_STATE, trig_win_cnt_r) + begin + trig_win_cnt_f <= "00000000011"; + trig_win_end_f <= '0'; + case TrigWin_STATE is + when IDLE => + + when COUNT => + trig_win_cnt_f <= trig_win_cnt_r + to_unsigned(1, 1); + when WIN_END => + trig_win_end_f <= '1'; + end case; + end process TrigWinOutput; + trig_win_cnt_r <= trig_win_cnt_f when rising_edge(CLK_TDC); + trig_win_end_tdc <= trig_win_end_f when rising_edge(CLK_TDC); + + -- syn trigger window end strobe to readout clock domain + ThePulseSync : pulse_sync + port map ( + CLK_A_IN => CLK_TDC, + RESET_A_IN => RESET_TDC, + PULSE_A_IN => trig_win_end_tdc, + CLK_B_IN => CLK_RDO, + RESET_B_IN => RESET_RDO, + PULSE_B_OUT => trig_win_end_rdo); + + TRIGGER_WIN_END_TDC_OUT <= trig_win_end_tdc; + TRIGGER_WIN_END_RDO_OUT <= trig_win_end_rdo when rising_edge(CLK_RDO); + + +end architecture behavioral; diff --git a/tdc_releases/tdc_v1.6/bit_sync.vhd b/tdc_releases/tdc_v1.6/bit_sync.vhd new file mode 100644 index 0000000..ba9adb2 --- /dev/null +++ b/tdc_releases/tdc_v1.6/bit_sync.vhd @@ -0,0 +1,60 @@ +--synchronizes a single bit to a different clock domain + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity bit_sync is + generic( + DEPTH : integer := 3 + ); + port( + RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register + CLK0 : in std_logic; --clock for first FF + CLK1 : in std_logic; --Clock for other FF + D_IN : in std_logic; --Data input + D_OUT : out std_logic --Data output + ); +end entity; + +architecture behavioral of bit_sync is + + signal sync_q : std_logic_vector(DEPTH downto 0); + + attribute syn_preserve : boolean; + attribute syn_keep : boolean; + attribute syn_keep of sync_q : signal is true; + attribute syn_preserve of sync_q : signal is true; + + +begin + sync_q(0) <= D_IN; + D_OUT <= sync_q(DEPTH); + + process(CLK0) + begin + if rising_edge(CLK0) then + if RESET = '1' then + sync_q(1) <= '0'; + else + sync_q(1) <= sync_q(0); + end if; + end if; + end process; + + gen_others : if DEPTH > 1 generate + gen_flipflops : for i in 2 to DEPTH generate + process(CLK1) + begin + if rising_edge(CLK1) then + if RESET = '1' then + sync_q(i) <= '0'; + else + sync_q(i) <= sync_q(i-1); + end if; + end if; + end process; + end generate; + end generate; + +end architecture; diff --git a/tdc_releases/tdc_v1.6/fallingEdgeDetect.vhd b/tdc_releases/tdc_v1.6/fallingEdgeDetect.vhd new file mode 100644 index 0000000..f413d0b --- /dev/null +++ b/tdc_releases/tdc_v1.6/fallingEdgeDetect.vhd @@ -0,0 +1,17 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity fallingEdgeDetect is + port (CLK : in std_logic; + SIGNAL_IN : in std_logic; + PULSE_OUT : out std_logic); +end fallingEdgeDetect; + +architecture Behavioral of fallingEdgeDetect is + + signal signal_d : std_logic; + +begin + signal_d <= SIGNAL_IN when rising_edge(CLK); + PULSE_OUT <= (not SIGNAL_IN) and signal_d when rising_edge(CLK); +end Behavioral; diff --git a/tdc_releases/tdc_v1.6/risingEdgeDetect.vhd b/tdc_releases/tdc_v1.6/risingEdgeDetect.vhd new file mode 100644 index 0000000..fad9f7e --- /dev/null +++ b/tdc_releases/tdc_v1.6/risingEdgeDetect.vhd @@ -0,0 +1,17 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity risingEdgeDetect is + port (CLK : in std_logic; + SIGNAL_IN : in std_logic; + PULSE_OUT : out std_logic); +end risingEdgeDetect; + +architecture Behavioral of risingEdgeDetect is + + signal signal_d : std_logic; + +begin + signal_d <= SIGNAL_IN when rising_edge(CLK); + PULSE_OUT <= (not signal_d) and SIGNAL_IN when rising_edge(CLK); +end Behavioral; diff --git a/tdc_releases/tdc_v1.6/tdc_constraints.lpf b/tdc_releases/tdc_v1.6/tdc_constraints.lpf new file mode 100644 index 0000000..1914698 --- /dev/null +++ b/tdc_releases/tdc_v1.6/tdc_constraints.lpf @@ -0,0 +1,925 @@ +################################################################# +# TDC Constraints +################################################################# +############################################################################## +## REGION DECLERATION ## +############################################################################## +REGION "REGION_UR_CC" "R51C106D" 4 3 DEVSIZE; +REGION "REGION_LR_CC" "R85C106D" 3 3 DEVSIZE; +REGION "REGION_UL_CC" "R48C53D" 3 3 DEVSIZE; +REGION "REGION_LL_CC" "R90C53D" 3 3 DEVSIZE; + + +############################################################################## +## REFERENCE CHANNEL PLACEMENT ## +############################################################################## +UGROUP "Ref_Ch" BBOX 1 51 + BLKNAME THE_TDC/ReferenceChannel/Channel200/SimAdderNo_FC; +LOCATE UGROUP "Ref_Ch" SITE "R8C131D" ; +UGROUP "ref_hit" BBOX 1 1 + BLKNAME THE_TDC/ReferenceChannel/hit_buf_RNO; +LOCATE UGROUP "ref_hit" SITE "R9C133D" ; +UGROUP "Ref_ff_en" BBOX 1 1 + BLKNAME THE_TDC/ReferenceChannel/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "Ref_ff_en" SITE "R8C156D" ; + +############################################################################## +## DELAY LINE and HIT BUFFER PLACEMENTS ## +############################################################################## +UGROUP "FC_1" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_1" SITE "R10C131D" ; +UGROUP "hit_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_1_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_1" SITE "R11C133D" ; +UGROUP "ff_en_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_1" SITE "R10C156D" ; +# +UGROUP "FC_2" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_2" SITE "R21C131D" ; +UGROUP "hit_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_2_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_2" SITE "R22C133D" ; +UGROUP "ff_en_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_2" SITE "R21C156D" ; +# +UGROUP "FC_3" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_3" SITE "R23C131D" ; +UGROUP "hit_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_3_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_3" SITE "R24C133D" ; +UGROUP "ff_en_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_3" SITE "R23C156D" ; +# +UGROUP "FC_4" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_4" SITE "R30C131D" ; +UGROUP "hit_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_4_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_4" SITE "R31C133D" ; +UGROUP "ff_en_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_4" SITE "R30C156D" ; +# +UGROUP "FC_5" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_5" SITE "R32C131D" ; +UGROUP "hit_5" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_5_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_5" SITE "R33C133D" ; +UGROUP "ff_en_5" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_5" SITE "R32C156D" ; +# +UGROUP "FC_6" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_6" SITE "R35C131D" ; +UGROUP "hit_6" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_6_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_6" SITE "R36C133D" ; +UGROUP "ff_en_6" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_6" SITE "R35C156D" ; +# +UGROUP "FC_7" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_7" SITE "R37C131D" ; +UGROUP "hit_7" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_7_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_7" SITE "R38C133D" ; +UGROUP "ff_en_7" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_7" SITE "R37C156D" ; +# +UGROUP "FC_8" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_8" SITE "R48C131D" ; +UGROUP "hit_8" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_8_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_8" SITE "R49C133D" ; +UGROUP "ff_en_8" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_8" SITE "R48C156D" ; +# +UGROUP "FC_9" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_9" SITE "R50C131D" ; +UGROUP "hit_9" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_9_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_9" SITE "R51C133D" ; +UGROUP "ff_en_9" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_9" SITE "R50C156D" ; +# +UGROUP "FC_10" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_10" SITE "R53C131D" ; +UGROUP "hit_10" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_10_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_10" SITE "R54C133D" ; +UGROUP "ff_en_10" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_10" SITE "R53C156D" ; +# +UGROUP "FC_11" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_11" SITE "R55C131D" ; +UGROUP "hit_11" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_11_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_11" SITE "R56C133D" ; +UGROUP "ff_en_11" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_11" SITE "R55C156D" ; +# +UGROUP "FC_12" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_12" SITE "R10C58D" ; +UGROUP "hit_12" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_12_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_12" SITE "R11C60D" ; +UGROUP "ff_en_12" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_12" SITE "R10C83D" ; +# +UGROUP "FC_13" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_13" SITE "R23C58D" ; +UGROUP "hit_13" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_13_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_13" SITE "R24C60D" ; +UGROUP "ff_en_13" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_13" SITE "R23C83D" ; +# +UGROUP "FC_14" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_14" SITE "R32C58D" ; +UGROUP "hit_14" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_14_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_14" SITE "R33C60D" ; +UGROUP "ff_en_14" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_14" SITE "R32C83D" ; +# +UGROUP "FC_15" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_15" SITE "R37C58D" ; +UGROUP "hit_15" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_15_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_15" SITE "R38C60D" ; +UGROUP "ff_en_15" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_15" SITE "R37C83D" ; +# +UGROUP "FC_16" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_16" SITE "R50C58D" ; +UGROUP "hit_16" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_16_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_16" SITE "R51C60D" ; +UGROUP "ff_en_16" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_16" SITE "R50C83D" ; +# +UGROUP "FC_17" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_17" SITE "R66C131D" ; +UGROUP "hit_17" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_17_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_17" SITE "R67C133D" ; +UGROUP "ff_en_17" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_17" SITE "R66C156D" ; +# +UGROUP "FC_18" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_18" SITE "R68C131D" ; +UGROUP "hit_18" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_18_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_18" SITE "R69C133D" ; +UGROUP "ff_en_18" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_18" SITE "R68C156D" ; +# +UGROUP "FC_19" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_19" SITE "R71C131D" ; +UGROUP "hit_19" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_19_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_19" SITE "R72C133D" ; +UGROUP "ff_en_19" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_19" SITE "R71C156D" ; +# +UGROUP "FC_20" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_20" SITE "R73C131D" ; +UGROUP "hit_20" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_20_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_20" SITE "R74C133D" ; +UGROUP "ff_en_20" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_20" SITE "R73C156D" ; +# +UGROUP "FC_21" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_21" SITE "R84C131D" ; +UGROUP "hit_21" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_21_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_21" SITE "R85C133D" ; +UGROUP "ff_en_21" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_21" SITE "R84C156D" ; +# +UGROUP "FC_22" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_22" SITE "R86C131D" ; +UGROUP "hit_22" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_22_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_22" SITE "R87C133D" ; +UGROUP "ff_en_22" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_22" SITE "R86C156D" ; +# +UGROUP "FC_23" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_23" SITE "R89C131D" ; +UGROUP "hit_23" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_23_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_23" SITE "R90C133D" ; +UGROUP "ff_en_23" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_23" SITE "R89C156D" ; +# +UGROUP "FC_24" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_24" SITE "R91C131D" ; +UGROUP "hit_24" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_24_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_24" SITE "R92C133D" ; +UGROUP "ff_en_24" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_24" SITE "R91C156D" ; +# +UGROUP "FC_25" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_25" SITE "R102C131D" ; +UGROUP "hit_25" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_25_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_25" SITE "R103C133D" ; +UGROUP "ff_en_25" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_25" SITE "R102C156D" ; +# +UGROUP "FC_26" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_26" SITE "R104C131D" ; +UGROUP "hit_26" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_26_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_26" SITE "R105C133D" ; +UGROUP "ff_en_26" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_26" SITE "R104C156D" ; +# +UGROUP "FC_27" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_27" SITE "R111C131D" ; +UGROUP "hit_27" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_27_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_27" SITE "R112C133D" ; +UGROUP "ff_en_27" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_27" SITE "R111C156D" ; +# +UGROUP "FC_28" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_28" SITE "R113C131D" ; +UGROUP "hit_28" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_28_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_28" SITE "R114C133D" ; +UGROUP "ff_en_28" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_28" SITE "R113C156D" ; +# +UGROUP "FC_29" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_29" SITE "R91C58D" ; +UGROUP "hit_29" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_29_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_29" SITE "R92C60D" ; +UGROUP "ff_en_29" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_29" SITE "R91C83D" ; +# +UGROUP "FC_30" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_30" SITE "R104C58D" ; +UGROUP "hit_30" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_30_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_30" SITE "R105C60D" ; +UGROUP "ff_en_30" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_30" SITE "R104C83D" ; +# +UGROUP "FC_31" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_31" SITE "R113C58D" ; +UGROUP "hit_31" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_31_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_31" SITE "R114C60D" ; +UGROUP "ff_en_31" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_31" SITE "R113C83D" ; +# +UGROUP "FC_32" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_32" SITE "R84C58D" ; +UGROUP "hit_32" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_32_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_32" SITE "R85C60D" ; +UGROUP "ff_en_32" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_32" SITE "R84C83D" ; +# +UGROUP "FC_33" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_33" SITE "R8C58D" ; +UGROUP "hit_33" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_33_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_33" SITE "R9C60D" ; +UGROUP "ff_en_33" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_33" SITE "R8C83D" ; +# +UGROUP "FC_34" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_34" SITE "R21C58D" ; +UGROUP "hit_34" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_34_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_34" SITE "R22C60D" ; +UGROUP "ff_en_34" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_34" SITE "R21C83D" ; +# +UGROUP "FC_35" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_35" SITE "R30C58D" ; +UGROUP "hit_35" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_35_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_35" SITE "R31C60D" ; +UGROUP "ff_en_35" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_35" SITE "R30C83D" ; +# +UGROUP "FC_36" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_36" SITE "R35C58D" ; +UGROUP "hit_36" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_36_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_36" SITE "R36C60D" ; +UGROUP "ff_en_36" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_36" SITE "R35C83D" ; +# +UGROUP "FC_37" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_37" SITE "R48C58D" ; +UGROUP "hit_37" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_37_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_37" SITE "R49C60D" ; +UGROUP "ff_en_37" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_37" SITE "R48C83D" ; +# +UGROUP "FC_38" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_38" SITE "R8C2D" ; +UGROUP "hit_38" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_38_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_38" SITE "R9C4D" ; +UGROUP "ff_en_38" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_38" SITE "R8C27D" ; +# +UGROUP "FC_39" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_39" SITE "R10C2D" ; +UGROUP "hit_39" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_39_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_39" SITE "R11C4D" ; +UGROUP "ff_en_39" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_39" SITE "R10C27D" ; +# +UGROUP "FC_40" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_40" SITE "R21C2D" ; +UGROUP "hit_40" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_40_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_40" SITE "R22C4D" ; +UGROUP "ff_en_40" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_40" SITE "R21C27D" ; +# +UGROUP "FC_41" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_41" SITE "R23C2D" ; +UGROUP "hit_41" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_41_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_41" SITE "R24C4D" ; +UGROUP "ff_en_41" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_41" SITE "R23C27D" ; +# +UGROUP "FC_42" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_42" SITE "R30C2D" ; +UGROUP "hit_42" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_42_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_42" SITE "R31C4D" ; +UGROUP "ff_en_42" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_42" SITE "R30C27D" ; +# +UGROUP "FC_43" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_43" SITE "R32C2D" ; +UGROUP "hit_43" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_43_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_43" SITE "R33C4D" ; +UGROUP "ff_en_43" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_43" SITE "R32C27D" ; +# +UGROUP "FC_44" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_44" SITE "R35C2D" ; +UGROUP "hit_44" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_44_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_44" SITE "R36C4D" ; +UGROUP "ff_en_44" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_44" SITE "R35C27D" ; +# +UGROUP "FC_45" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_45" SITE "R37C2D" ; +UGROUP "hit_45" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_45_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_45" SITE "R38C4D" ; +UGROUP "ff_en_45" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_45" SITE "R37C27D" ; +# +UGROUP "FC_46" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_46" SITE "R48C2D" ; +UGROUP "hit_46" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_46_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_46" SITE "R49C4D" ; +UGROUP "ff_en_46" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_46" SITE "R48C27D" ; +# +UGROUP "FC_47" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_47" SITE "R50C2D" ; +UGROUP "hit_47" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_47_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_47" SITE "R51C4D" ; +UGROUP "ff_en_47" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_47" SITE "R50C27D" ; +# +UGROUP "FC_48" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_48" SITE "R53C2D" ; +UGROUP "hit_48" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_48_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_48" SITE "R54C4D" ; +UGROUP "ff_en_48" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_48" SITE "R53C27D" ; +# +UGROUP "FC_49" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_49" SITE "R55C2D" ; +UGROUP "hit_49" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_49_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_49" SITE "R56C4D" ; +UGROUP "ff_en_49" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_49" SITE "R55C27D" ; +# +UGROUP "FC_50" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_50" SITE "R89C58D" ; +UGROUP "hit_50" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_50_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_50" SITE "R90C60D" ; +UGROUP "ff_en_50" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_50" SITE "R89C83D" ; +# +UGROUP "FC_51" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_51" SITE "R102C58D" ; +UGROUP "hit_51" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_51_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_51" SITE "R103C60D" ; +UGROUP "ff_en_51" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_51" SITE "R102C83D" ; +# +UGROUP "FC_52" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_52" SITE "R111C58D" ; +UGROUP "hit_52" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_52_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_52" SITE "R112C60D" ; +UGROUP "ff_en_52" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_52" SITE "R111C83D" ; +# +UGROUP "FC_53" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_53" SITE "R66C2D" ; +UGROUP "hit_53" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_53_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_53" SITE "R67C4D" ; +UGROUP "ff_en_53" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_53" SITE "R66C27D" ; +# +UGROUP "FC_54" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_54" SITE "R68C2D" ; +UGROUP "hit_54" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_54_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_54" SITE "R69C4D" ; +UGROUP "ff_en_54" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_54" SITE "R68C27D" ; +# +UGROUP "FC_55" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_55" SITE "R71C2D" ; +UGROUP "hit_55" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_55_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_55" SITE "R72C4D" ; +UGROUP "ff_en_55" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_55" SITE "R71C27D" ; +# +UGROUP "FC_56" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_56" SITE "R73C2D" ; +UGROUP "hit_56" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_56_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_56" SITE "R74C4D" ; +UGROUP "ff_en_56" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_56" SITE "R73C27D" ; +# +UGROUP "FC_57" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_57" SITE "R84C2D" ; +UGROUP "hit_57" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_57_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_57" SITE "R85C4D" ; +UGROUP "ff_en_57" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_57" SITE "R84C27D" ; +# +UGROUP "FC_58" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_58" SITE "R86C2D" ; +UGROUP "hit_58" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_58_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_58" SITE "R87C4D" ; +UGROUP "ff_en_58" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_58" SITE "R86C27D" ; +# +UGROUP "FC_59" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_59" SITE "R89C2D" ; +UGROUP "hit_59" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_59_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_59" SITE "R90C4D" ; +UGROUP "ff_en_59" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_59" SITE "R89C27D" ; +# +UGROUP "FC_60" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_60" SITE "R91C2D" ; +UGROUP "hit_60" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_60_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_60" SITE "R92C4D" ; +UGROUP "ff_en_60" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_60" SITE "R91C27D" ; +# +UGROUP "FC_61" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_61" SITE "R102C2D" ; +UGROUP "hit_61" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_61_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_61" SITE "R103C4D" ; +UGROUP "ff_en_61" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_61" SITE "R102C27D" ; +# +UGROUP "FC_62" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_62" SITE "R104C2D" ; +UGROUP "hit_62" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_62_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_62" SITE "R105C4D" ; +UGROUP "ff_en_62" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_62" SITE "R104C27D" ; +# +UGROUP "FC_63" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_63" SITE "R111C2D" ; +UGROUP "hit_63" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_63_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_63" SITE "R112C4D" ; +UGROUP "ff_en_63" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_63" SITE "R111C27D" ; +# +UGROUP "FC_64" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_64" SITE "R113C2D" ; +UGROUP "hit_64" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_64_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_64" SITE "R114C4D" ; +UGROUP "ff_en_64" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_64" SITE "R113C27D" ; + + +############################################################################## +## CHANNEL PLACEMENTS ## +############################################################################## +UGROUP "E&F_ref" BBOX 6 27 + BLKNAME THE_TDC/ReferenceChannel/Channel200; +LOCATE UGROUP "E&F_ref" SITE "R11C129D" ; +UGROUP "E&F_1" BBOX 6 27 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200; +LOCATE UGROUP "E&F_1" SITE "R11C155D" ; +UGROUP "E&F_2" BBOX 6 27 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200; +LOCATE UGROUP "E&F_2" SITE "R15C129D" ; +UGROUP "E&F_3" BBOX 6 27 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200; +LOCATE UGROUP "E&F_3" SITE "R15C155D" ; +UGROUP "E&F_4" BBOX 6 27 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200; +LOCATE UGROUP "E&F_4" SITE "R24C129D" ; +UGROUP "E&F_5" BBOX 6 27 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200; +LOCATE UGROUP "E&F_5" SITE "R24C155D" ; +UGROUP "E&F_6" BBOX 6 27 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200; +LOCATE UGROUP "E&F_6" SITE "R38C129D" ; +UGROUP "E&F_7" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200; +LOCATE UGROUP "E&F_7" SITE "R38C156D" ; +UGROUP "E&F_8" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200; +LOCATE UGROUP "E&F_8" SITE "R42C131D" ; +UGROUP "E&F_9" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200; +LOCATE UGROUP "E&F_9" SITE "R42C156D" ; +UGROUP "E&F_10" BBOX 6 24 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200; +LOCATE UGROUP "E&F_10" SITE "R56C131D" ; +UGROUP "E&F_11" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200; +LOCATE UGROUP "E&F_11" SITE "R56C155D" ; +UGROUP "E&F_12" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200; +LOCATE UGROUP "E&F_12" SITE "R11C84D" ; +UGROUP "E&F_13" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200; +LOCATE UGROUP "E&F_13" SITE "R15C84D" ; +UGROUP "E&F_14" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200; +LOCATE UGROUP "E&F_14" SITE "R24C84D" ; +UGROUP "E&F_15" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200; +LOCATE UGROUP "E&F_15" SITE "R38C84D" ; +UGROUP "E&F_16" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200; +LOCATE UGROUP "E&F_16" SITE "R42C84D" ; +UGROUP "E&F_17" BBOX 6 24 + BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel200; +LOCATE UGROUP "E&F_17" SITE "R60C131D" ; +UGROUP "E&F_18" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel200; +LOCATE UGROUP "E&F_18" SITE "R60C155D" ; +UGROUP "E&F_19" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel200; +LOCATE UGROUP "E&F_19" SITE "R74C131D" ; +UGROUP "E&F_20" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel200; +LOCATE UGROUP "E&F_20" SITE "R74C156D" ; +UGROUP "E&F_21" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel200; +LOCATE UGROUP "E&F_21" SITE "R78C131D" ; +UGROUP "E&F_22" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel200; +LOCATE UGROUP "E&F_22" SITE "R78C156D" ; +UGROUP "E&F_23" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel200; +LOCATE UGROUP "E&F_23" SITE "R92C131D" ; +UGROUP "E&F_24" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel200; +LOCATE UGROUP "E&F_24" SITE "R92C156D" ; +UGROUP "E&F_25" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel200; +LOCATE UGROUP "E&F_25" SITE "R96C131D" ; +UGROUP "E&F_26" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel200; +LOCATE UGROUP "E&F_26" SITE "R96C156D" ; +UGROUP "E&F_27" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel200; +LOCATE UGROUP "E&F_27" SITE "R105C131D" ; +UGROUP "E&F_28" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel200; +LOCATE UGROUP "E&F_28" SITE "R105C156D" ; +UGROUP "E&F_29" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel200; +LOCATE UGROUP "E&F_29" SITE "R92C84D" ; +UGROUP "E&F_30" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel200; +LOCATE UGROUP "E&F_30" SITE "R96C84D" ; +UGROUP "E&F_31" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel200; +LOCATE UGROUP "E&F_31" SITE "R105C84D" ; +UGROUP "E&F_32" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel200; +LOCATE UGROUP "E&F_32" SITE "R78C72D" ; +UGROUP "E&F_33" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel200; +LOCATE UGROUP "E&F_33" SITE "R11C59D" ; +UGROUP "E&F_34" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel200; +LOCATE UGROUP "E&F_34" SITE "R15C59D" ; +UGROUP "E&F_35" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel200; +LOCATE UGROUP "E&F_35" SITE "R24C59D" ; +UGROUP "E&F_36" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel200; +LOCATE UGROUP "E&F_36" SITE "R38C59D" ; +UGROUP "E&F_37" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel200; +LOCATE UGROUP "E&F_37" SITE "R42C59D" ; +UGROUP "E&F_38" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel200; +LOCATE UGROUP "E&F_38" SITE "R11C3D" ; +UGROUP "E&F_39" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel200; +LOCATE UGROUP "E&F_39" SITE "R11C28D" ; +UGROUP "E&F_40" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel200; +LOCATE UGROUP "E&F_40" SITE "R15C3D" ; +UGROUP "E&F_41" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel200; +LOCATE UGROUP "E&F_41" SITE "R15C28D" ; +UGROUP "E&F_42" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel200; +LOCATE UGROUP "E&F_42" SITE "R24C3D" ; +UGROUP "E&F_43" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel200; +LOCATE UGROUP "E&F_43" SITE "R24C28D" ; +UGROUP "E&F_44" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel200; +LOCATE UGROUP "E&F_44" SITE "R38C3D" ; +UGROUP "E&F_45" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel200; +LOCATE UGROUP "E&F_45" SITE "R38C28D" ; +UGROUP "E&F_46" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel200; +LOCATE UGROUP "E&F_46" SITE "R42C3D" ; +UGROUP "E&F_47" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel200; +LOCATE UGROUP "E&F_47" SITE "R42C28D" ; +UGROUP "E&F_48" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel200; +LOCATE UGROUP "E&F_48" SITE "R56C3D" ; +UGROUP "E&F_49" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel200; +LOCATE UGROUP "E&F_49" SITE "R56C28D" ; +UGROUP "E&F_50" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel200; +LOCATE UGROUP "E&F_50" SITE "R92C59D" ; +UGROUP "E&F_51" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel200; +LOCATE UGROUP "E&F_51" SITE "R96C59D" ; +UGROUP "E&F_52" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel200; +LOCATE UGROUP "E&F_52" SITE "R105C59D" ; +UGROUP "E&F_53" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel200; +LOCATE UGROUP "E&F_53" SITE "R60C3D" ; +UGROUP "E&F_54" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel200; +LOCATE UGROUP "E&F_54" SITE "R60C28D" ; +UGROUP "E&F_55" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel200; +LOCATE UGROUP "E&F_55" SITE "R74C3D" ; +UGROUP "E&F_56" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel200; +LOCATE UGROUP "E&F_56" SITE "R74C28D" ; +UGROUP "E&F_57" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel200; +LOCATE UGROUP "E&F_57" SITE "R78C3D" ; +UGROUP "E&F_58" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel200; +LOCATE UGROUP "E&F_58" SITE "R78C28D" ; +UGROUP "E&F_59" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel200; +LOCATE UGROUP "E&F_59" SITE "R92C3D" ; +UGROUP "E&F_60" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel200; +LOCATE UGROUP "E&F_60" SITE "R92C28D" ; +UGROUP "E&F_61" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel200; +LOCATE UGROUP "E&F_61" SITE "R96C3D" ; +UGROUP "E&F_62" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel200; +LOCATE UGROUP "E&F_62" SITE "R96C28D" ; +UGROUP "E&F_63" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel200; +LOCATE UGROUP "E&F_63" SITE "R105C3D" ; +UGROUP "E&F_64" BBOX 6 25 + BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel200; +LOCATE UGROUP "E&F_64" SITE "R105C28D" ; + +############################################################################# +## Coarse counter register placement + +UGROUP "UR_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_1_TheCoarseCounter; +LOCATE UGROUP "UR_Coarse_Counter" SITE R36C134D; #REGION "REGION_UR_CC" ; +UGROUP "LR_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_2_TheCoarseCounter; +LOCATE UGROUP "LR_Coarse_Counter" SITE R85C134D; #REGION "REGION_LR_CC" ; +UGROUP "UL_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_3_TheCoarseCounter; +LOCATE UGROUP "UL_Coarse_Counter" SITE R36C50D; #REGION "REGION_UL_CC" ; +UGROUP "LL_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_4_TheCoarseCounter; +LOCATE UGROUP "LL_Coarse_Counter" SITE R85C50D; #REGION "REGION_LL_CC" ; +UGROUP "Epoch_Counter" + BLKNAME THE_TDC/TheEpochCounter; +LOCATE UGROUP "Epoch_Counter" SITE R36C138D; + +############################################################################# +## Bus Handler Placements + +UGROUP "BusHandlers" + BLKNAME THE_TDC/TheHitCounterBus + BLKNAME THE_TDC/TheStatusRegistersBus + BLKNAME THE_TDC/TheLostHitBus + BLKNAME THE_TDC/TheEncoderStartBus + BLKNAME THE_TDC/TheEncoderFinishedBus; +#LOCATE UGROUP "BusHandlers" REGION BUS + + + + +############################################################################# +## Unimportant Data Lines ## +############################################################################# + +BLOCK NET "THE_TDC/reset_tdc*" ; +BLOCK NET "THE_TDC/hit_in_i_*" ; +#BLOCK PATH TO CELL "THE_TDC/GEN_Channels_*_Channels/Channel200/SimAdderNo_FC/FF_*" ; +#BLOCK NET "THE_TDC/reset_counters_200*" ; +BLOCK PATH TO CELL "THE_TDC/GEN_Channels_*_Channels/sync_q_2*"; + +PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en_i"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels_*_Channels/Channel200/ff_array_en_i"; + +MAXDELAY NET "THE_TDC/ReferenceChannel/hit_buf" 0.600000 nS DATAPATH_ONLY ; +MAXDELAY NET "THE_TDC/GEN_Channels_*_Channels/hit_buf" 0.600000 nS DATAPATH_ONLY ; + +MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset_1" 50 ns; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter_*" TO CELL "THE_TDC/GEN_Channels_*_Channels/Channel200/epoch_cntr_*" 5.000000 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter_*" TO CELL "THE_TDC/ReferenceChannel/Channel200/epoch_cntr_*" 5.000000 X; +#MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/FIFO_ALMOST_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg_*" 2.000000 X; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/FIFO_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg_*" 2.000000 X; +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels_*_Channels/Channel200/FIFO_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg*" 2.000000 X; +#MULTICYCLE FROM CELL "THE_TDC/GEN_Channels_*_Channels/Channel200/FIFO_ALMOST_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg*" 2.000000 X; + diff --git a/tdc_releases/tdc_v1.6/trb3_periph.vhd b/tdc_releases/tdc_v1.6/trb3_periph.vhd new file mode 100644 index 0000000..e074371 --- /dev/null +++ b/tdc_releases/tdc_v1.6/trb3_periph.vhd @@ -0,0 +1,809 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + + +entity trb3_periph is + port( + --Clocks + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + --Trigger + TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out + TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out + --Serdes + CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible + CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems + SERDES_INT_TX : out std_logic_vector(3 downto 0); + SERDES_INT_RX : in std_logic_vector(3 downto 0); + SERDES_ADDON_TX : out std_logic_vector(11 downto 0); + SERDES_ADDON_RX : in std_logic_vector(11 downto 0); + --Inter-FPGA Communication + FPGA5_COMM : inout std_logic_vector(11 downto 0); + --Bit 0/1 input, serial link RX active + --Bit 2/3 output, serial link TX active + --Connection to ADA AddOn + SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only + INP : in std_logic_vector(63 downto 0); + --DAC_SDO : in std_logic; + DAC_SDI : out std_logic; + DAC_SCK : out std_logic; + DAC_CS : out std_logic_vector(4 downto 1); + --Flash ROM & Reboot + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_DIN : out std_logic; + FLASH_DOUT : in std_logic; + PROGRAMN : out std_logic; --reboot FPGA + --Misc + TEMPSENS : inout std_logic; --Temperature Sensor + CODE_LINE : in std_logic_vector(1 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + SUPPL : in std_logic; --terminated diff pair, PCLK, Pads + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + attribute syn_useioff of CODE_LINE : signal is false; + attribute syn_useioff of TRIGGER_LEFT : signal is false; + attribute syn_useioff of TRIGGER_RIGHT : signal is false; + --important signals + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_DIN : signal is true; + attribute syn_useioff of FLASH_DOUT : signal is true; + attribute syn_useioff of FPGA5_COMM : signal is true; + attribute syn_useioff of TEST_LINE : signal is true; + attribute syn_useioff of INP : signal is false; + attribute syn_useioff of SPARE_LINE : signal is true; + --attribute syn_useioff of DAC_SDO : signal is true; + attribute syn_useioff of DAC_SDI : signal is true; + attribute syn_useioff of DAC_SCK : signal is true; + attribute syn_useioff of DAC_CS : signal is true; + +end entity; + + +architecture trb3_periph_arch of trb3_periph is + --Constants + constant REGIO_NUM_STAT_REGS : integer := 3; + constant REGIO_NUM_CTRL_REGS : integer := 3; + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + --Clock / Reset + signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal clk_125_i : std_logic; -- 125 MHz, via Clock Manager and bypassed PLL + signal clk_20_i : std_logic; -- clock for calibrating the tdc, 20 MHz, via Clock Manager and internal PLL + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + --Media Interface + signal med_stat_op : std_logic_vector (1*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med_data_out : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); + signal med_dataready_out : std_logic; + signal med_read_out : std_logic; + signal med_data_in : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); + signal med_dataready_in : std_logic; + signal med_read_in : std_logic; + + --LVL1 channel + signal timing_trg_received_i : std_logic; + signal trg_data_valid_i : std_logic; + signal trg_timing_valid_i : std_logic; + signal trg_notiming_valid_i : std_logic; + signal trg_invalid_i : std_logic; + signal trg_type_i : std_logic_vector(3 downto 0); + signal trg_number_i : std_logic_vector(15 downto 0); + signal trg_code_i : std_logic_vector(7 downto 0); + signal trg_information_i : std_logic_vector(23 downto 0); + signal trg_int_number_i : std_logic_vector(15 downto 0); + signal trg_multiple_trg_i : std_logic; + signal trg_timeout_detected_i : std_logic; + signal trg_spurious_trg_i : std_logic; + signal trg_missing_tmg_trg_i : std_logic; + signal trg_spike_detected_i : std_logic; + + --Data channel + signal fee_trg_release_i : std_logic; + signal fee_trg_statusbits_i : std_logic_vector(31 downto 0); + signal fee_data_i : std_logic_vector(31 downto 0); + signal fee_data_write_i : std_logic; + signal fee_data_finished_i : std_logic; + signal fee_almost_full_i : std_logic; + + --Slow Control channel + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); + + --RegIO + signal regio_addr_out : std_logic_vector (15 downto 0); + signal regio_read_enable_out : std_logic; + signal regio_write_enable_out : std_logic; + signal regio_data_out : std_logic_vector (31 downto 0); + signal regio_data_in : std_logic_vector (31 downto 0); + signal regio_dataready_in : std_logic; + signal regio_no_more_data_in : std_logic; + signal regio_write_ack_in : std_logic; + signal regio_unknown_addr_in : std_logic; + signal regio_timeout_out : std_logic; + + --Timer + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_ticks : std_logic_vector(1 downto 0); + + --Flash + signal spictrl_read_en : std_logic; + signal spictrl_write_en : std_logic; + signal spictrl_data_in : std_logic_vector(31 downto 0); + signal spictrl_addr : std_logic; + signal spictrl_data_out : std_logic_vector(31 downto 0); + signal spictrl_ack : std_logic; + signal spictrl_busy : std_logic; + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(5 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_ack : std_logic; + signal spidac_read_en : std_logic; + signal spidac_write_en : std_logic; + signal spidac_data_in : std_logic_vector(31 downto 0); + signal spidac_addr : std_logic_vector(4 downto 0); + signal spidac_data_out : std_logic_vector(31 downto 0); + signal spidac_ack : std_logic; + signal spidac_busy : std_logic; + + signal dac_cs_i : std_logic_vector(3 downto 0); + signal dac_sck_i : std_logic; + signal dac_sdi_i : std_logic; + + signal hitreg_read_en : std_logic; + signal hitreg_write_en : std_logic; + signal hitreg_addr : std_logic_vector(6 downto 0); + signal hitreg_data_out : std_logic_vector(31 downto 0); + signal hitreg_data_ready : std_logic; + signal hitreg_invalid : std_logic; + + signal srb_read_en : std_logic; + signal srb_write_en : std_logic; + signal srb_addr : std_logic_vector(6 downto 0); + signal srb_data_out : std_logic_vector(31 downto 0); + signal srb_data_ready : std_logic; + signal srb_invalid : std_logic; + + signal lhb_read_en : std_logic; + signal lhb_write_en : std_logic; + signal lhb_addr : std_logic_vector(6 downto 0); + signal lhb_data_out : std_logic_vector(31 downto 0); + signal lhb_data_ready : std_logic; + signal lhb_invalid : std_logic; + + signal esb_read_en : std_logic; + signal esb_write_en : std_logic; + signal esb_addr : std_logic_vector(6 downto 0); + signal esb_data_out : std_logic_vector(31 downto 0); + signal esb_data_ready : std_logic; + signal esb_invalid : std_logic; + + signal efb_read_en : std_logic; + signal efb_write_en : std_logic; + signal efb_addr : std_logic_vector(6 downto 0); + signal efb_data_out : std_logic_vector(31 downto 0); + signal efb_data_ready : std_logic; + signal efb_invalid : std_logic; + + signal tdc_ctrl_read : std_logic; + signal last_tdc_ctrl_read : std_logic; + signal tdc_ctrl_write : std_logic; + signal tdc_ctrl_addr : std_logic_vector(2 downto 0); + signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); + signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); + signal tdc_ctrl_reg : std_logic_vector(5*32-1 downto 0); + + signal spi_bram_addr : std_logic_vector(7 downto 0); + signal spi_bram_wr_d : std_logic_vector(7 downto 0); + signal spi_bram_rd_d : std_logic_vector(7 downto 0); + signal spi_bram_we : std_logic; + + --TDC + signal hit_in_i : std_logic_vector(64 downto 1); + signal logic_analyser_i : std_logic_vector(15 downto 0); + +begin +--------------------------------------------------------------------------- +-- Reset Generation +--------------------------------------------------------------------------- + + GSR_N <= pll_lock; + + THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + + +--------------------------------------------------------------------------- +-- Clock Handling +--------------------------------------------------------------------------- + THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_RIGHT, + CLKOP => clk_100_i, + CLKOK => clk_200_i, + LOCK => pll_lock + ); + + -- generates hits for calibration uncorrelated with tdc clk + THE_CALIBRATION_PLL : pll_in125_out20 + port map ( + CLK => CLK_GPLL_LEFT, + CLKOP => clk_20_i, + CLKOK => clk_125_i, + LOCK => open); + +--------------------------------------------------------------------------- +-- The TrbNet media interface (to other FPGA) +--------------------------------------------------------------------------- + THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp + generic map( + SERDES_NUM => 1, --number of serdes in quad + EXT_CLOCK => c_NO, --use internal clock + USE_200_MHZ => c_YES, --run on 200 MHz clock + USE_125_MHZ => c_NO, + USE_CTC => c_NO + ) + port map( + CLK => clk_200_i, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => med_data_out, + MED_PACKET_NUM_IN => med_packet_num_out, + MED_DATAREADY_IN => med_dataready_out, + MED_READ_OUT => med_read_in, + MED_DATA_OUT => med_data_in, + MED_PACKET_NUM_OUT => med_packet_num_in, + MED_DATAREADY_OUT => med_dataready_in, + MED_READ_IN => med_read_out, + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => SERDES_INT_RX(2), + SD_RXD_N_IN => SERDES_INT_RX(3), + SD_TXD_P_OUT => SERDES_INT_TX(2), + SD_TXD_N_OUT => SERDES_INT_TX(3), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => FPGA5_COMM(0), + SD_LOS_IN => FPGA5_COMM(0), + SD_TXDIS_OUT => FPGA5_COMM(2), + -- Status and control port + STAT_OP => med_stat_op, + CTRL_OP => med_ctrl_op, + STAT_DEBUG => med_stat_debug, + CTRL_DEBUG => (others => '0') + ); + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + --regio_hardware_version_i <= x"9100" & addOn_type_i & edge_type_i & tdc_channel_no_i & x"0"; + + --addOn_type_i <= x"0"; -- x"0" - ADA AddOn version 1 + -- -- x"1" - ADA AddOn version 2 + -- -- x"2" - multi purpose test AddOn + -- -- x"3" - SFP hub AddOn + -- -- x"4" - Wasa AddOn + --edge_type_i <= x"0"; -- x"0" - single edge + -- -- x"1" - double edge + -- -- x"4" - has spi interface + -- -- x"8" - double edge on consecutive channels + --tdc_channel_no_i <= x"6"; -- 2^n channels + + THE_ENDPOINT : trb_net16_endpoint_hades_full_handler + generic map( + REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg + REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + BROADCAST_SPECIAL_ADDR => x"48", + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), + REGIO_HARDWARE_VERSION => x"91000460", -- regio_hardware_version_i, + REGIO_INIT_ADDRESS => x"f305", + REGIO_USE_VAR_ENDPOINT_ID => c_YES, + CLOCK_FREQUENCY => 100, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 13, --13 + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-(maximal 2**12) + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + MED_DATAREADY_OUT => med_dataready_out, -- open, -- + MED_DATA_OUT => med_data_out, -- open, -- + MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, -- open, -- + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, + LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, + LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, + LVL1_INVALID_TRG_OUT => trg_invalid_i, + + LVL1_TRG_TYPE_OUT => trg_type_i, + LVL1_TRG_NUMBER_OUT => trg_number_i, + LVL1_TRG_CODE_OUT => trg_code_i, + LVL1_TRG_INFORMATION_OUT => trg_information_i, + LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, + + --Information about trigger handler errors + TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i, + TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i, + TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i, + TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i, + TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i, + + --Response from FEE + FEE_TRG_RELEASE_IN(0) => fee_trg_release_i, + FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i, + FEE_DATA_IN => fee_data_i, + FEE_DATA_WRITE_IN(0) => fee_data_write_i, + FEE_DATA_FINISHED_IN(0) => fee_data_finished_i, + FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i, + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, + REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, + REGIO_STAT_REG_IN => stat_reg, --start 0x80 + REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 + REGIO_STAT_STROBE_OUT => stat_reg_strobe, + REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), + + BUS_ADDR_OUT => regio_addr_out, + BUS_READ_ENABLE_OUT => regio_read_enable_out, + BUS_WRITE_ENABLE_OUT => regio_write_enable_out, + BUS_DATA_OUT => regio_data_out, + BUS_DATA_IN => regio_data_in, + BUS_DATAREADY_IN => regio_dataready_in, + BUS_NO_MORE_DATA_IN => regio_no_more_data_in, + BUS_WRITE_ACK_IN => regio_write_ack_in, + BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + BUS_TIMEOUT_OUT => regio_timeout_out, + ONEWIRE_INOUT => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + + TIME_GLOBAL_OUT => global_time, + TIME_LOCAL_OUT => local_time, + TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, + TIME_TICKS_OUT => timer_ticks, + + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => open, + STAT_DEBUG_2 => open, + STAT_DEBUG_DATA_HANDLER_OUT => open, + STAT_DEBUG_IPU_HANDLER_OUT => open, + STAT_TRIGGER_OUT => open, + CTRL_MPLEX => (others => '0'), + IOBUF_CTRL_GEN => (others => '0'), + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open, + DEBUG_LVL1_HANDLER_OUT => open + ); + + timing_trg_received_i <= TRIGGER_LEFT; --TRIGGER_RIGHT; -- + common_stat_reg <= (others => '0'); + stat_reg <= (others => '0'); + +--------------------------------------------------------------------------- +-- AddOn +--------------------------------------------------------------------------- + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : trb_net16_regio_bus_handler + generic map( + PORT_NUMBER => 9, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 3, others => 0) + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + + --Bus Handler (SPI CTRL) + BUS_READ_ENABLE_OUT(0) => spictrl_read_en, + BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, + BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, + BUS_ADDR_OUT(0*16) => spictrl_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, + BUS_DATAREADY_IN(0) => spictrl_ack, + BUS_WRITE_ACK_IN(0) => spictrl_ack, + BUS_NO_MORE_DATA_IN(0) => spictrl_busy, + BUS_UNKNOWN_ADDR_IN(0) => '0', + --Bus Handler (SPI Memory) + BUS_READ_ENABLE_OUT(1) => spimem_read_en, + BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, + BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, + BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, + BUS_DATAREADY_IN(1) => spimem_ack, + BUS_WRITE_ACK_IN(1) => spimem_ack, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', + --Bus Handler (SPI DAC) + BUS_READ_ENABLE_OUT(2) => spidac_read_en, + BUS_WRITE_ENABLE_OUT(2) => spidac_write_en, + BUS_DATA_OUT(2*32+31 downto 2*32) => spidac_data_in, + BUS_ADDR_OUT(2*16+4 downto 2*16) => spidac_addr, + BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATA_IN(2*32+31 downto 2*32) => spidac_data_out, + BUS_DATAREADY_IN(2) => spidac_ack, + BUS_WRITE_ACK_IN(2) => spidac_ack, + BUS_NO_MORE_DATA_IN(2) => spidac_busy, + BUS_UNKNOWN_ADDR_IN(2) => '0', + --HitRegisters + BUS_READ_ENABLE_OUT(3) => hitreg_read_en, + BUS_WRITE_ENABLE_OUT(3) => hitreg_write_en, + BUS_DATA_OUT(3*32+31 downto 3*32) => open, + BUS_ADDR_OUT(3*16+6 downto 3*16) => hitreg_addr, + BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(3*32+31 downto 3*32) => hitreg_data_out, + BUS_DATAREADY_IN(3) => hitreg_data_ready, + BUS_WRITE_ACK_IN(3) => '0', + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => hitreg_invalid, + --Status Registers + BUS_READ_ENABLE_OUT(4) => srb_read_en, + BUS_WRITE_ENABLE_OUT(4) => srb_write_en, + BUS_DATA_OUT(4*32+31 downto 4*32) => open, + BUS_ADDR_OUT(4*16+6 downto 4*16) => srb_addr, + BUS_ADDR_OUT(4*16+15 downto 4*16+7) => open, + BUS_TIMEOUT_OUT(4) => open, + BUS_DATA_IN(4*32+31 downto 4*32) => srb_data_out, + BUS_DATAREADY_IN(4) => srb_data_ready, + BUS_WRITE_ACK_IN(4) => '0', + BUS_NO_MORE_DATA_IN(4) => '0', + BUS_UNKNOWN_ADDR_IN(4) => srb_invalid, + --Encoder Start Registers + BUS_READ_ENABLE_OUT(5) => esb_read_en, + BUS_WRITE_ENABLE_OUT(5) => esb_write_en, + BUS_DATA_OUT(5*32+31 downto 5*32) => open, + BUS_ADDR_OUT(5*16+6 downto 5*16) => esb_addr, + BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open, + BUS_TIMEOUT_OUT(5) => open, + BUS_DATA_IN(5*32+31 downto 5*32) => esb_data_out, + BUS_DATAREADY_IN(5) => esb_data_ready, + BUS_WRITE_ACK_IN(5) => '0', + BUS_NO_MORE_DATA_IN(5) => '0', + BUS_UNKNOWN_ADDR_IN(5) => esb_invalid, + --Fifo Write Registers + BUS_READ_ENABLE_OUT(6) => efb_read_en, + BUS_WRITE_ENABLE_OUT(6) => efb_write_en, + BUS_DATA_OUT(6*32+31 downto 6*32) => open, + BUS_ADDR_OUT(6*16+6 downto 6*16) => efb_addr, + BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open, + BUS_TIMEOUT_OUT(6) => open, + BUS_DATA_IN(6*32+31 downto 6*32) => efb_data_out, + BUS_DATAREADY_IN(6) => efb_data_ready, + BUS_WRITE_ACK_IN(6) => '0', + BUS_NO_MORE_DATA_IN(6) => '0', + BUS_UNKNOWN_ADDR_IN(6) => efb_invalid, + --Lost Hit Registers + BUS_READ_ENABLE_OUT(7) => lhb_read_en, + BUS_WRITE_ENABLE_OUT(7) => lhb_write_en, + BUS_DATA_OUT(7*32+31 downto 7*32) => open, + BUS_ADDR_OUT(7*16+6 downto 7*16) => lhb_addr, + BUS_ADDR_OUT(7*16+15 downto 7*16+7) => open, + BUS_TIMEOUT_OUT(7) => open, + BUS_DATA_IN(7*32+31 downto 7*32) => lhb_data_out, + BUS_DATAREADY_IN(7) => lhb_data_ready, + BUS_WRITE_ACK_IN(7) => '0', + BUS_NO_MORE_DATA_IN(7) => '0', + BUS_UNKNOWN_ADDR_IN(7) => lhb_invalid, + --TDC config registers + BUS_READ_ENABLE_OUT(8) => tdc_ctrl_read, + BUS_WRITE_ENABLE_OUT(8) => tdc_ctrl_write, + BUS_DATA_OUT(8*32+31 downto 8*32) => tdc_ctrl_data_in, + BUS_ADDR_OUT(8*16+2 downto 8*16) => tdc_ctrl_addr, + BUS_ADDR_OUT(8*16+15 downto 8*16+3) => open, + BUS_TIMEOUT_OUT(8) => open, + BUS_DATA_IN(8*32+31 downto 8*32) => tdc_ctrl_data_out, + BUS_DATAREADY_IN(8) => last_tdc_ctrl_read, + BUS_WRITE_ACK_IN(8) => tdc_ctrl_write, + BUS_NO_MORE_DATA_IN(8) => '0', + BUS_UNKNOWN_ADDR_IN(8) => '0', + + STAT_DEBUG => open + ); + + PROC_TDC_CTRL_REG : process + variable pos : integer; + begin + wait until rising_edge(clk_100_i); + pos := to_integer(unsigned(tdc_ctrl_addr))*32; + tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos); + last_tdc_ctrl_read <= tdc_ctrl_read; + if tdc_ctrl_write = '1' then + tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in; + end if; + end process; + +--------------------------------------------------------------------------- +-- SPI / Flash +--------------------------------------------------------------------------- + + THE_SPI_MASTER : spi_master + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_READ_IN => spictrl_read_en, + BUS_WRITE_IN => spictrl_write_en, + BUS_BUSY_OUT => spictrl_busy, + BUS_ACK_OUT => spictrl_ack, + BUS_ADDR_IN(0) => spictrl_addr, + BUS_DATA_IN => spictrl_data_in, + BUS_DATA_OUT => spictrl_data_out, + -- SPI connections + SPI_CS_OUT => FLASH_CS, + SPI_SDI_IN => FLASH_DOUT, + SPI_SDO_OUT => FLASH_DIN, + SPI_SCK_OUT => FLASH_CLK, + -- BRAM for read/write data + BRAM_A_OUT => spi_bram_addr, + BRAM_WR_D_IN => spi_bram_wr_d, + BRAM_RD_D_OUT => spi_bram_rd_d, + BRAM_WE_OUT => spi_bram_we, + -- Status lines + STAT => open + ); + + -- data memory for SPI accesses + THE_SPI_MEMORY : spi_databus_memory + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_ACK_OUT => spimem_ack, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + -- state machine connections + BRAM_ADDR_IN => spi_bram_addr, + BRAM_WR_D_OUT => spi_bram_wr_d, + BRAM_RD_D_IN => spi_bram_rd_d, + BRAM_WE_IN => spi_bram_we, + -- Status lines + STAT => open + ); + + -- dac spi entity + DAC_SPI : spi_ltc2600 + port map ( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_READ_IN => spidac_read_en, + BUS_WRITE_IN => spidac_write_en, + BUS_BUSY_OUT => spidac_busy, + BUS_ACK_OUT => spidac_ack, + BUS_ADDR_IN => spidac_addr, + BUS_DATA_IN => spidac_data_in, + BUS_DATA_OUT => spidac_data_out, + -- SPI connections + SPI_CS_OUT(15 downto 4) => open, + SPI_CS_OUT(3 downto 0) => dac_cs_i, + SPI_SDI_IN => '0', + SPI_SDO_OUT => dac_sdi_i, + SPI_SCK_OUT => dac_sck_i); + + DAC_CS <= dac_cs_i; + DAC_SDI <= dac_sdi_i; + DAC_SCK <= dac_sck_i; + +--------------------------------------------------------------------------- +-- Reboot FPGA +--------------------------------------------------------------------------- + THE_FPGA_REBOOT : fpga_reboot + port map( + CLK => clk_100_i, + RESET => reset_i, + DO_REBOOT => common_ctrl_reg(15), + PROGRAMN => PROGRAMN + ); + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_GREEN <= not med_stat_op(9); + LED_ORANGE <= not med_stat_op(10); + LED_RED <= not INP(0); + LED_YELLOW <= not med_stat_op(11); + +--------------------------------------------------------------------------- +-- Test Connector - Logic Analyser +--------------------------------------------------------------------------- + + TEST_LINE <= logic_analyser_i; + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + + THE_TDC : TDC + generic map ( + CHANNEL_NUMBER => 65, -- Number of TDC channels + CONTROL_REG_NR => 5, -- Number of control regs - higher than 8 check tdc_ctrl_addr + TDC_VERSION => "001" & x"51") -- TDC version number + port map ( + RESET => reset_i, + CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement + CLK_READOUT => clk_100_i, -- Clock for the readout + REFERENCE_TIME => timing_trg_received_i, -- Reference time input + HIT_IN => hit_in_i(64 downto 1), -- Channel start signals + HIT_CALIBRATION => clk_20_i, -- Hits for calibrating the TDC + TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width + TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width + -- + -- Trigger signals from handler + TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet + VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet + VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet + INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet + TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet + SPIKE_DETECTED_IN => trg_spike_detected_i, + MULTI_TMG_TRG_IN => trg_multiple_trg_i, + SPURIOUS_TRG_IN => trg_spurious_trg_i, + -- + TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package + TRG_CODE_IN => trg_code_i, -- + TRG_INFORMATION_IN => trg_information_i, -- + TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package + -- + --Response to handler + TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal + TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc + DATA_OUT => fee_data_i, -- tdc data + DATA_WRITE_OUT => fee_data_write_i, -- data valid signal + DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal + -- + --Hit Counter Bus + HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe + HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe + HCB_ADDR_IN => hitreg_addr, -- bus address + HCB_DATA_OUT => hitreg_data_out, -- bus data + HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe + HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr + --Status Registers Bus + SRB_READ_EN_IN => srb_read_en, -- bus read en strobe + SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe + SRB_ADDR_IN => srb_addr, -- bus address + SRB_DATA_OUT => srb_data_out, -- bus data + SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe + SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr + --Encoder Start Registers Bus + ESB_READ_EN_IN => esb_read_en, -- bus read en strobe + ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe + ESB_ADDR_IN => esb_addr, -- bus address + ESB_DATA_OUT => esb_data_out, -- bus data + ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe + ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr + --Fifo Write Registers Bus + EFB_READ_EN_IN => efb_read_en, -- bus read en strobe + EFB_WRITE_EN_IN => efb_write_en, -- bus write en strobe + EFB_ADDR_IN => efb_addr, -- bus address + EFB_DATA_OUT => efb_data_out, -- bus data + EFB_DATAREADY_OUT => efb_data_ready, -- bus data ready strobe + EFB_UNKNOWN_ADDR_OUT => efb_invalid, -- bus invalid addr + --Lost Hit Registers Bus + LHB_READ_EN_IN => lhb_read_en, -- bus read en strobe + LHB_WRITE_EN_IN => lhb_write_en, -- bus write en strobe + LHB_ADDR_IN => lhb_addr, -- bus address + LHB_DATA_OUT => lhb_data_out, -- bus data + LHB_DATAREADY_OUT => lhb_data_ready, -- bus data ready strobe + LHB_UNKNOWN_ADDR_OUT => lhb_invalid, -- bus invalid addr + -- + LOGIC_ANALYSER_OUT => logic_analyser_i, + CONTROL_REG_IN => tdc_ctrl_reg); + + -- For single edge measurements + hit_in_i <= INP; + --hit_in_i <= (others => timing_trg_received_i); + + ---- For ToT Measurements + --Gen_Hit_In_Signals : for i in 1 to 32 generate + -- hit_in_i(i*2-1) <= INP(i-1); + -- hit_in_i(i*2) <= not INP(i-1); + --end generate Gen_Hit_In_Signals; + +-- !!!!! IMPORTANT !!!!! Don't forget to set the REGIO_HARDWARE_VERSION !!!!! +end architecture; diff --git a/tdc_releases/tdc_v1.6/trbnet_constraints.lpf b/tdc_releases/tdc_v1.6/trbnet_constraints.lpf new file mode 100644 index 0000000..38622c4 --- /dev/null +++ b/tdc_releases/tdc_v1.6/trbnet_constraints.lpf @@ -0,0 +1,46 @@ +################################################################# +# Reset Nets +################################################################# +GSR_NET NET "reset_i"; + +################################################################# +# Locate Serdes and media interfaces +################################################################# +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; + +REGION "MEDIA_UPLINK" "R105C109D" 10 22; +REGION "REGION_SPI" "R2C109D" 15 22 DEVSIZE; + +LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; +LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; + +LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; + +MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 30 ns; + + +#Jan: Placement of TrbNet components (at least, most of them) +REGION "REGION_TRBNET" "R35C109D" 70 22 DEVSIZE; +#UGROUP "TrbNet" BBOX 77 27 +# BLKNAME THE_ENDPOINT +# BLKNAME THE_ENDPOINT/THE_ENDPOINT +#LOCATE UGROUP "TrbNet" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_2_gentermbuf_termbuf/TRMBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_INTERNAL_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/MPLEX/MUX_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/HUBLOGIC_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/RegIO_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; diff --git a/tdc_releases/tdc_v1.6/up_counter.vhd b/tdc_releases/tdc_v1.6/up_counter.vhd new file mode 100644 index 0000000..1d8a887 --- /dev/null +++ b/tdc_releases/tdc_v1.6/up_counter.vhd @@ -0,0 +1,41 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity up_counter is + + generic ( + NUMBER_OF_BITS : positive); + port ( + CLK : in std_logic; + RESET : in std_logic; + COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0); + UP_IN : in std_logic); + +end up_counter; + +architecture up_counter of up_counter is + + signal counter : std_logic_vector (NUMBER_OF_BITS-1 downto 0); + attribute syn_preserve : boolean; + attribute syn_preserve of counter : signal is true; + +begin + + COUNTER_PROC : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + counter <= (others => '0'); + elsif UP_IN = '1' then + counter <= counter + 1; + else + counter <= counter; + end if; + end if; + end process COUNTER_PROC; + + COUNT_OUT <= counter; + +end up_counter; diff --git a/tdc_test/compile_constraints.pl b/tdc_test/compile_constraints.pl index 491a12f..98cf0e9 100755 --- a/tdc_test/compile_constraints.pl +++ b/tdc_test/compile_constraints.pl @@ -8,6 +8,6 @@ my $TOPNAME = "trb3_periph"; #Name of top-level entity #create full lpf file system("cp ../base/trb3_periph_mainz.lpf diamond/$TOPNAME.lpf"); -system("cat ../tdc_releases/tdc_v1.5/trbnet_constraints.lpf >> diamond/$TOPNAME.lpf"); -system("cat ../tdc_releases/tdc_v1.5/tdc_constraints.lpf >> diamond/$TOPNAME.lpf"); +system("cat ../tdc_releases/tdc_v1.5.1/trbnet_constraints.lpf >> diamond/$TOPNAME.lpf"); +system("cat ../tdc_releases/tdc_v1.5.1/tdc_constraints.lpf >> diamond/$TOPNAME.lpf");