From: Adrian Weber Date: Fri, 13 May 2022 08:16:53 +0000 (+0200) Subject: Trb5sc for CBM RICH with 240MHz interface, internal CTS, calib, TDC. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5dcedceae7faf60c97735c4f9e3f106b916edbe1;p=trb5sc.git Trb5sc for CBM RICH with 240MHz interface, internal CTS, calib, TDC. --- diff --git a/cbmrich/create_project.pl b/cbmrich/create_project.pl new file mode 100755 index 0000000..93fed0a --- /dev/null +++ b/cbmrich/create_project.pl @@ -0,0 +1,350 @@ +#!/usr/bin/env perl + +# small straight-forward program to create a diamond project based on the standard trb3 project structure +# execute the script with the current project as working directory. if existing the current project may be altered. +# take care ! + + +use strict; +use warnings; +use Data::Dumper; +use File::Copy; +use Term::ANSIColor; +use Cwd 'abs_path'; + +sub parsePRJ { + my $input = shift; + my $options = {}; + my @files = (); + + open FH, "<" , $input; + while (my $line = ) { + chomp $line; + if ($line =~ m/^\s*set_option -([^\s]+)\s+"?([^"]+)"?\s*$/) { + $options->{$1} = $2; + } + + if ($line =~ m/^\s*add_file -(vhdl|verilog|fpga_constraint)( -lib "?([^"\s]+)"?|)? "?([^"]+)"?\s*$/g) { + push @files, [$3, $4]; + } + + + } + + close FH; + + return ($options, \@files); +} + +sub generateLDF { + my $prj_file = shift; + my $options = shift; + my $files = shift; + + my $path = '../'; + + open FH, ">", $prj_file; + + my $device = $options->{'part'} . $options->{'speed_grade'} . $options->{'package'}; + $device =~ s/_/\-/g; + + my $prj_title = $options->{'top_module'}; + $prj_title =~ s/trb3_(central|periph)_(.+)/$2/; + + my $def_impl = $options->{'top_module'}; + + my $inclPath = $options->{'include_path'}; + $inclPath = '' if (!$inclPath); + $inclPath =~ s/\{(.*)\}$/$1/; + #$inclPath = abs_path($inclPath) if ($inclPath); + + print FH "\n"; + print FH "\n"; + print FH " \n"; + print FH " \n"; + print FH " \n"; + print FH " \n"; + + + my $lpf_included = 0; + + for my $filer (@{$files}) { + my $file = $filer->[1]; + my $lib = $filer->[0]; + my $suffix = $file; + my $fpath = $path . $file; + $suffix =~ s/^.*\.([^.]+)$/$1/g; + if ("vhd" eq $suffix) { + print FH " \n"; + } elsif ("v" eq $suffix) { + print FH " \n"; + } elsif ("lpf" eq $suffix) { + print FH " \n"; + $lpf_included = 1; + } elsif ("fdc" eq $suffix) { + print FH " \n"; + } else { + print "WARNING: Could not determine type of input file $file. Not included!\n"; + } + } + + print FH " \n"; + print FH " \n"; + print FH "\n"; + + close FH; + + if (!$lpf_included) { + print color "red bold"; + print "WARNING: No lpf included. You won't be able to load this project with diamond. Check your compile_constraints.pl script!\n"; + print color "reset"; + } +} + +sub generateSTY { + my $file = shift; + open FH, ">", $file; + print FH < + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +STY +; + close FH; +} + +# Search project file + my @prj_files = glob('*.prj'); + die "No .prj found? Is the current working dir the project root?" if 0 == scalar @prj_files; + die "Multiple prj-files found. This is not supported by this tool." if 1 < scalar @prj_files; + my $input = shift @prj_files; + + print "NOTE: Use $input as input file\n"; + +# parse PRJ file + my ($options, $files) = parsePRJ $input; + +# create dir if necessary + mkdir 'project' unless (-e 'project'); + +# create workdir + if (-e './compile_constraints.pl') { + my $workdir = 'project/' . $options->{'top_module'}; + my $lpffile = $workdir . '/' . $options->{'top_module'} . ".lpf"; + + print "NOTE: execute ./compile_constraints.pl $workdir\n"; + system "./compile_constraints.pl $workdir"; + + if(-e $lpffile) { + rename $lpffile, 'project/' . $options->{'top_module'} . '.lpf'; + push @$files, ['work', 'project/' . $options->{'top_module'} . '.lpf']; + } else { + print "WARNING: compile_constraints did not generate $lpffile. Please include the necessary contraint files manually\n"; + } + } else { + print "No ./compile_constraints.pl script found. Please make sure, the workdir contains all links and constraint-files\n"; + } + +# generate ldf + my $project_file = 'project/' . $options->{'top_module'} . '.ldf'; + if (-e $project_file) {move $project_file, $project_file . '.backup'}; + generateLDF $project_file, $options, $files; + print "NOTE: LDF generated\n"; + +# generate strategy file + unless (-e 'project/auto_strat.sty') { + generateSTY 'project/auto_strat.sty'; + print "NOTE: STY generated\n"; + } + + + +print "\nNOTE: The version.vhd file is neither generated nor updated when building in diamond.\n"; +print "\nUse command-line compilation to create a version file.\n"; +print "\nDone. Execute \n> diamond $project_file\nto open the project\n"; diff --git a/cbmrich/trb5sc_cbmrich.lpf b/cbmrich/trb5sc_cbmrich.lpf index 5ad9471..b6be2d6 100644 --- a/cbmrich/trb5sc_cbmrich.lpf +++ b/cbmrich/trb5sc_cbmrich.lpf @@ -11,12 +11,12 @@ FREQUENCY PORT CLK_200 200 MHz; FREQUENCY PORT CLK_125 125 MHz; FREQUENCY PORT CLK_EXT 200 MHz; -FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; -FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 240 MHz; +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 240 MHz; # FREQUENCY NET "med_stat_debug[11]" 200 MHz; -FREQUENCY NET "med2int_0.clk_full" 200 MHz; -# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; +#FREQUENCY NET "med2int_0.clk_full" 240 MHz; + FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 240 MHz; BLOCK PATH TO PORT "LED*"; diff --git a/cbmrich/trb5sc_cbmrich.prj b/cbmrich/trb5sc_cbmrich.prj index 64173de..11a145b 100644 --- a/cbmrich/trb5sc_cbmrich.prj +++ b/cbmrich/trb5sc_cbmrich.prj @@ -66,7 +66,9 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" #Basic Infrastructure add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" -add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../dirich/cores/ecp5/pll_200_240.vhd" +#add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler_240.vhd" add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" @@ -145,7 +147,8 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync_240.vhd" ######################################### @@ -164,11 +167,21 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" #add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" #channel 1, SFP -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" ########################################## -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" -add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" +######################################### +#240MHz +#channel 0, backplane +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/240MHz/chan0_0/serdes_sync_0.vhd" + +#channel 1, SFP +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/240MHz/chan0_1/serdes_sync_0.vhd" +########################################## + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/240MHz/pcs_240.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/240MHz/pcs2_240.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/240MHz/serdes_sync_0_softlogic.v" #TrbNet Endpoint diff --git a/cbmrich/trb5sc_cbmrich.vhd b/cbmrich/trb5sc_cbmrich.vhd index 5ac9c97..3ecd028 100644 --- a/cbmrich/trb5sc_cbmrich.vhd +++ b/cbmrich/trb5sc_cbmrich.vhd @@ -88,7 +88,7 @@ architecture arch of trb5sc_cbmrich is attribute syn_keep : boolean; attribute syn_preserve : boolean; - signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic; + signal clk_sys, clk_full, clk_full_osc, clk_cal, ref_clk_240 : std_logic; signal GSR_N : std_logic; signal reset_i : std_logic; signal clear_i : std_logic; @@ -212,8 +212,6 @@ architecture arch of trb5sc_cbmrich is signal link_stat_in_reg : std_logic; - - begin trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); @@ -222,7 +220,7 @@ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and no --------------------------------------------------------------------------- -- Clock & Reset Handling --------------------------------------------------------------------------- - THE_CLOCK_RESET : entity work.clock_reset_handler + THE_CLOCK_RESET : entity work.clock_reset_handler_240 port map( CLOCK_IN => CLK_200, RESET_FROM_NET => med2int(INTERFACE_NUM).stat_op(13), --make_reset --Used on combiner_CTS @@ -238,6 +236,7 @@ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and no REF_CLK_OUT => clk_full, SYS_CLK_OUT => clk_sys, RAW_CLK_OUT => clk_full_osc, + REF_CLK_240_OUT => ref_clk_240, DEBUG_OUT => debug_clock_reset ); @@ -275,14 +274,14 @@ THE_CAL_PLL : entity work.pll_in125_out50 -- TrbNet Uplink --------------------------------------------------------------------------- - THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync_240 generic map( SERDES_NUM => 0, IS_SYNC_SLAVE => c_YES ) port map( - CLK_REF_FULL => clk_full_osc, --med2int(1).clk_full, - CLK_INTERNAL_FULL => clk_full_osc, + CLK_REF_FULL => med2int(INTERFACE_NUM).clk_full, + CLK_INTERNAL_FULL => ref_clk_240, SYSCLK => clk_sys, RESET => reset_i, CLEAR => clear_i,